Tcitsmcn40ggpmplla1 Guide

TCITSMCN40GGPMPLLA1_guide 1

True Circuits, Inc. General-Purpose PLL for TSMC CLN40G 40nm

Guidelines and Specifications

Revision 1.1

*** True Circuits, Inc. Confidential ***

Copyright (C) 2000-2011 True Circuits, Inc. All rights reserved.

Purpose

This document describes a General-Purpose PLL design in the TSMC CLN40G 40nm0.9V IC process. This PLL design is a flexible core library macro thatperforms frequency synthesis within the noisy environment of large ASICdesigns. Low-jitter operation is a primary concern in these large devicesthat often contain multiple phase-locked loops, RAM, and hundreds ofhigh current / high speed output buffers.

Due to the high frequency capability of the VCO at the minimum PVT corner,internal high performance dividers are included to eliminate false lockingseen with external divider architectures. The PLL has dedicated analogVDDA and VSSA supply pads which are preferred for best jitter performance.

General-Purpose PLL

The General-Purpose PLL is designed to multiply an input clock signalby an integer between 1 and 64. It also provides basic deskewfunctionality. It contains a 1-16 divider at the reference clock input,a 1-64 divider in the internal feedback path, and a 1-16 divider at theoutput. The output is 50% duty cycle for all output divider values.The -3dB bandwidth is adjustable over a factor of 4 range.

Contents

This documents contains the following sections. It is highly recommendedthat the user read each section carefully. - General-Purpose PLL Specifications - Line Item Definitions of Specifications - PLL Default Settings - Modes Of Operation - PLL Output Frequency - Frequency Programming Calculation Script - PLL Bandwidth Adjustment - PLL Bypass Mode - PLL Test Mode - PLL Behavioral Modeling - PLL Feedback Path - PLL Feedback Delay - Minimizing Jitter - Timing Budgets - PLL Power-up and Reset Operation - Timing Relationships for PLL Digital Signal Inputs - PLL Cycle Slip Detection - Cascaded PLL Configurations - Chip Integration Issues - PLL Analog Supplies - Chip Layout Guidelines - Package and Board Guidelines - PLL Bench/Performance Testing Procedure - PLL Production Testing Guidelines - Additional Notes - Addendum to Line Item Definitions of Specifications - Definitions - Deskew PLL Application Notes


General-Purpose PLL Specifications

Performance Specifications - Divided reference frequency range 13.3MHz - 1.7GHz - /1 output frequency range 340MHz - 1.7GHz (VCO output internally divided by 2 for 50% DC) - Reference divider values 1-16 - Feedback divider values 1-64 - Output divider values 1-16 - /1 output multiples of div. reference 1-64 - Bandwidth adjustment div. range 1-64 - Feedback signal delay (max) NF/1.7GHz - Output duty cycle (nom, tol) 50%, +/-2% - Static phase error (max) +/-1.25% div. reference cycle - Period jitter (P-P) (max) +/-3% output cycle - Input-to-output jitter (P-P) (max) +/-1.5% div. reference cycle (jitter numbers are worst-case estimates with supply and substrate noise levels below -- actual results will be better)

- Power dissipation (nom) 2.5mA @ 850MHz (/1 output) - Reset pulse width (min) 5us - Reset /1 output frequency range 10MHz - 100MHz - Lock time (min allowed) 500 div. reference cycles (actual lock time will be much smaller) - Freq. overshoot (full-/half-) (max) 40%/50% - Area (including isolation) (max) 0.020mm^2

- Number of PLL supply pkg. pins 1 VDDA, 1 VSSA (preferred) - Low freq. supply noise est. (P-P) (max) 10% VDDA - Low freq. sub. noise est. (P-P) (max) 10% VDDA - Ref. input jitter (long-term, P-P) (max) 2% div. reference cycle - Reference/Feedback H/L pulse width (min) 150ps

- Process technology TSMC CLN40G 40nm - Supply voltage (VDD, VDDA) (nom, tol) 0.9V, +/-10% - Junction temperature (nom, min, max) 70C, -40C, 125C

Pin List - VDDA - Analog VDD - VSSA - Analog VSS - VDD - Digital VDD (connected to core VDD) - VSS - Digital VSS (connected to core VSS) - RCLK - Reference clock input - FCLK - Feedback clock input - CLKOUT - PLL clock output - CLKR[0:3] - NR = CLKR[3:0] + 1, CLKR[0] is LSB - CLKF[0:5] - NF = CLKF[5:0] + 1, CLKF[0] is LSB - CLKOD[0:3] - OD = CLKOD[3:0] + 1, CLKOD[0] is LSB - BWADJ[0:5] - Loop BW adj.: NB = BWADJ[5:0] + 1, BWADJ[0] is LSB - RESET - Reset when high (also clears NR and NF counters) - PWRDN - Power down when high - INTFB - Select internal feedback path when high rather than FCLK (not shown in diagrams below) - BYPASS - Reference-to-output bypass when high - TEST - Reference-to-counters-to-output bypass when high - RFSLIP - Reference cycle slip output (CLKOUT frequency high) - FBSLIP - Feedback cycle slip output (CLKOUT frequency low)


Simplified Block Diagrams

- Normal/BYPASS Mode (TEST=0) (The multiplexers for TEST mode are not shown.)

+-----------------------------------------------------------+

| | | +-----+ +-----+ +-----+ | FCLK --|---->| |----->| | | | +-----+ 0|\ | | | /NF | | PFD | ... | VCO |----->| |-->| |---|-CLKOUT CLKF --|-/-->| | /-->| | | | | /OD | | | | | 6 +-----+ | +-----+ +-----+ /-->| | | | | | | | +-----+ | | | | | | 1| | | | /------------C------------------------C------------>| | | | | | | |/ | | | +-----+ | | ^ | RCLK --|-+-->| |--/ | | | | | /NR | | | | CLKR --|-/-->| | | | | | 4 +-----+ | | | | | | | CLKOD--|-/-------------------------------------/ | | | 4 | | | | | BWADJ--|-/-- ... | | | 6 | | | | | RESET--|-- ... | | | | | PWRDN--|-- ... | | | | | BYPASS-|------------------------------------------------------/ | | | TEST --|-- (=0) ... --|-RFSLIP | | VDDA --| ... --|-FBSLIP | | VSSA --| | | | VDD --| | | | VSS --| | +-----------------------------------------------------------+


- TEST Mode (TEST=1) (When NR=1, NF=1, or OD=1, outputs do not toggle.)

+-----------------------------------------------------------+

| | | | | | | +-----+ | FCLK --|-- ... /------>| | +-----+ | | | | /NF |----------------->| |---------|-CLKOUT CLKF --|-/--------/ /-->| | | /OD | | | 6 | +-----+ /-->| | | | | | +-----+ | | | | | | | | | | | | | | +-----+ | | | RCLK --|---->| |--/ | | | | /NR | | | CLKR --|-/-->| | | | | 4 +-----+ | | | | | CLKOD--|-/-------------------------------------/ | | 4 | | | BWADJ--|-/-- ... | | 6 | | | RESET--|-- ... | | | PWRDN--|-- ... | | | BYPASS-|-- ... | | | TEST --|-- (=1) ... --|-RFSLIP | | VDDA --| ... --|-FBSLIP | | VSSA --| | | | VDD --| | | | VSS --| | +-----------------------------------------------------------+

Line Item Definitions of Specifications

- Divided reference frequency range: Allowed frequency range at the phase-frequency detector (PFD) input.

- /1 output frequency range: Frequency range of the PLLs output clock when the output divider (OD) is set to /1.

- Reference divider values: Allowed divider settings for the PLLs reference divider.

- Feedback (integer or fractional) divider values: Allowed divider settings for the PLLs feed-back divider.

- Output divider values: Allowed divider settings for the PLLs output divider.

- /1 output multiples of div. reference: Provides feed-back multiply range.


- Bandwidth adjustment div. range: Allowed closed-loop 3-dB bandwidth (Fbw_3dB) adjustment range.

- Feedback signal delay (max): Maximum permitted delay in the feedback path from output clock pin of PLL to feed-back clock input pin of the PLL. This specification applies only to de-skew (DS) PLLs.

- Output duty cycle (nom, tol): Duty cycle of the PLLs output clock.

- Static phase error (max): Static phase error between a rising edge of the input reference clock and the corresponding edge of the PLLs feedback clock.

- Period jitter (P-P) (max): The difference between maximum and minimum measured cycle times of the PLLs output clock.

- Input-to-output jitter (P-P) (max): The difference between maximum and minimum measured offset between the input reference clock edge and the corresponding PLL output clock edge.

- Power dissipation (nom): Total power (analog + digital) dissipated by the PLL when locked.

- Reset pulse width (min): Minimum required pulse-width of the PLL reset signal.

- Reset /1 output frequency range: Frequency range of the PLL output while PLL is in reset state and its output divider (OD) is set to /1.

- Lock time (min allowed): Maximum number of divided reference clock cycles it will take the PLL to achieve phase/frequency lock once reset is de-asserted.

- Freq. overshoot (full-/half-) (max): Maximum output frequency overshoot during lock acquisition as a percentage of the final, locked, PLL output frequency. "full" refers to the measurement of one full cycle (rising edge to following rising edge). "half" refers to the measurement of one half cycle (rising edge to following falling edge or falling edge to following rising edge, whichever happens to be smaller).

- Area (including isolation) (max): Total layout area occupied by the PLL including built in isolation.

- Number of PLL supply pkg. pins: Number of supply pins dedicated to PLL.

- Low freq. supply noise est. (P-P) (max): Maximum allowed low-frequency peak-to-peak noise voltage on PLL supply pins as a percentage of nominal supply voltage.

- Low freq. sub. noise est. (P-P) (max): Maximum allowed low-frequency peak-to-peak substrate noise voltage in the vicinity of the PLL as a percentage of nominal supply voltage.

- Ref. input jitter (long-term, P-P) (max): Maximum allowed long-term jitter on the input reference clock.

- Reference/Feedback H/L pulse width (min):


Minimum allowed pulse-width (rising edge to following falling edge or falling edge to following rising edge, whichever happens to be smaller) on the input reference clock.

- Process technology: Process technology in which PLL is developed and characterized.

- Supply voltage (VDD, VDDA) (nom, tol): Supply voltage (digital and analog) ranges over which the PLLs performance specifications are defined.

- Junction temperature (nom, min, max): Device junction temperature range over which the PLLs performance specifications are defined.

* For additional details please refer in the "Addendum to Line Item Definitions of Specifications" section.

PLL Default Settings

All PLL input control pins should be controllable through some sort ofregister. TCI does not recommended the hard-wiring of any controlpins. If it is necessary to hard-wire any control pins TCI should beconsulted for feedback. In addition, the following PLL controlpins should be set at their default values.

Default values: NB = (! INTFB)? (NF * OD * Next) : NF

TCI should be consulted prior to programming the above controls tonon-default settings.


Modes Of Operation

The PLL can operate in several modes:1. Locked The positive edges of the PLL feedback and reference signals are phase aligned in normal operation.2. Reset (RESET=1) The PLL outputs a fixed free-running frequency in the range of 10MHz to 100MHz for a divide by 1 output depending on the specific PLL type.3. Power-down (PWRDN=1) All analog circuitry in the PLL is turned off so as to only dissipate leakage current. The digital dividers are not affected.4. Bypass (BYPASS=1) The reference input is bypassed directly to the outputs.5. Test (TEST=1) The reference input drives all dividers cascaded one after the other for production testing.

PLL Output Frequency

The relationship between the PLL output frequency and the referencefrequency in normal locked operation depends on the divider inputs. Alldivider inputs are binary encoded where an input of N typically causesthe divider to divide by N+1.

The output frequency Fout at CLKOUT is related to the reference frequencyFref by: Fout = Fref * NF / NR * Nextwhen INTFB is low, and by: Fout = Fref * NF / NR / ODwhen INTFB is high.where Next is the total external feedback division and OD is in thefeedback path (otherwise divide by OD in equation). Note that with INTFB low, the totaldivision in the feedback path (NF * OD * Next), including both the internalfeedback divider and any output/external feedback division, must be lessthan or equal to 64 under all operating conditions. This total feedbackdivision limit is necessary in order to prevent the stability of the PLLfrom begin compromised. To compensate for any output/external feedbackdivision, NB should be set to the total division in the feedback path(NF * OD * Next with INTFB=0 and NF with INTFB=1).

The divided reference clock is the internal clock that follows thereference divider, and has a frequency Fref/NR.

PLL counters:1. CLKR: A 4-bit bus that selects the values 1-16 for the reference divider (NR)

NR = CLKR[3:0] + 1

Example: /1 pgm 0000 /4 pgm 0011 /8 pgm 0111

2. CLKF: A 6-bit bus that selects the values 1-64 for the multiplication factor (NF)

NF = CLKF[5:0] + 1

Example: X1 pgm 000000 X2 pgm 000001 X64 pgm 111111

3. CLKOD: A 4-bit bus that selects the values 1-16 for the post VCO


divider (OD)

OD = CLKOD[3:0] + 1


2. BWADJ: A 6-bit bus that selects the values 1-64 for the bandwidth divider (NB)

NB = BWADJ[5:0] + 1


Frequency Programming Calculation Script

The program "TCITSMCN40GGPMPLLA1_calc.csh" can be used to calculate PLLfrequency settings given input parameters. The script must be run onUNIX systems and have access to the C compiler. The script contains asimple C program that will be automatically compiled upon execution.

The script does perform range checking and should return optimalsettings, but should be used with care in that its results are onlyas good as the supplied input.

Examples: TCITSMCN40GGPMPLLA1_calc.csh -u

TCITSMCN40GGPMPLLA1_calc.csh 30e3 500e6

TCITSMCN40GGPMPLLA1_calc.csh 30e3 500e6 1e-6

PLL Bandwidth Adjustment

The loop bandwidth (BW) of the PLL can be adjusted using BWADJ[5:0].The bandwidth is given by: BW = nom_BW*sqrt(NB_base / NB)where nom_BW is approximately given by: nom_BW = Fref / (NR*20)and Fref is the reference clock frequency. The damping factor (D) isapproximately given by: D = nom_D*sqrt(NB_base / NB)where nom_D is approximately 1. Because the damping factor changes withbandwidth settings, the bandwidth is practically limited to: nom_BW/sqrt(2) < BW < nom_BW*sqrt(2)in order to limit the damping factor range to 0.7 - 1.4. The -3dBbandwidth (Fbw_3dB) is approximately given by: Fbw_3dB = 2.4 * nom_BW * (NB_base / NB)NB_base is NF * OD * Next for INTFB=0 and NF for INTFB=1.The recommended setting for NB is NB_base, which will yield the nominalbandwidth. Note that nom_BW and nom_D are chosen to result in optimalPLL loop dynamics.

PLL Bypass Mode

The PLL has a bypass mode (BYPASS=1) where the reference clock (RCLK)is bypassed directly to the PLL output (CLKOUT) with no clock multiplicationor deskew operation.

BYPASS controls the PLLs output multiplexer that selects either the


reference clock or the clock from the PLLs output divider. If the PLLis locked and BYPASS is asserted, then the overall power dissipationwill be similar to what one would see under functional mode operation.However, if both power-down and bypass are asserted, then the overallpower dissipation will be due mainly to a few buffers toggling in thebypass path. The power dissipation in this case will be very small.

PLL Test Mode

The PLL has a divider test mode (TEST=1) to allow for rapid productiontesting of the dividers in the PLLs without using the internal analogcircuitry. This mode (TEST=1) overrides the bypass mode (BYPASS=1).

The output frequency Fout at CLKOUT is related to the reference frequencyFref by: Fout = Fref / NR / NF / OD

The dividers typically implement an N+1 divide given an input of N. Theyare actually synchronous counters where the output is the carry-out signal.In divider test mode, the dividers are cascaded with carry-out signalof one driving the input clock of the next. When dividing by 1, thecarry-out signal is fixed high. Thus, the PLL outputs will not togglein divider test mode if any of the dividers have an input of 1.

To perform rapid vector testing on the counters, they must be set to aknown state so that the PLL output transitions can be tracked and comparedagainst a predefined sequence.The PLL reference and feedback counters can be synchronously reset byasserting RESET in a specified vector sequence.

PLL Behavioral Modeling

For system level verification a Verilog based behavioral model of thePLL is provided. The Verilog model predicts the behavior of the PLLclosely but not perfectly. The model requires a sufficiently finetime-step to model locking behavior correctly. In steady state, theVerilog model does not model any jitter that might be present in thereal PLL. To speed up simulation, during startup, the Verilog model issetup to achieve lock much faster than would be the case with the realPLL. After changes to the clock source frequency and/or runtime dividervalue, the number of cycles required by the Verilog model for re-lockis also less than the case with the real PLL. The real lock-timespecification can be found in the "PLL Specifications" section. Upondeassertion of PLL reset, the PLL will proceed towards a locked state.During this transition, the PLL may output a few cycles that are higherin frequency than the final target frequency. This frequency overshootmodelled by Verilog may be different from the real overshoot. The realfrequency overshoot specification can be found in the "PLL FrequencyOvershoot" section below. In general, the chip operation should notdepend on the behavior PLL output clock until the PLL is completelylocked.

PLL Feedback Path

The feedback path for the PLL must be able to propagate a clock frequencythat is higher then the final PLL output frequency. This extra frequencyrange is required because while the PLL is in the process of locking,it can temporarily overshoot above the final output frequency. Thistemporary overshoot can cause the output clock period to be as much as40% smaller than the final output clock period and the output clock highor low time to be as much as 50% smaller than the final output clockhigh or low time. If the feedback path is unable to propagate all clockedges at these higher frequencies for a particular desired operatingfrequency, the PLL will be unable to lock.


In general, the PLL feedback path should be able to propagate clock edgesat least 5us before the PLL reset signal is deasserted.

PLL Feedback Delay

The feedback delay between the PLL output and PLL feedback input mustbe limited to avoid compromising the stability of the PLL. The maximumfeedback delay that can be tolerated has a square root dependence on thereference frequency as listed in the table.

The feedback divider (NF) inside the PLL has a zero effective insertiondelay. Thus, no matching division is needed in the reference path. Thisdivider is useful if the clock distribution output must be phase-lockedto a multiple of the reference with zero added skew.

See the "Deskew PLL Application Notes" section for more information onissues with the feedback path.

Minimizing Jitter

The amount of period jitter observed will depend on the actual noiselevel on the PLL supplies and chip substrate and noise frequency content.It will increase roughly linearly with the output period and will beroughly independent of multiplication factor or bandwidth setting.

To minimize the overall output jitter, the PLLs should be operated as closeas possible to the maximum frequency before any output division. Thusif some division is necessary for the PLL, it should be performed by theOD divider rather than in a reference divider to maximize the VCO frequency.Since the PLL power dissipation increases with increased VCO frequency,there will be a trade-off between jitter performance and power dissipation.

The overall tracking jitter can be minimized by increasing the dividedreference frequency. The overall period jitter can be minimized by usingan NF value that is as small as possible.

In addition, to minimize the overall output jitter, the analog suppliesshould connect to separate dedicated pads.

The PLL will work beyond the specified maximum frequencies, but thejitter performance will be degraded.

Timing Budgets

The PLL specifications, along with those from the clock distributionnetwork and the clocked elements, play a key part in chip timing budgets.When calculating the timing budgets, one may need to consider theworst-case static phase offset, duty cycle error, period jitter,and possibly tracking jitter from the PLL, the worst-case skew and jitterfrom the clock distribution, and the worst-case setup, hold, andclock-to-output times for the clocked elements.

Period jitter is significant for setup time or cycle based pathbudgets but not for hold time or race path budgets. Clock distributionjitter is significant for setup time budgets but less for hold timebudgets, depending on the clock distribution structure. Clock distributionskew is important for both setup time and hold time budgets. Staticphase offset along with tracking jitter is significant for the setup andhold time budgets of latches or registers receiving data at the chipinterface. Finally, duty cycle error must be considered for latch-baseddesigns where the timing of both clock edges is significant.

PLL Power-up and Reset Operation


In order to guarantee that the PLL will lock properly after startup ora counter change, follow the reset sequence described below. In practice,since the feedback path is enclosed, it will probably always oscillatefrom PLL power-up with a reasonable reference input frequency (not toohigh). However, this behavior should not be relied upon. When RESETis asserted, the PLL goes to a frequency between 10MHz and 100MHz dependingon the PLL type. This frequency is not well controlled. Upon deassertionof RESET, the PLL output frequency will slew toward lock. The figurebelow is a timing diagram that shows the Power-Up and RESET sequence.

---+

PWRDN | +-------------------------------------------------------------

^

| | t1

+------------------+

RESET | | ----------+ +-----------------------------------

^ ^ ^

||| | | | t2 t3 t4

t1 represents the later of the times when VDDA and VDD have reached theirsteady state levels or when PWRDN is deasserted. PWRDN can be tied lowby default.

The time relationship between t1 and t2 is arbitrary -- t1 can occurbefore t2 and vice versa. However, t3 must occur at least 5us afterboth t1 and t2. Normally, t2 will occur after t1, in which case t_rst(t3-t2) must be at least 5us. t2 can occur at time 0.

If the PLL settings are changed while RESET is asserted, the settingsshould be changed least 5us before t3 (where RESET is deasserted).

Once RESET is deasserted at t3, wait at least 500 divided reference clockcycles to ensure PLL has locked (t_lock interval). At t4 the PLL willbe locked.

Timing Relationships for PLL Digital Signal Inputs

The following describes the timing relationships for the digital signalinputs to the PLL.

The timing relationship for PLL reset (RESET) is as follows: - should be asserted on power up - deassertion of PLL reset should occur 5us after any feedback counter values change (CLKF[] or external feedback counter inputs) - chip reset should be held for 500 divided reference clock (RCLK/NR) cycles to insure that the PLL is completely locked

The timing relationship for feedback counter values (CLKF[], etc.)is as follows: - changes should occur 5us before PLL reset is deasserted

The timing relationship for PLL power down (PWRDN) is as follows: - can be asserted any time - deassertion should be followed by an assertion of PLL reset, etc.

The typical chip startup sequence (non-testing mode), controlled by anexternal power-on reset signal, is as follows: - assert chip reset and PLL reset (RESET) based on power-on reset signal assertion


- set feedback counter values if not static - power-on reset signal deasserts - if power-on reset signal is not guaranteed to be at least 5us wide after voltages have stabilized, then count 5us based on the reference clock (RCLK) - deassert PLL reset (RESET) - count 500 divided reference clock (RCLK/NR) cycles - deassert chip reset

The following block diagram should implement reset signals for the typicalchip startup sequence:

power-on reset | +-----------+

| aset | | | 5us 0 --| D DFF Q |-------- PLL RESET | | | +------------------+ | clk | | count | +-----------+ | | | RCLK --| clk COUNTER co |---------/ | | | arst | +------------------+

| power-on reset

power-on reset | +-----------+

| aset | | | 500*NR+5us 0 --| D DFF Q |-------- chip reset | | | +------------------+ | clk | | count | +-----------+ | | | RCLK --| clk COUNTER co |---------/ | | | arst | +------------------+

| power-on reset

arst - asynchronous reset (for counter) aset - asynchronous set (for FF)

PLL Cycle Slip Detection

A cycle slip occurs when the edge mis-alignment between the rising edgesof reference and feedback clocks at the PFD input exceeds one reference(or feedback) clock cycle.

The PLL does not have a classic analog lock detection circuit. Suchcircuits are weak points of PLL designs because they have double sidedconstraints. If their threshold is too low, they may never signal lockin a noisy environment. If their threshold is too high, they may signallock too early. Instead, TCI provides two lower-level signals (FBSLIPand RFSLIP) which detect cycle slips between the VCO and reference clocks.Cycle slip detection circuits are desirable because they signal anout-of-lock condition immediately, not after some large number of cycles,caused by the low bandwidth of a classic lock detection circuit. Thesecycle slip output can be used to construct a highly effective lock-detectmechanism as described below.


RFSLIP goes active for one or more divided feedback VCO cycles when thephase detector misses a divided reference cycle, i.e. when the VCO isrunning too fast. FBSLIP goes active for one or more divided referencecycles when the phase detector misses a divided feedback VCO cycle, i.e.when the VCO is running too slow. Neither signal is synchronized to thePLL output clocks.

A "PLL lock" signal is usually used for one of two purposes:

1. Determining when to start the chip. We suggest using the previously described reference cycle count instead.

2. Determining if the PLL has lost lock because of a reference frequency change or some other exceptional condition. In this case, the RFSLIP and FBSLIP signals can provide a low-latency way to detect a loss of lock.

Since neither of these signals is synchronized to a PLL output clock,they must first be sampled by meta-stable-hardened circuitry beforebeing processed by logic. We suggest a meta-stable-hard SR latch followedby two meta-stable-hard D flip-flops, as shown below:

+-------+ CLK ---+-----------+ | | +----+ v v | RFSLIP|-->| | +------------+ +-------+ +-------+ | | | OR |---->|S | | CLK | | CLK | | FBSLIP|-->| | | SR-latch Q|-->|D DFF Q|-->|D DFF Q|--\ | | +----+ /->|R MHARD | | MHARD | | MHARD | | | PLL | | +------------+ +-------+ +-------+ | +-------+ | | | +------------------------------------+ | | | | | \--|ACK Out-Of-Lock Resolution Logic DET|


reference frequency. A second strategy is to use a single PLL in afractional N configuration, provided that the dither jitter is not toolarge. A third strategy is to use cascaded PLLs, each PLL using smallNR and NF divider values to form a low value ratio, but collectivelyimplementing a high value ratio. This configuration has the advantageof avoiding low divided reference frequencies that can increase long-termjitter. The long-term jitter will be dominated by the PLL operating atthe lowest bandwidth.

The key issue with cascaded PLL configurations is preventing jitteramplification. Each PLL will amplify jitter a little which occurs atnoise frequencies near the PLL bandwidth. Cascading two or more PLLsoperating with the same loop bandwidth can lead to increased jitteramplification. To avoid jitter amplification, the PLLs should operateat different loop bandwidths. Specifically, any PLL in the cascadedchain will attenuate jitter amplification from PLLs that precede it whichare operating at higher bandwidths. Ideally, the lowest bandwidth PLLshould be last in the chain, but since some net clock multiplication iscommonly needed, which necessitates a low bandwidth, the first PLL willtypically have the lowest bandwidth. It is desirable to make the bandwidthat least a factor of two or four apart.

Chip Integration Issues

- Distributed MUXes

Distributed multiplexers can be used to avoid undesired cross talk betweenmultiplexed clock signals. Cross talk can lead to increased jitter inthe resultant output clock signal. The idea behind distributed multiplexingis to gate each clock signal at its source and combine the gated clocksat the output destination, each performed with a gain stage for noiseisolation. The destination may be shared with one of the sources. Bygating the clock signals at their sources, cross talk or feed throughat the point where the clock signals are combined is minimized.

- - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Source 1 Location | Output Location +-----\ | Clock_1 ---| | | NAND |O----------+ Sel_1 ---| | | +-----/ | | +-----\ +---| | - - - - - - - - - - - - - - | | NAND |O--- Clock_Out +---| | +-----\ | | +-----/ Clock_2 ---| | | | NAND |O----------+ Sel_2 ---| | +-----/ | Source 2 Location | - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

- Clock Distribution

TCI recommends that the reference clock be treated as carefully as anyother clock signal on the chip. Ideally, the reference clock pad shouldbe located close to the PLL. When the pad cannot be close, the latencyshould be minimized using wide shielded wires and large inverting buffers.To minimize threshold modulation of the insertion delay, the slew timeat the input of every gate in the transmission path should be less thanor equal to that of an inverter driving fanout of 6. Lateral shieldingof the clock wires should be employed, and the clock should be routed


to curtail the number of signals crossing over and under it in adjacentmetal.

For example, consider an RCLK path of 10mm from ESD pad to PLL in atypical 130nm process. We recommend that the path be cut into 7 sectionseach 1.5mm long. Each section should be routed using 2um wide upper-layermetal and 0.5um VSSD shields on either side spaced by 0.5um, and drivenby a 80um/40um inverter. 5x6 via arrays should be used when switchinglayers. Suppose that each wire segment would have a resistance of 32ohms and a capacitance of 838 fF. The 30%-70% worst-case slew time seenat the end of each wire segment would be about 55ps, and the worst-casestage delay would be about 75 ps. The insertion delay of the RCLK pathis then 525 ps. If we assume that +/-5% dynamic supply variation willcause +/-5% delay modulation, this insertion delay will give 53 ps ofpeak-to-peak jitter, which is sufficiently low to drive a 380 MHz referenceclock from a crystal reference. This example is intended to illustratethat, while it is possible to transmit a clock across a fair amount ofsilicon, it requires work that can otherwise be avoided.

Please note that a 80um/40um inverter is 4x larger than the maximuminverter size in widely available standard cell libraries. To reducethe local power supply drop from the inverter, it should have a narrowaspect ratio (so that it connects to many metal straps in the powergrid), and it should have decoupling capacitance adjacent to the invertercell.

PLL Analog Supplies

The PLLs VDDA and VSSA supplies should be connected to dedicated padsnear the PLL supplied by an off-chip filter network. This configurationwill result in the specified jitter performance.

When multiple PLLs are used, each PLL should have its own VDDA and VSSApads or bumps which are isolated from those of other PLLs. Also, eachPLL should have its own package pins and filter network. However, ifnecessary, the PLL analog supplies can be shorted in the package whenthis short leads to a lower inductance and better isolated solution.

There are no power sequencing requirements for VDDA and VDD from thePLL. However, the supply pads used for the VDDA and VDD supplies mayimpose power sequencing requirements. Please consult the supply paddocumentation.

Chip Layout Guidelines

PLL integration layout is primarily concerned with three things: substratenoise, supply resistance, and analog supply noise coupling. The PLL isan analog system, which means that compromising any of these things willcompromise the jitter performance of the PLL.

- ESD Protection

The PLL has no built-in ESD protection. The customer must provideprovide standard ESD protection for all PLL power, input, and outputchip pins.

- Substrate Noise

The PLL block is ideally located on the edge of the die adjacent to theESD structures for the PLLs analog supply pads. It should not be placednear groups of output drivers, but rather near input receivers, powersupply pads, or test pins where the substrate is likely to have the leastnoise.

- Supply Resistance


The total resistance from the analog supply bumps or pads to the PLLpins should be 1 ohm or less for each of VSSA and VDDA. All of the PLLsanalog supply pins should be connected with the same or greater widthmetal in multiple metal layers, and should be routed directly to the PLLsanalog supply pads. The recommended practice is to stack VDDA and VSSAon adjacent metal layers, and to use more than one metal layer for eachof these supplies, so that the total metal width for each supply is 30um.Note that for C4 (flip-chip) packaged chips, the wires between the ESDstructures and the bumps add to the resistance of the wires between thePLL and the ESD structure, making it somewhat more challenging to ensure1 ohm or less for each of VSSA and VDDA.

Total resistance from digital supply bumps or pads to the digital supplypins at the edge of the PLL should be 2 ohms or less for each of VSS andVDD. Additionally, resistance between the PLLs digital supply pins andthe source/drains of the clock tree buffers should be less than 2 ohms.This low resistance connection is important so that the output signalswitches supply domains inside the PLL where the edge rates are controlledto minimize added jitter. Generally, the PLLs digital supply wiresshould be connected with at least 5um wide wires in one metal layer.

- Analog Supply Noise Coupling

This PLL is designed to shield sensitive internal nodes from outsideinfluences with guard rings and a mat of VDDA/VSSA metal. However, theanalog supplies are themselves sensitive to external noise. In general,the ONLY thing that can shield the analog supplies from aggressor signalsis space. Digital VDD/VSS, in particular, are aggressor signals. However,the realities of chip integration will often preclude blank space inmany particular contexts listed below, and so this section is a guideto making the inevitable compromises.

For wire-bonded chips with pad frames, the pads adjacent to the PLLanalog supplies should be either quiescent I/Os (e.g. test pins not usedin production) or other voltage supplies. On C4 packaged parts, similarplacement constraints for the ESD structures should be observed.

The ESD structures for VSSA and VDDA should be isolated from other ESDstructures in the same way that ESD structures for I/Os with differingsupply voltages are normally isolated, even when the PLL analog supplyvoltage is the same as the adjacent supply voltage. Usually this isolationis done with a diode cell between the PLL supply ESD structures and theadjacent ESD structures to break the supply rings.

Note that the VSSA and VDDA supplies are directly connected to transistorgates inside the PLL. Some I/O libraries include an "analog power supply"pad that has no ESD break-down path to the main chip supplies, whichassumes that the VSSA and VDDA nets do not connect directly to transistorgates. Do not use these ESD pads with a TCI PLL.

- C4 (Flip-Chip) Packaging

..................... .....................................

. (I/O Cells) . . . ..................... . .

. -- . . -- -- --

.........../ \.... . / \ / \ / \ . | | . .| | | | | | ..........| |... .|SPARE | | JTAG | | VDD | . JTAG \ / . . \ / \ / \ / ............ -- ..... . -- -- --

: diode break : . . ..................... . PLL . . VDDA .====. . ............ -- ..... . -- -- --

. VSSA / \ .====. / \ / \ / \ ..........| |... .| | | | | | : diode|break | : .| VSSA | | VDDA | | VSS |


...........\ /.... . \ / \ / \ / . -- . . -- -- --

..................... . .

. . . .

..................... .....................................

. .

............ -- ..... -- -- --

. / \ . / \ / \ / \ ..........| |... | | | | | | . | | . | | | | | | ...........\ /.... \ / \ / \ / . -- . -- -- --

.....................

Example of C4 chip floor plan with PLL.

On C4 (flip-chip) packaged chips, the PLL usually ends up below severalbump positions (see figure). Noise or signals on these bumps will couplevertically into the analog power supply shields over the PLL. In orderof desirability, these bumps should be assigned to:

- Analog VDDA/VSSA - Unused or spare - Static (unchanging) digital inputs (i.e. configuration or test pins) - PLL output clocks (NOT reference clocks) - Digital VDD/VSS

It is particularly desirable to place analog VDDA/VSSA over the PLL andclose to the ESD structures, since those bumps will couple to the digitalpower grid if they are placed anywhere else. It is better to have thePLL close to the ESD structures, so that the power routes are short andthe analog supply resistance can be low, than to have the PLL far fromthe ESD structures in order to avoid placement under bumps.

Metal on the redistribution layer over the PLL should only be used toreach bumps over the PLL.

If, despite the above suggestions, bumps or redistribution layer routesover the PLL are assigned to changing digital signals, those aggressorsmust be shielded. A single layer of digital VDD or VSS under the aggressorshould be used to shield the PLL and its analog supplies from the effectsof rail-to-rail swings. Digital VSS is the preferred shield supply (andanalog VDDA and VSSA are to be avoided entirely). This single layershould be on the HIGHEST metal layer possible and only under the aggressor,not over the whole PLL. Multiple layers of shielding are counterproductivesince they just bring the noise on the digital supplies closer to thePLL and its analog supplies.

- PLL Placement in I/O Pad Ring Area

Placement of the PLL in the I/O pad ring area is possible, but not apreferred approach due to the increased noise coupling from I/O supplies.

If the PLL is placed in the I/O pad ring area, no signal pads or powerI/O pads should be placed over the PLL area. I/O filler cells can beplaced over the PLL area in order to connect the power and ESDbreak-down rails and to maintain proper ESD protection. The fillercells will result in power routing over the PLL area. To reduce noisecoupling into the PLL these filler cells should use top metal layerfor routing the power rails. If feasible, to further reduce noisecoupling into the PLL, a core VSS shield should be placed over the PLLin order to isolate it from noise on the power rails routed over it.This shield should be in the highest level metal below that used toconnect the power rails. Other than the power rail routing in thefiller cells and the VSS shield underneath, only floating metal fillshould be placed over the PLL area. To minimize noise coupling andseries interconnect resistance, I/O pads adjacent to the PLL should beassigned to the PLLs VDDA/VSSA pins. The PLLs core VDD/VSS power


pins can be connected to the nearest point on the chips core VDD/VSSpower mesh.

- Other Layout Issues

No signals or supplies should ideally be routed over the PLL.

Metal fill above the PLL should be left floating, and cut along the PLLboundary to minimize capacitive coupling from outside the block throughthe metal fill. Typically, the PLL hard macros are supplied with themetal fill for upper layers already in place, so this constraint shouldnot be a problem.

The PLL analog supplies should be routed at least 15um away from othersupplies or signals on all metal layers. Specifically, we stronglydiscourage routing the analog supplies under, over or adjacent to thedigital supplies. If the analog supplies must cross digital supplies,it is best to have at least one empty metal layer between them, andthey should cross orthogonally. Digital supplies are specifically NOTto be used to shield the analog supplies from signals -- physicaldistance is the only thing that works.

The PLL has an internal substrate isolation ring, which means that noadditional isolation is needed beyond the boundary of the block. Nowires of any kind should be routed over the PLL block.

No signals in the RCLK signal path, from a possible pad receiver to thePLL input, should have a slew time greater than that of a fanout of 6inverter, as measured at the input of the next gate in the chain.

TCI requires the reference clock to have less than 2% P-P long-termjitter at the RCLK pin of the PLL. Crystal oscillators are typicallyquoted to have a timing accuracies of a few parts per million. Thistiming accuracy relates to the error in the average frequency from thespecified value, and should not be confused with jitter. Short-termreference clock jitter, caused by delay modulation due to supply variationor crosstalk coupling, is less of a problem because the PLL will filterout most of the high frequency reference clock jitter components. However,the low frequency components that are below the PLL bandwidth will bepassed straight through to the output.

Ideally, the RCLK pad receiver should be located near the PLL so thatthe RCLK insertion delay (delay from the RCLK pad to the PLL pin) issmall. If the RCLK pad is more than 1 mm away from the PLL, care shouldbe taken to minimize the insertion delay and crosstalk to RCLK. Referto the "Clock Distribution" section above.

Package and Board Guidelines

The PLL supply wires inside the package should not be routed near activeI/O signal wires or I/O supply wires, but instead near static inputsignal wires or core supply wires.

The PLLs two analog supplies should be filtered with two series ferritebeads and two shunt 0.1uF and 0.01uF capacitors. The ferrite on VSS ispreferred but optional. Adding the ferrite on VSS converts supply noiseto substrate noise as seen by the PLL. The PLLs are designed to berelatively insensitive to supply and substrate noise, so the presenceof this ferrite is a second order issue.

VDD -----@@@@@-----+------+------ VDDA ferrite | | --- ---

0.1uF --- --- 0.01uF | |VSS -----@@@@@-----+------+------ VSSA ferrite


The ferrite beads should be similar one of the following from Murata:

Part number R@DC Z@10MHz Z@100MHz Z@1GHz size ----------------------------------------------------------------

BLM18EG601SN1 * 0.35 200 600 0603 BLM18PG471SN1 0.20 130 470 0603 BLM18KG601SN1 0.15 160 600 0603 BLM18AG601SN1 0.38 180 600 0603 BLM18AG102SN1 0.50 280 1000 0603 BLM18TG601TN1 0.45 190 600 0603

BLM15AG601SN1 0.60 200 600 0402 BLM15AX601SN1 * 0.34 190 600 0402 BLM15AX102SN1 0.49 250 1000 0402

BLM03AX601SN1 0.85 120 600 0201

* preferred choice

Similar ferrite beads are also available from Panasonic. The keycharacteristics to select are: - DC resistance less than 0.40 ohms - impedance at 10MHz equal to or greater 180 ohms - impedance at 100MHz equal to or greater than 600 ohms

The capacitors should be mounted as close to the package balls aspossible.

PLL Bench/Performance Testing Procedure

This section describes lab testing procedures for the PLL. Typicallythese tests would not be done in production testing.

- General testing requirements

1. The input clock RCLK should be controllable from off-chip.

2. At least one output clock should be accessible from off-chip. This output clock should be the highest frequency PLL output used on the chip. However, if there is concern about I/O bandwidth limitations, a lower frequency output or divided version can be used. Having off-chip access to RCLK driven from the chip (path is from off-chip, into chip, to PLL, then out of the chip) is also useful for jitter characterization. To conserve package pins, a multiplexer could be used to select between RCLK (at the input of the PLL) and CLKOUT for off-chip observation. The output used for this multiplexer can also be shared with other test circuits.

3. Need easy control over the pins: - RESET - PWRDN - BYPASS Ideally these inputs would directly connect to package pins. They can be shared with other PLLs or other circuits. If it is not convenient to make them directly accessible from package pins, then they can be controlled by configuration register state.

4. Other configuration inputs for the PLL can be controlled by configuration register states. These inputs include: - CLKR[0:3] - CLKF[0:5] - CLKOD[0:3] - BWADJ[0:5] - INTFB - TEST


5. IMPORTANT: Any configuration register state used must controllable without the PLL output clock functioning.

- Optional testing features

1. A multiplexer can be added at the PLL output to select between a true and inverted clock and drive an off-chip observation point for duty-cycle measurements.

2. A multiplexer can be added to before the RCLK input of the PLL to select between a true and inverted clock. This multiplexer will facilitate phase-step measurements.

- Normal closed-loop PLL tests

A number of tests can be performed on the PLL to measure their closedloop performance level. The first sets of tests focus on basic operationin a noise-free environment. The second set of tests focus on noisesensitivity.

1. Basic tests a. Make sure PLL locks correctly - for production testing, frequency only measurement - for lab testing, see if the waveform is locked

b. Measure maximum frequency range - for system lab testing, tap off of clock tree output - for production test, tap off of PLL directly - force the VCO to rail out by applying the a large input frequency - could lower supply voltage for PLL if frequency is too high - this measurement will make sure PLL has adequate frequency range

c. Over desired frequency range, measure - operate only at DESIRED frequencies for production testing 1. static phase offset - only measure if interested in it 2. power dissipation (supply current) 3. duty cycle - only measure if interested in it 4. period jitter and input-to-output jitter (no noise) a. period jitter is measured by triggering oscilloscope with PLL output and measuring jitter on next cycle edge of PLL output b. input-to-output jitter is measured by triggering oscilloscope with PLL input and measuring jitter on corresponding edge of PLL output - may not need to measure (low bandwidth) 5. lock time

2. Noise tests - not for production testing - can do minor re-work on system test board

a. Apply noise to both supply and substrate for (b) and (c) by 1. removing any bypass capacitors on PLL supplies 2. insert 5-10ohm resistors in series with PLL supplies 3. add 100ohm resistors between noise source and PLL supplies 4. for supply noise, only drive 100ohm resistor on VDDA 5. for substrate noise, drive both 100ohm resistors on VDDA and VSSA 6. provide a way of measuring VDDA/VSSA waveform to determine actual noise amplitude and edge rates

- can do a more focused testing strategy in lab after observing part - substrate noise is less precise because of unknown noise magnitude - can just use an oscilloscope

b. Pulse noise tests (square wave) 1. apply a square wave as noise source with supply peak-to-peak


amplitudes from 5% to 20% VDDA 2. sweep noise frequency from 1KHz to PLL reference frequency 3. determine worst-case peak-to-peak jitter (RMS jitter is meaningless for this test) and the frequency where it occurs 4. measure for both supply and substrate noise 5. measure both period jitter and input-to-output jitter

c. Sine wave noise tests 1. apply a sine wave as a noise source with supply peak-to-peak amplitude of 10% VDDA 2. sweep noise frequency from 1KHz to PLL reference frequency 3. plot the peak-to-peak jitter (RMS jitter is meaningless for this test) over the whole frequency range 4. measure for both supply and substrate noise 5. measure both period jitter and input-to-output jitter

Note that the worst-case jitter will be observed at noise frequencies near the PLL loop bandwidth. Also, the measured period and long-term jitter will be higher at lower VCO frequencies and will progressively get smaller as VCO frequency increases. However, TCIs jitter specifications cover the worst-case across the entire specified VCO operating frequency range.

- Special PLL tests

If problems are suspected in the PLL operation, the additional testingfeatures allow internal parameters of the PLL to be measured. Note thatgiven the adaptive nature of the circuits, the VCO and loop filterparameters are not tightly controlled and will vary with process cornerand temperature. While the characteristics of each block (VCO, chargepump, etc.) are sensitive to the process and temperature, these sensitivitiesdrop out of the combined transfer characteristics, leading to loopdynamics are independent of process, voltage, and temperature. However,the maximum operating frequency will be sensitive to process, voltage,and temperature.

1. Closed Loop Tests a. Phase step response 1. need a circuit to invert or step the phase of the input clock -- Ideally it would be controlled by a configuration signal 2. trigger the oscilloscope in one-shot mode with the same phase inversion signal 3. lock the PLL at the desired operating frequency 4. invert the phase of the input clock 5. measure the rising edge crossing locations 6. plot the rising edge crossing locations b. Synchronous phase step measurements 1. same as above, but also divide the PLL output by number on the order of 256 and use it to trigger the scope and invert the phase 2. scope can be in normal trigger mode c. Bandwidth measurements 1. loop bandwidth can be measured from the phase-step responses or from the output spectrum (spectrum analyzer measurement)

2. Testing configuration a. It may be desirable to measure the the jitter characteristics, phase-step response, or output spectrum using different settings. In general, all settings used in normal chip operation should be tested.

b. Parameters to vary 1. counter values: - CLKR[0:3] - CLKF[0:5] 2. bandwidth setting: - BWADJ[0:5]


3. operating frequency

PLL Production Testing Guidelines

1. Functional closed loop testing will be employed to test the analogcircuitry within the PLL for two extreme input frequencies via NR andNF settings. This functional test establishes both the VCO operationand the frequency/phase-lock operation at both high and low VCO frequencycorners. The configuration of the clock multiplication divider shouldbe such as to exercise the worst-case speed digital divider path duringthe high-speed VCO functional test.

2. With TEST and PWRDN asserted the PLL is also configured into "dividertest mode." The analog sections of the PLL are effectively powered-down.The PLLs digital dividers are configured as a chain. The output frequencyis (CLKOUT freq) = (REF freq) / NR / NF / OD

By connecting a clock source of known frequency to the REF input andmonitoring the frequency of the CLKOUT output, the functionality of thedigital circuitry can be determined.

The NR, NF, OD, NB divider circuits do not require any initialization.However, the initial state of the dividers is undetermined unless a resetsequence is used.

PLL production tests:

Pin access:

1. RCLK: Pin access.2. FCLK: Pin access.3. CLKOUT: Pin access. Divide appropriately to an output pin so frequency to test is below 150MHz.4. CLKR[0:3]: Register or pin access.5. CLKF[0:5]: Register or pin access.6. CLKOD[0:3]: Register or pin access.7. BWADJ[0:5]: Register or pin access.8. RESET: Pin access (or some way of guaranteeing RESET timing is met).9. PWRDN: Register or pin access.10. INTFB: Register or pin access.11. BYPASS: Register or pin access.12. TEST: Register or pin access.13. RFSLIP: Optional pin access if desired (after dividers, if required).14. FBSLIP: Optional pin access if desired (after dividers, if required).

Tests:

1. Lock PLL and perform frequency counting:

a. Maximum spec. frequency with output divider set to keep measurement frequency below 150MHz. b. Minimum spec. frequency with output divider set to keep measurement frequency below 150MHz. c. Application frequency (use additional dividers to keep measurement frequency below 150MHz, if required).

Since the user can connect a divider to FCLK, locking will depend onthis divider.

2. RESET test: Pulse reset for 5us and measure frequency within spec.

3. Divider test: When TEST=1, the 3 dividers (NR, NF, OD) areconnected in series such that RCLK is divided by NR*NF*OD and the outputis available at CLKOUT. This divider will be tested using a slow-speedfunctional test. To reset the counters:


a. Set CLKR=0001, CLKF=000001, RESET=1, wait 1 RCLK cycle. b. Set RESET=0, wait 1 RCLK cycle. c. Set RESET=1, wait 1 RCLK cycle. d. Set CLKOD=0000, RESET=0, wait 63 RCLK cycles. e. Stop clock and load desired values to test dividers. (next RCLK cycle will load all counters and force CLKOUT high)

After resetting the counters to the starting state, test the countersas follows:

a. Set NR, NF, and OD to desired test values, wait 1 RCLK cycle. b. Check that CLKOUT changed from low to high (may already be high after reset). c. Wait NR*NF RCLK cycles. d. Check that CLKOUT changed from high to low. e. Wait NR*NF*(OD-1)-1 RCLK cycles. f. Go to step "a" for next test iteration. g. Wait 1 RCLK cycle. h. Check that CLKOUT changed from low to high.

All input changes should be when RCLK goes low to avoid setup or holdtime issues.

The testing time for each set of settings is proportional to the productof the input values for all counters. The total testing time can beminimized by testing one counter at a time, where all but one counterinput value is set two. The counter under test can simply be testedwith input values to be used by applications. To obtain more completecoverage, each bit of the counter input value can be independently setin separate tests. This method will insure that logic attached to eachinput functions correctly. Because internal state of the counter isperiodic in nature and will have redundant states between tests, completecoverage is possible. The total testing time will then be proportionalto the sum of the maximum counter values (instead of the square of theproduct if all input values were independently tested).

4. Scan test of system logic with BYPASS=1.

5. Iddq test of system logic with BYPASS=1 and PWRDN=1.

Additional Notes

1. No external loop filter components are required for this PLL.

2. Although an on-chip voltage regulator is not explicitly specified anda good PSRR should be inherent in the design of the delay stage, aregulator option is left open to the designer to facilitate meetingjitter requirements if needed.

3. The MUXes that select clocks external to the PLL for testing andfeedback modes should be NAND based and not Transmission Gate MUXes(library MUXes should not be used). The MUX function should be distributedand the control signal run along with the internal "distributed" MUXnode to minimize the high frequency cross talk associated with co-locatedmacro inputs and shared VDD/VSS connections. An example of thisconfiguration is presented earlier in the "Distributed MUXes" subsection.

4. Since there will be large numbers of SSO producing output buffers,there will be two types of SSO noise that are addressed with this design.The first is the normal core VDD / VSS bounce that can be stabilizedwith core capacitance and the second is the reflected negative voltagepulse pumping current into the substrate. The latter SSO term modulatesthe Vt of the Nch transistors thereby creating a change in delay (jitter).

Addendum to Line Item Definitions of Specifications


- Divided reference frequency range: The divided reference frequency (Fint) is defined as: Fint = Fref/NR where Fref is the input reference clock frequency, and NR is the reference divider value. Fint is the rate at which the PFD updates.

- /1 output frequency range: This frequency range can also be interpreted as the allowed VCO frequency range when PLL is locked.

- Output divider values: The output divider is outside the PLL feed-back loop.

- Bandwidth adjustment div. range: These affect both 3-dB band-width (Fbw_3dB) as well as damping factor (D) of the PLL. Fbw_3dB should be set to less than Fint/10. D should be set to between 0.7 and 1.4.

- Feedback signal delay (max): Exceeding this maximum feedback delay can result in poor dynamic performance of the PLL, which can manifest itself as large jitter or inability to lock.

- Period jitter (P-P) (max): Typically, period jitter measurements should be performed over at least 100,000 consecutive output clock periods. Ideally, at least 10*Fout/Fbw_3db consecutive periods should be measured. The specification assumes worst case on-chip operating condition. Actual measured data is expected to result in much smaller value. For formal definition of period jitter refer in the "Definitions" section.

- Input-to-output jitter (P-P) (max): Typically, input-to-output jitter measurements should be performed over at least 100,000 consecutive output clock edges. Ideally, at least 10*Fout/Fbw_3db consecutive edges should be measured. The specification assumes worst case on-chip operating condition. Actual measured data is expected to result in much smaller value. If the reference clock is noise free, input-to-output jitter and long-term/accumulated jitter measurements are identical. For formal definition of input-to-output jitter refer in the "Definitions" section.

- Power dissipation (nom): The total power dissipation scales approximately linearly with VCO frequency and will show approximately 20% P-P variation across PVT.

Definitions

Output Jitter Definitions

Output clock jitter can be measured in a number of ways. It can bemeasured relative to absolute time, to another signal, or to the outputclock itself. The first measurement of jitter is commonly referred toas absolute jitter or long-term jitter. The second is commonly referredto as tracking jitter or input-to-output jitter when the other signalis the reference signal. If the reference signal is perfectly periodicsuch that it has no jitter, absolute jitter and tracking jitter for theoutput clock are equivalent. The third is commonly referred to as periodjitter and/or cycle-to-cycle jitter.

Output jitter is typically reported as RMS or peak-to-peak jitter. RMSjitter is interesting only to applications that can tolerate a smallnumber of edges with large time displacements that are well beyond theRMS specification with gracefully degrading results. Such applications


can include video and audio signal generation. Peak-to-peak jitter isinteresting to applications that cannot tolerate any edges with timedisplacements beyond some absolute level. The peak-to-peak jitterspecification is typically the only useful specification for jitterrelated to clock generation since most setup or hold time failures arecatastrophic to the operation of a chip. Mathematical definitions ofthe various jitter terms are described in the sections below.

- Jitter types: Tjit_per_pp = peak-to-peak period jitter measured over N consecutive edges of output clock.

Tjit_per_rms = RMS period jitter measured over N consecutive edges of output clock.

Tjit_cyc_pp = peak-to-peak cycle-to-cycle jitter measured over N consecutive edges of output clock.

Tjit_cyc_rms = RMS cycle-to-cycle jitter measured over N consecutive edges of output clock.

Tjit_lt_pp = peak-to-peak long-term/absolute jitter from N consecutive measurements carried out at i-th edge of output clock.

Tjit_lt_rms = RMS long-term/absolute jitter from N consecutive measurements carried out at i-th edge of output clock.

Tjit_trk_pp = peak-to-peak tracking/input-to-output jitter from N consecutive measurements carried out at i-th edge of output clock.

Tjit_trk_rms = RMS tracking/input-to-output jitter from N consecutive measurements carried out at i-th edge of output clock.

- Intermediate quantities: Eout(i) = edge time of i-th edge of output clock.

Eref(i) = edge time of reference clock that corresponds to i-th edge of output clock.

Tout(i) = period at i-th edge of output clock.

Tjit_per(i) = period jitter measured at i-th edge of output clock.

Tjit_cyc(i) = cycle-to-cycle jitter measured at i-th edge of output clock.

Tjit_lt(i) = long-term or absolute jitter measurement at i-th edge of output clock.

Tjit_trk(i) = tracking or input-to-output jitter measurement at i-th edge of output clock.

- Notation used: Sum[X(N)] = X[1] + X[2] + ... + X[N] Sum[X(N)^2] = X[1]^2 + X[2]^2 + ... + X[N]^2 Avg[X(N)] = Sum[X(N)]/N Avg[X(N)^2] = Sum[X(N)^2]/N Std[X(N)] = sqrt(Avg[X(N)^2] - Avg[X(N)]^2) Max[X(N)] = max(X[1], X[2], ... X[N]) Min[X(N)] = min(X[1], X[2], ... X[N])

- Jitter definitions: Tout(i) = Eout(i) - Eout(i-1)

Tjit_per(i) = Tout(i) - Avg[Tout(N)] Tjit_per_pp = Max[Tout(N)] - Min[Tout(N)] Tjit_per_rms = Std[Tout(N)]


Tjit_cyc(i) = Tout(i) - Tout(i-1) Tjit_cyc_pp = Max[Tjit_cyc(N)] - Min[Tjit_cyc(N)] Tjit_cyc_rms = Std[Tjit_cyc(N)]

Tjit_lt(i) = Eout(i) - i*Avg[Tout(N)] Tjit_lt_pp = Max[Tjit_lt(N)] - Min[Tjit_lt(N)] Tjit_lt_rms = Std[Tjit_lt(N)]

Tjit_trk(i) = Eout(i) - Eref[i] Tjit_trk_pp = Max[Tjit_trk(N)] - Min[Tjit_trk(N)] Tjit_trk_rms = Std[Tjit_trk(N)]

-------------------------------------------------------------------------------


Deskew PLL Application Notes=============================

1. Introduction

For interfacing signals in and out of the chip, it is often requiredthat these signals be synchronized to a common clock source that residesoutside the chip. To comply with these interface standards, each chipneeds an internal clock that is phase-aligned with the external clockand sequences the on-chip I/O circuitry.

In many cases, the off-chip clock driver cannot drive the large on-chipclock loads directly and the external clock must be buffered first beforeuse. These on-chip clock buffers have finite delays, which introduce aphase offset between the external and internal clocks. Unfortunately,it is very difficult to predict this delay prior to the chip fabricationdue to process variability and the resulted phase difference between theexternal and internal clocks is almost arbitrary (Figure 1a).

Phase-locked loops can synchronize these clocks by effectively hidingthe delay of the clock buffers. A phase-locked loop (PLL) is a feedbacksystem that aligns the phases of the two input clocks, FCLK and RCLK asdenoted in Figure 1b. A PLL achieves this alignment by adjusting thephase of its output clock, which feeds to the clock tree input in thiscase. Thanks to this feedback operation, the clock at the end of theclock tree (FCLK) is phase-aligned with the external clock (FCLK) andthe synchrony is maintained. The deskew PLL specified in this documentcan keep the timing skew between the RCLK and the FCLK clocks within+/-2% of the /1 output period.

Figure 1. Deskew PLL Overview ___

| | | | ... |_^_| | +---> FCLK ____________ | | | | RCLK >---->--------------------------| clock tree |- - - -+-- .... |____________| (a) Simple clock buffering: phase relationship between RCLK and FCLK is unknown and can be arbitrary as the clock tree delay can largely vary due to process variation. ___

| | | | ... |_^_| | | +--------------------------------------------- - - --+

| ____________ | | +---------------+ | | | FCLK +---->| CLKOUT |->-------| clock tree |- - - -+-- .... | PLL | |____________| RCLK >---->| | +---------------+

(b) Deskewing using a phase-locked loop: FCLK is phase-aligned with RCLK and the delay of the clock tree is effectively nulled out.

2. Features of the Deskew PLL

In addition to deskewing the phase difference between the external and


internal clocks, the deskew PLL have some others features forthe users convenience: the built-in feedback, reference, and outputclock dividers.

Sometimes, the internal clock frequency has to be a multiple of theexternal clock frequency. Phase-locked loops can perform frequencymultiplication by inserting a clock divider (denoted as /NF) in thefeedback path (FCLK). The clock divider divides the clock frequencydown by an integer number and now the PLL tries to phase-align thisdivided clock (DCLK) with the divided external clock (RCLK) (since theexternal reference clock is divided by the NR divider). As a result, thefrequency of the PLL output clock will be the same integer-multiple ofthe divided external frequency. In deskew PLL, the divide-ratio canbe 1 to 64 configurable by the 6-bit CLKF input (Figure 2).

The users can choose to use external clock dividers if differentdivide-ratios are desired. However, the best performance of this PLLis achieved via the use of the internal clock divider (/NF) because itis specially-designed to hide its inherent delay. In Figure 2, the delaythrough the internal clock divider (/NF) is effectively zero so thedelays from the FCLK and RCLK inputs to the phase-frequency detector(PFD) are identical. For stable operation of the PLL, it is requiredto keep the feedback path delay shorter than the specified amount.Incautious use of external clock dividers may make the PLL fall in theunstable state where the timings of the output clocks become extremelysensitive to noise. External clock dividers also require carefuldelay-matching.

Figure 2. Additional features of the deskew PLL: built-in reference, feedback, and output divider.

+-----------------------------------------------------------+

| | | +-----+ DCLK +-----+ +-----+ | FCLK --|---->| |----->| | | | +-----+ 0|\ | | | /NF | | PFD | ... | VCO |----->| |-->| |---|-CLKOUT CLKF --|-/-->| | /-->| | | | | /OD | | | | | 6 +-----+ | +-----+ +-----+ /-->| | | | | | | | +-----+ | | | | | | 1| | | | /------------C------------------------C------------>| | | | | | | |/ | | | +-----+ | | ^ | RCLK --|-+-->| |--/ | | | | | /NR | | | | CLKR --|-/-->| | | | | | 4 +-----+ | | | | | | | CLKOD--|-/-------------------------------------/ | | | 4 | | | | | BYPASS-|------------------------------------------------------/ | | | +-----------------------------------------------------------+

3. Dynamic Behavior of the PLL

Clock jitter means the dynamic variation of the clock timing and it isof primary concern since the uncertainty in timing can limit the maximumfrequency of systems operation. The jitter is contributed both by theVCO itself and by the application-dependent circuits on the output/feedbackpath (e.g. clock distribution trees) and thus it is important fordesigners to understand the PLL dynamic behavior to minimize the overallclock jitter and estimate reasonable amount for their timing budgets.For low jitter possible, the feedback path must be free from noise andits delay should be kept short.


A phase-locked loop (PLL) constantly examines the phase difference betweenthe reference clock and the feedback clock and adjusts the frequency ofthe voltage-controlled oscillator (VCO) accordingly. For example, whenthe reference phase drifts down, the PLL will move the output phase totrack the change of the reference phase. Similarly, when some noisecauses the output phase to move away from the reference phase, the PLLwill try to recover the lock state as quickly as possible.

However, there is a limit on how quickly the PLL can adjust its outputphase. This limit is called "bandwidth" and determines how quickly thePLL can track the change in the reference phase, or equivalently, howwell the PLL can reject the undesired disturbance of the output phase.High-bandwidth PLLs are good at reducing jitter on the output clock pathby tracking the reference clock and low-bandwidth PLLs are good atfiltering jitter on the reference clock.

Deskew PLLs have high bandwidths and therefore can suppress the disturbanceon the output clock path if that disturbance happens slower than thebandwidth. In the applications of deskew PLLs, the most dominantdisturbances are likely to occur from the clock distribution trees, wherethe clock signal travels a long distance under the influence of manyhostile noise sources. As a result, the clock at the end of thedistribution tree will have worse jitter than the direct output clockof the PLL. If the phase drift caused by this added jitter is slowenough, then the error can be effectively canceled by the PLL. If thedrift is faster than the bandwidth, however, the PLL will not be ableto respond quickly enough to correct the error. Unfortunately, thejitter added by the clock tree typically has a drift rate that is muchhigher than the bandwidth which prevents the PLL from correcting it.

Therefore, when designers budget the timing uncertainties on their clocksafter the distribution chains, they must add the expected jitter fromthe clock distribution paths to the specified PLL jitter. This addedjitter is likely to increase with the delay of the clock distributionpath.

4. Application Examples

4.1 Example 1: Basic Configuration

Figure 3 shows the basic application of this deskew PLL. Lets say theexternal clock (RCLK) frequency is 200MHz and the on-chip circuits need400MHz clock synchronized to RCLK. To accomplish this, the bufferedCLKOUT (denoted as CLKA) is fed back as FCLK and the internal clockdivider of the PLL (/NF) is configured to divide by 2.

Figure 3. Basic configuration of the deskew PLL. ___

| | | | ... |_^_| | | +----------------------------------------------------+

| ______________ | | +---------------+ /-->| clock tree A |-----+ ... CLKA FCLK +---->| CLKOUT |->--/ -------------- (400MHz) | PLL | RCLK >---->| (NF=2,NR=OD=1)| (200MHz) +---------------+

Static timing offset between the rising edges of FCLK and RCLK seen atthe PLL input is kept less than 2% of the reference clock period. However,if there is some delay on the feedback path between CLKA and FCLK, thephase difference between CLKA and RCLK will be undesirably offsetted bythis amount. Likewise, if the RCLK route path on the chip is long and


has noticeable delay, this will introduce an undesirable offset betweenthe internal clocks and the external clock. Therefore, it is best tominimize, or at least equalize the propagation delays on RCLK and FCLKpaths.

The net polarity of the clock buffer tree does not affect the outputphase, as long as the buffer tree is within the PLL feedback loop. The180-degree phase shift caused by the net inversion will be compensatedby the PLL adjusting its output phase. In this example, CLKA will bealways rising-edge aligned with RCLK, regardless of the net polarity ofthe clock tree.

4.2 Example 2: The External Clock Divider in the Feedback Path

For cases where an external clock divider is necessary, the PLL can beconfigured as in Figure 4. Since most clock dividers have delays andintroduce phase offsets between their input and output clocks, this delaymust be effectively canceled by inserting a delay-matched dummy dividerin the RCLK path. Otherwise, the delay will cause a static phase offsetbetween FCLK and RCLK, since the PLL aligns the clock phases seen at itsinputs, A and B as denoted in Figure 4. The reasons are similar to thecase of having delay on the feedback path, discussed in Section 4.1.

Figure 4. The use of external clock dividers in the feedback path. ___

| | | | ... |_^_| | | +--------------------------------------------- - - --+

| | | +----+ A +---------------+ ____________ | FCLK +--| /N |-->| CLKOUT |->---| clock tree |- - -+-- .... +----+ | | ------------ | PLL | +----+ B |

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