Tasks and Functions.ppt

8/12/2019 Tasks and Functions.ppt

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Tasks and Functions


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2014 Tasks and Functions 2

A designer is frequently required to implementthe same functionality at many places in abehavioral design.

This means that the commonly used partsshould be abstracted into routines and theroutines must be invoked instead of repeatingthe code.

Verilog provides tasks and functions to break uplarge behavioral designs into smaller pieces.


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Differences between...

FunctionsCan enable (call) just

another function (not task)

Execute in 0 simulation

time

No timing controlstatements allowed

At least one input

Return only a single value

TasksCan enable other tasks and

functions

May execute in non-zerosimulation time

May contain any timingcontrol statements

May have arbitrary input,output, or inout

Do not return any value


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Bothare defined in a module

are local to the module

can have local variables (registers, but not nets) andevents

contain only behavioral statements

do not contain initialor alwaysstatements

are called from initialor alwaysstatements or othertasks or functions


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Tasks can be used for common Verilog code

Tasks are capable of enabling a function as wellas enabling other versions of a Task

Function are used when the common code is purely combinational

executes in 0 simulation time

provides exactly one output

Functions are typically used for conversions andcommonly used calculations


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Tasks

Keywords: task, endtask

Must be used if the procedure has

any timing control constructs

zero or more than one output arguments

no input arguments


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Task declaration and invocation

Declaration syntax

task ;

begin // if more than one statement needed

end // if beginused!

endtask


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Task declaration and invocationTask invocation syntax;

();

inputand inoutarguments are passed intothe task

outputand inoutarguments are passedback to the invoking statement when task iscompleted


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I/O declaration in modules vs. tasksBoth used keywords: input, output,inout

In modules, represent portsconnect to external signals

In tasks, represent arguments

pass values to and from the task


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module operation;parameter delay= 10;reg [15:0] A, B;reg [15:0] AB_AND, AB_OR, AB_XOR;

initial$monitor( );

initialbegin

end

always @(A or B)begin

bitwise_oper(AB_AND, AB_OR,AB_XOR, A, B);

end

task bitwise_oper;output [15:0] ab_and, ab_or,

ab_xor;input [15:0] a, b;begin

#delayab_and = a & b;ab_or = a | b;ab_xor = a ^ b;

endendtask

endmodule

Task ExampleUse of input and output arguments


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module sequence;

reg clock;

initial

begin

end

initial

init_sequence;

always

asymmetric_sequence;

task init_sequence;

clock= 1'b0;

endtask

task asymmetric_sequence;begin

#12 clock= 1'b0;

#5 clock= 1'b1;

#3 clock= 1'b0;

#10 clock= 1'b1;

end

endtask

endmodule

Task ExampleUse of module local variables


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moduletraffic_lights;regclock, red, amber, green;parameteron = 1, off = 0, red_tics = 350,

amber_tics = 30, green_tics = 200;

initialred = off;initialamber = off;initialgreen = off;

alwaysbegin// sequence to control the lights.

red = on; // turn red light onlight(red, red_tics); // and wait.green = on; // turn green light onlight(green, green_tics); // and wait.amber = on; // turn amber light onlight(amber, amber_tics); // and wait.end// task to wait for tics positive edge clocks// before turning color light off.

tasklight;outputcolor;input[31:0] tics;begin

repeat(tics) @ (posedgeclock);color = off; // turn light off.endendtask

alwaysbegin// waveform for the clock.#100 clock = 0;#100 clock = 1;endendmodule// traffic_lights.


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module top;reg [15:0] cd_xor, ef_xor;reg [15:0] c, d, e, f;

task automatic bitwise_xor;output [15:0] ab_xor;input [15:0] a, b;begin#delay ab_and = a & b;

ab_or = a | b;ab_xor = a ^ b;endendtask/*These two always blocks will call the bitwise_xor task concurrently at eachpositive edge of clk. However, since the task is re-entrant, these concurrent calls

will work correctly. */always @(posedge clk)bitwise_xor(ef_xor, e, f);always @(posedge clk2) // twice the frequency as the previous blockbitwise_xor(cd_xor, c, d);endmodule


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Function Declaration and Invocation

Declaration syntax:

function ;

begin // if more than one statement needed

end // if begin used

endfunction


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Function Declaration and Invocation

Invocation syntax: ();


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Semanticsmuch like functionin Pascal

An internal implicit regis declared inside

the function with the same name

The return value is specified by setting thatimplicit reg

defines width and type ofthe implicit reg

can be integeror real

default bit width is 1


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modulefunction_calling(a, b,c);

inputa, b ;outputc;wirec;

functionmyfunction;inputa, b;beginmyfunction = (a+b);endendfunction

assignc = myfunction (a,b);

endmodule


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Function ExamplesParity Generator

module parity;

reg [31:0] addr;

reg parity;

initial begin

end

always @(addr)

begin

parity = calc_parity(addr);

$display("Parity calculated = %b",calc_parity(addr));

end

function calc_parity;

input [31:0] address;

begin

calc_parity= ^address;

end

endfunction

endmodule


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Function ExamplesControllable Shifter

module shifter;

`define LEFT_SHIFT 1'b0

`define RIGHT_SHIFT 1'b1

reg [31:0] addr, left_addr,right_addr;

reg control;

initial

begin

end

always @(addr)

begin

left_addr =shift(addr, `LEFT_SHIFT);

right_addr =shift(addr,`RIGHT_SHIFT);

end

function [31:0]shift;

input [31:0] address;

input control;

begin

shift = (control==`LEFT_SHIFT)

?(address1);end

endfunction

endmodule


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Automatic (Recursive) Functions:

Functions are normally used non-recursively. If a function is called concurrentlyfrom two locations, the results are non-deterministic because both calls operate onthe same variable space. However, the keyword automatic can be used to declare a recursive (automatic)function where all function declarations are allocated dynamically for each recursivecalls.

Each call to an automatic function operates in an independent variable space. Automatic function items cannot be accessed by hierarchical references. Automatic functions can be invoked through the use of their hierarchical name.


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// Define the functionfunction automatic integer factorial;

input [31:0] oper;beginif (oper >= 2)factorial = factorial (oper -1) * oper; //recursive callelsefactorial = 1 ;

endendfunction// Call the functioninteger result;initial beginresult = factorial(4);// Call the factorial of 4$display("Factorial of 4 is %d", result); //Displays 24endendmodule


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Signed Functions:

Signed functions allow signed operations to be performed on the function returnvalues.

module top;--

//Signed function declaration//Returns a 64 bit signed valuefunction signed [63:0] compute_signed(input [63:0] vector);-- --endfunction--

//Call to the signed function from the higher moduleif(compute_signed(vector) < -3)begin--end--

endmodule

Tasks and Functions.ppt

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