Talk Gatech Ps2 2003

8/6/2019 Talk Gatech Ps2 2003

http://slidepdf.com/reader/full/talk-gatech-ps2-2003 1/17

PS2 ArchitectureToshiba Corporation

Sony Computer Entertainment

Prepared by: Weidong Shi



PS2 Design Policy

Cutting-edge application specific processorsHigh speed renderingHigh performance geometry processingHigh speed simulationHigh performance data path



Graphics Pipeline

Application (AI, collision detection,

physical simulation,3D scene )

Geometry Processing(transformation,

perspective division,lighting, clipping )

Rasterization

(scan conversion,texturing, z-buffering)

Frame Buffer

CS

EE



The Emotion Engine

CPU+FPU : programcontrol, housekeeping

CPU+FPU+VU0 : AI,Physics, simulation

VU1: geometryprocessing



.25-micro CMOS processwith .18-micro gate length

13.5 million transistors

300MHz, 18 watts of power

15.02-mm X 15.04-mm die

size

The Emotion Engine



High Performance Data Path

2 128Mbits RDRAM,3.2GB/sec Main Memory:32MB (Direct RDRAM

2ch@800MHz)High performance DMAengine (list of DMAdescriptors).DMA from memory to CPU

scratch ram, VPU ram andGS.shared memory architecture

GS

GIF (FIFO)

VU1VU0CPU

Memory

EE



The MIPS III Core

two issue superscalarMIPS III 64-bit instruction set (MIPS IV pre-fetchinstruction)

instruction cache: 16kbytes, two-way, 4qword cachelinedata cache: 8k bytes, two-way, hit-under-miss,4qword cache linescratchpad RAM (SPR) 16kbytes, data bus 128bitsFPU 32bit 1FMAC + 1DIVTLB: 48 double entries



The Vector Units

Functionality

VU1: perspective transformation, lighting calculation,

volumetric fog, connects to GS via GIFVU0: animation, physics, simulation, collision detectioncoupled with MIPS core, 128bit coprocessor bus

Two modesVLI: stand-alone processorMIPS coprocessor mode (for VU0 only)



Examples - what VUs can dofor games

Dynamic lightingShadow

AnimationCollision DetectionWave SimulationVehicle Dynamic



VU architecture



VLIW instruction

an upper execution unit with four parallel fMACs(SIMD)a lower execution unit with fDIV, load/store, iALU, andbranch128-bit X 32 floating registers16-bit X 16 integer registers



Switch from COP mode to VLIW mode

Switch from co-processor mode to VLIW mode bythe MIPS core

Step 1: store VLIW codes in VU0 code RAM using DMAStep 2: load data to VU0 data RAM using DMAStep 3: run COP2 to execute the loaded code



Performance

Perspective Transformation: 66 million polygons/sec.Lighting: 38 million polygons/sec.



Graphics Synthesizer

CS core: Rasterization + On chip Frame bufferClock Frequency: 147.456MHzSilicon Process Technology: 0.25 4-level metalTotal Number of Transistors: 43 millionNo. of Pixel Engines: 16 (in parallel)Embedded DRAM: 4MB of multi-port DRAM (Synced at150MHz)Combined Internal Data Bus Bandwidth: 2,560 bit (Read: 1,024bit,Write: 1,024 bit, Texture: 512 bit)Display Color Depth: 32 bit (RGBA: 8 bits each)Z Buffering: 32 bit



Performance

Pixel Fill Rate: 2.4 giga pixel/secParticle Drawing Rate: 150 million/sec.Polygon Drawing Rate:

75 million/sec. (small polygon)50 million/sec. (48 pixel quad with Z and A)30 million/sec. (50 pixel triangle with Z and A)25 million/sec. (48 pixel quad with Z, A, and T)Sprite Drawing Rate: 18.75 million (8 x 8 pixels)

Talk Gatech Ps2 2003

Documents

Transcript of Talk Gatech Ps2 2003