TALENT Summer School, June 2013 1 Monolithic pixel sensors Ivan Perić.
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Transcript of TALENT Summer School, June 2013 1 Monolithic pixel sensors Ivan Perić.
![Page 1: TALENT Summer School, June 2013 1 Monolithic pixel sensors Ivan Perić.](https://reader030.fdocuments.net/reader030/viewer/2022032802/56649e195503460f94b05eec/html5/thumbnails/1.jpg)
TALENT Summer School, June 2013 1
Monolithic pixel sensors
Ivan Perić
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TALENT Summer School, June 2013
Monolithic vs. hybrid detectors
• Monolithic pixel sensor• Monolithic - formed from a single crystal• Pixel sensor - segmented detector of visible light or radiation
Sensor pixel chip
Readout pixel chip
Sensor chip
Hybrid detector
n2 chip to chip connections
Monolithic detector
Output signal
Output signal
Readout block
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TALENT Summer School, June 2013
Overview of monolithic sensors
• Monolithic pixel sensors – three classes• 1) Pixel sensors implemented in commercial CMOS technologies• 2) Special monolithic technologies (DEPFETs, SOI-detectors)• 3) Monolithic sensors obtained by 3D integration
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TALENT Summer School, June 2013 4
Commercial (C)MOS monolithic pixel sensors
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TALENT Summer School, June 2013
(C)MOS monolithic sensors
• The original application of CMOS sensors – consumer electronics• Imaging sensors for digital cameras and mobile phones• Such sensors be used for particle tracking, however…• certain improvements are necessary• Epi layer, hi-resistivity substrate, deep-n-well, use of true CMOS pixels• Although implemented in CMOS technologies commercial imagers use only one type of transistor
in pixels – (C)MOS
Phone with 41 M pixel sensor, 1.4um pixel size
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TALENT Summer School, June 2013
Commercial imaging sensors
• Imaging sensors for digital cameras and mobile phones• Two basic types CMOS sensor and CCD
Canon 120 M pixels, 2um pixel size Teledyne DALSA 60 M pixels CCD, 6um pixel size
29 mm
54 mm
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TALENT Summer School, June 2013
MOS technology
• MOS Technology – Integrated circuit technology based on Metal Oxide Semiconductor field effect transistors
• Field effect transistor invented in 1925 by Julius Lilienfeld• Finally realized in 1960s
Silicon p type
n type region “diffusion”
„Metal“ Electrode Insulator
Samsung 32nm process
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TALENT Summer School, June 2013
PN junction
• The simplest building element – PN junction• N-diffusion – potential valley for electrons• P-substrate –potential barrier for electrons
Silicon n type Silicon p type
Free electrons
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TALENT Summer School, June 2013
PN junction
• Reversely biased – large depleted layer• Detector mode
Silicon n type Silicon p type
+
Depleted
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TALENT Summer School, June 2013
PN junction
• Directly biased – current flow• Not used in MOS circuits
Silicon n type Silicon p type
+
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TALENT Summer School, June 2013
PN junction as sensor of radiation
• PN junction as sensor• 1. step - ionization
Atoms
Photons or particles
IonisationFree e-
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TALENT Summer School, June 2013
PN junction as sensor of radiation
• PN junction as sensor• 2. step – charge collection• Two possibilities for charge collection – drift (through E-force) and by diffusion (density gradient)
Atoms
Collection of electrons
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TALENT Summer School, June 2013
PN junction as sensor of radiation
• PN junction as sensor• 3. step – charge to voltage conversion• Collection of the charge signal leads to the potential change
AtomsPotential change
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TALENT Summer School, June 2013
MOS transistor
• The basic element – MOS field effect transistor• Potential barrier between the transistor contacts can be controlled by the voltage applied at gate
electrode• N-channel MOS - NMOS
Silicon p type
N-type diffusion-regions (drain and source)
„Metal“ Electrode(Gate)
Insulator
Gate
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TALENT Summer School, June 2013
MOS transistor
• Current flow controlled by gate-bulk voltage
Silicon p type
Insulator
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TALENT Summer School, June 2013
MOS transistor
• Interesting: Current flow does not depend on drain voltage
Silicon p type
Insulator
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TALENT Summer School, June 2013
MOS transistor
• Current flow controlled only by gate-bulk voltage
Silicon p type
Insulator
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TALENT Summer School, June 2013
CMOS pixel
• Pixel sensor in MOS technology
N-type regionDiffusion (shallow)
Or well (deep)
Sensor-junction
MOS FET
Sensor-junction
MOS FET
Gate
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TALENT Summer School, June 2013
CMOS pixel
• N in P diode acts as sensor element – signal collection electrode
N-type regionDiffusion (shallow)
Or well (deep)
Sensor-junction
MOS FET
Sensor-junction
MOS FET
Gate
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TALENT Summer School, June 2013
CMOS pixel
• Charge generated by ionization is collected by the N-diffusion• This leads to the potential change of the N-diffusion• The potential change is transferred to transistor gate – it modulates the transistor current
N-type regionDiffusion (shallow)
Or well (deep)
Sensor-junction
MOS FET
Sensor-junction
MOS FET
Gate
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TALENT Summer School, June 2013
Rolling shutter readout
• Readout principle: Many pixels (usually one row) share one readout line• Additional MOSFET used as switch• The readout lines lead to the electronics at the chip periphery that does signal processing• Monolithic detector – signal processing on the chip - fast
A
AAAAA
SwitchSwitch
Pixel i+1Pixel i
Periphery of the chip
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TALENT Summer School, June 2013
CCD principle
• CCD principle as comparison• Potential valleys and barriers in silicon formed by proper doping. • They are controlled applying voltages on metal electrodes
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TALENT Summer School, June 2013
CCD principle
• Illumination, ionization and charge collection
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TALENT Summer School, June 2013
CCD principle
• Shifting of the charge• Two voltage pulses are used to raise and lower the barriers
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TALENT Summer School, June 2013
CCD principle
• Shifting of the charge
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TALENT Summer School, June 2013
CCD principle
• Shifting of the charge
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TALENT Summer School, June 2013
CCD principle
• Charge signals are shifted to the external amplifier• No conversion to voltage occurs• Amplification and signal processing on separated chip• Slow readout
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TALENT Summer School, June 2013 28
(C)MOS monolithic pixel sensors for particle tracking
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TALENT Summer School, June 2013
CMOS sensors for particle tracking
• Can CMOS structure be used for detection of high energy particles in particle tracking?• Yes, but fill factor is an issue – ratio of the sensitive versus insensitive area
Detected Not detected
Charge collection by drift
Absorbed by electronics
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TALENT Summer School, June 2013
Fill-factor
• Partial signal collection in the regions without E-field
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TALENT Summer School, June 2013
Fill-factor
• Partial signal collection in the regions without E-field
Recombination
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TALENT Summer School, June 2013
Overview
• Partial signal collection in the regions without E-field
Recombination
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TALENT Summer School, June 2013
Overview
• Partial signal collection in the regions without E-field
Charge collection by diffusion
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TALENT Summer School, June 2013
Fill-factor
• Partial signal collection in the regions without E-field
Charge collection by diffusion
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TALENT Summer School, June 2013
Fill-factor
• In the case visible light imaging, the insensitive regions do not impose a serious problem• Light can be focused by lenses• Exposure time can be increased• In the case of particle tracking, any insensitive region should be avoided
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TALENT Summer School, June 2013
MOS pixel sensor with 100% fill factor
• MOS sensor with 100% fill-factor• Based on epi-layer• Monolithic active pixel sensor - “MAPS”
Lightly p-doped epi-layer
Heavily p-doped P-well
N-diffusion or N-well
MOS FETNMOS
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TALENT Summer School, June 2013
MOS pixel sensor with 100% fill factor
• Ionization in the epi-layer• Charge collection by diffusion
N-diffusion or N-well
Particle
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TALENT Summer School, June 2013 38
MAPS
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TALENT Summer School, June 2013 39
MOS pixel sensor with 100% fill factor - MAPS
MAPS
NMOS transistor in p-well N-well (collecting region)Pixel i
Charge collection (diffusion)
P-type epi-layer
P-type substrate Energy (e-)
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TALENT Summer School, June 2013
MAPS
• Many institutes are developing MAPS, for instance: IPHC Strasbourg (PICSEL group)• Family of MIMOSA chips• Applications:, STAR-detector (RHIC Brookhaven), Eudet beam-telescope and ALICE inner
tracker upgrade
http://www.iphc.cnrs.fr/Monolithic-Active-Pixel-Sensors.html
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TALENT Summer School, June 2013
MAPS
http://www.iphc.cnrs.fr/Monolithic-Active-Pixel-Sensors.html
Ultimate chip for STARMIMOSA 26 for Eudet telescope
• Although based on simple MAPS principle – epi layer and NMOS electronics – MIMOSA chips use more complex pixel electronics
• Continuous reset and double correlated sampling
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TALENT Summer School, June 2013
Charge collection & technology studies – simple demonstrators
Production
MimoStar3
MimoTEL Imager10µ Imager12µ
Mimosa16 Mimosa16
Latchup ADC ADC MyMap
TestStruct
Real size prototype - yield studiesReticule 2x 2 cm 2006
Data compression - digitization
Sara 2006Suze 2007
Final circuits – sub-blocs integration
Mimosa22
2008
Pixel Array
DiscriminatorsZero Suppression
Bias Readout
2007
1999
MAPS
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TALENT Summer School, June 2013 43
Advanced CMOS pixel sensors with intelligent pixels
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TALENT Summer School, June 2013 44
Frame readout
- Simple pixels- Signal and leakage current is
collected- No time information is attached to
hits- The whole frames are readout Small pixels Low power consumption Slow readout
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TALENT Summer School, June 2013 45
Sparse readout
6
9
9
3
6
9
9
3
- Intelligent pixels- FPN is tuned inside pixels- Leakage current is compensated- Hit detection on pixel level- Time information is attached to hits Larger pixels Larger power consumption Fast (trigger based) readout
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TALENT Summer School, June 2013 46
Intelligent pixel
LatchComparatorCR-RC
4-bit tune DACReadout bus
CSA
Bus driver
RAM
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TALENT Summer School, June 2013
CMOS electronics
• Two transistor types n-channel NMOS and p-channel PMOS are needed for the realization of complex circuits
Silicon p type
Silicon n type
„Metal“ Electrode
Insulator
Silicon n type
Silicon p type
„Metal“ Electrode
Insulator
NMOS PMOS
NMOS
PMOS
Free e-
Holes
Holes
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TALENT Summer School, June 2013
CMOS electronics
• Example: A good voltage amplifier can only be realized with CMOS
Silicon p type
Silicon n type
„Metal“ Electrode
Insulator
Silicon n type
Silicon p type
„Metal“ Electrode
Insulator
NMOS PMOS
NMOS
PMOS
Free e-
Holes
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TALENT Summer School, June 2013
MAPS structure with CMOS pixel electronics
• If PMOS transistors are introduced, signal loss can happen
NMOS transistor in p-well
N-well (collecting region)
Pixel i
P-type epi-layer
P-type substrate Energy (e-)
MAPS with a PMOS transistor in pixel
PMOS transistor in n-well
Signal collectionSignal loss
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TALENT Summer School, June 2013 50
Advanced structures: INMAPS
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TALENT Summer School, June 2013 51
INMAPS
NMOS shielded by a deep p-well
PMOS in a shallow p-well
N-well (collecting region)
Pixel
P-doped epi layer
INMPAS
• Deep P-layer is introduced to shield the PMOS transistors from epi layer• No charge loss occurs• This is not a CMOS standard process• Only one producer so far: Tower Jazz
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TALENT Summer School, June 2013
Overview
• INMAPS Tower Jazz process is gaining popularity in particle physics community• It was originally developed by the foundry and the Detector Systems Centre, Rutherford Appleton
Laboratory
2 Megapixels, large area sensorDesigned for high-dynamic range X-ray imaging40 µm pixel pitch1350 x 1350 active pixels in focal planeAnalogue readoutRegion-of-Reset setting140 dB dynamic range20 frames per second
FORTIS chip
http://dsc.stfc.ac.uk/Capabilities/CMOS+Sensors+Design/Follow+us/19816.aspx
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TALENT Summer School, June 2013
Overview
• Detector Systems Centre, Rutherford Appleton Laboratory – some examples
http://dsc.stfc.ac.uk/Capabilities/CMOS+Sensors+Design/Follow+us/19816.aspx
Wafer scale 120 x 145 mm chip for medical imaging
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TALENT Summer School, June 2013 54
Fast CMOS detectors based on drift charge collection:detectors in HVCMOS-processes and the CMOS
processes with a high resistive wafer
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TALENT Summer School, June 2013 55
Drift based detector: HVMAPS
• HVMAPS rely on the charge collection by drift• Fast charge collection – high radiation tolerance• The key is the use of a high voltage n-well in a relatively highly doped substrate• Pixel electronics is embedded in the n-well• Two concepts:• High Ohmic Monolithic Pixels - LePIX – relies on a special CMOS process with high resistive
substrate (CERN, Geneve)• HVCMOS (or smart diode arrays - SDAs) – use a commercial HVCMOS process (CPPM,
CERN, Bonn, LBNL, Geneve, Göttingen, Manchester and Heidelberg)
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TALENT Summer School, June 2013 56
HVCMOS detectors (smart diode arrays)
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TALENT Summer School, June 2013 57
P-Substrat
Verarmungszone
“Smart” Diode
n-Wanne
Pixel
“Smart diode” Detector
Drift Potentialenergie (e-)
• Smart diode array
SDA
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TALENT Summer School, June 2013
SDA
• Collected charge causes a voltage change in the n-well.• This signal is sensed by the amplifier – placed in the n-well.
PMOS
N-well
NMOS
DS
G
holes
electrons
P-well
P-substrate
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TALENT Summer School, June 2013
SDA
• Collected charge causes a voltage change in the n-well.• This signal is sensed by the amplifier – placed in the n-well.
P-substrate
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TALENT Summer School, June 2013
SDA
P-substrate
• Collected charge causes a voltage change in the n-well.• This signal is sensed by the amplifier – placed in the n-well.
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TALENT Summer School, June 2013 61
Intelligent pixel
ComparatorCR-RC
CSA
N-well
AC coupling
3.3 V
-50 V
P-substrate
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Intelligent pixel
ComparatorCR-RC
CSA
N-well
AC coupling
3.3 V
-50 V
P-substrate
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Intelligent pixel
ComparatorCR-RC
CSA
N-well
AC coupling
3.3 V
-50 V
P-substrate
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Intelligent pixel
ComparatorCR-RC
CSA
N-well
AC coupling
3.3 V
-50 V
P-substrate
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Intelligent pixel
ComparatorCR-RC
CSA
N-well
AC coupling
3.3 V
-50 V
P-substrate
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Intelligent pixel
ComparatorCR-RC
CSA
N-well
AC coupling
3.3 V
-50 V
P-substrate
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Intelligent pixel
ComparatorCR-RC
CSA
N-well
AC coupling
3.3 V
-50 V
P-substrate
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TALENT Summer School, June 2013
3D layout of a “smart diode”
40 µm
3D layout generated by GDS2POV software
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TALENT Summer School, June 2013
Applications
• Mu3e experiment at PSI and ATLAS upgrade option
5 m
m
69
Mu3e prototype chip
4.4
mm
ATLAS prototype chip
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TWELL - MAPS
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TWELL MAPS
Triple-well MAPS
Deep n-well 2. n-well
P-well
NMOS PMOS
Pixel
Epi-layer Diffusion
Energy (e-)
Signal lossSignal collection
• Collection electrode is a deep n-well• To avoid crosstalk, secondary n-well is used for digital electronics• Rely on diffusion, implemented in low voltage CMOS processes• Collaboration: INFN Pisa, Pavia, Trieste, Padova, Torino, Bologna
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TWELL MAPS
• APSEL Chips for B-factories
The APSEL4D MAPS chip bonded to the chip carrier.
Schematic drawing of the full Layer0 made of 8 pixel modules mounted around the beam pipe with a pinwheel arrangement.
“Thin pixel development for the SuperB silicon vertex tracker”, NIMA vol. 650, 2011
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Special monolithic technologies
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SOI
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SOI technology
• An SOI detector consists of a typically micrometer-thick electronics layer, an insulation silicon-dioxide layer (called buried oxide) and a high resistance substrate. (In our case ~500m thick, 7.1kcm, n-type FZ substrate.)
• The sensor has the form of a matrix of pn junctions, the collecting regions are p-type diffusion implants in the n-substrate.
• A connection through the buried oxide is made to connect the readout electronics with electrodes
• The industrial SOI detector technology based on Lapis semiconductor (formerly OKI) 200nm (or 150nm) CMOS fully depleted process has been developed within a collaboration between industry and institutes
Hi re
s. N-typ
e su
bstra
teE
lectro
nics la
yer
Bu
ried
oxid
e
Connection
Energy (h+)
CMOS pixel electronics
P+ collecting electrode
• Originally developed at University of Krakow• The development continued in collaboration
with industry (OKI and Lapis)• The collaboration is now led by KEK, Japan
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TALENT Summer School, June 2013
MPW (Multi Project Wafer) runMPW (Multi Project Wafer) run ~Twice per Year~Twice per Year
76
Multi project runs organized by KEK
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SOI technology
• SOI technology can be used for x-ray detection thanks to its thick sensitive region• Example of an x-ray detector: INTPIX4
15.4 mm
10.2
mm
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DEPFET
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DEPFET
Pixel
PMOS Ext. gate
Int. gate
Clear
Signal collection
Signal clearing
N-substrate (depleted)
P-type backside contact
Potential en. (e-)
Elect. Interact.
Int. gate
• DEPFET is a special MOS-based monolithic detector produced at Semiconductor Laboratory (MPI) Munich
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DEPFET
Pixel
PMOS Ext. gate
Int. gate
Clear
Signal collection
Signal clearing
N-substrate (depleted)
P-type backside contact
Potential en. (e-)
Elect. Interact.
Int. gate
• DEPFET uses high resistive substrate with depleted layers up to 600 um – very high signal to noise ratio
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DEPFET
Pixel
PMOS Ext. gate
Int. gate
Clear
Signal collection
Signal clearing
N-substrate (depleted)
P-type backside contact
Potential en. (e-)
Elect. Interact.
Int. gate
• DEPFET structure is very innovative – the signals are collected in internal gates• Strong points: small “capacitance” of internal gate – high signal amplification• Absence of reset noise, special thinning technique assures mechanical stability of the thin
detectors
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DEPFET
• Application in high energy physics: Belle II pixel detector at KEK• 10 cm long detector modules fixed at the edges without any other supporting structure
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DEPFET
• Only silicon modules
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DEPFET
DCD DEPFET SWITCHER
• Since pixel electronics is very simple (only one transistor) and no periphery circuits can be realized at the detector substrate, external ASICs needed for the readout
• Semi-Monolithic concept
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• Thank you!