Taikan Suehara, CALICE electronics and DAQ WS, 16 Dec. 2014 page 1

Combined DAQ& DAQ Task force

Taikan Suehara(Kyushu University, Japan)

Taikan Suehara, CALICE electronics and DAQ WS, 16 Dec. 2014 page 2

• All CALICE Tech. proto. are based on the same chip family – ROC chips by Omega

• There existed a common DAQ elec. by UK

• Needs for common DAQ– Minimal effort in total– Common TB (towards real experiment)– Hybrid (Si + Sc)

• Groups are rival as well as collaborators– Need ‘neutral’ common system – difficult– Kyushu is at good position for neutralness

Combined DAQ: overview

Taikan Suehara, CALICE electronics and DAQ WS, 16 Dec. 2014 page 3

• Nov. 26 – Dec. 8, 2014, CERN PS– 2nd period of Scintillator testbeam

• 15 Sc layers (3 EBU + 12 HBU)• 1 Si layer (FEB8, from Kyushu)

Sc + Si TB at CERN

Taikan Suehara, CALICE electronics and DAQ WS, 16 Dec. 2014 page 4

Si and Sc DAQ

Si CCC

SKIROC2 SPIROC2

Si DIFs Sc DIFs

GDCC/LDA xLDA

PC PC

Sc CCC

Flexi cableHDMIEthernetCoaxial

ClockReadout cycle

Spill

Taikan Suehara, CALICE electronics and DAQ WS, 16 Dec. 2014 page 5

• Independent CCC board for Si and Sc– Difference on fast command specification

(should be fixed later)• Clock - Sc clock output connected to Si• Spill & busy

– Sc CCC creates output of “Readout cycle (RC)” TTL signal by (Spill & !Busy) to Si CCC

– All busy from Sc layers combined at Sc CCC

– Si converts RC up to start, down to stop– Si busy is not treated

Synchronization of clock/spill

Taikan Suehara, CALICE electronics and DAQ WS, 16 Dec. 2014 page 6

Combined DAQ for Si + Sc

Run control

Labview calicoes/pyrame

Sc hardware Si hardware

Sc data Si data

Data collector

LCIO file(s)

Event display(not finalized)

start/stop

EUDAQ

start/stoprun #

Taikan Suehara, CALICE electronics and DAQ WS, 16 Dec. 2014 page 7

Screenshot of EUDAQ

Master PC (Linux): EUDAQ + CALICOES (Silicon)Slave PC (Windows): LabView (Scintillator)Successfully took data for more than a week

Taikan Suehara, CALICE electronics and DAQ WS, 16 Dec. 2014 page 8

Output files

Taikan Suehara, CALICE electronics and DAQ WS, 16 Dec. 2014 page 9

A quick result – BX sync

Muon beam, All Sc hits to be compared with Si hits~ 1000 Readout cycles accumulatedDetailed analysis including tracking of Si+Sc is ongoing

Hits to be combined

Combinatorial

Taikan Suehara, CALICE electronics and DAQ WS, 16 Dec. 2014 page 10

• Talk to Labview is not efficient– Maybe better to directly talk to LDA

• BUSY treatment– Si busy cannot be used now– Common CCC is better to treat busy

CCC specification should be common• Online monitoring / quality check• More layers of silicon• Well-defined LCIO structure

Combined DAQ: ToDo

Taikan Suehara, CALICE electronics and DAQ WS, 16 Dec. 2014 page 11

CALICE DAQ Task Force

Taikan Suehara, CALICE electronics and DAQ WS, 16 Dec. 2014 page 12

• The first trial is successful, but many adhocs– Independent CCC– No busy synchronization

• Task force for CALICE-wide DAQ formed– Silicon: Remi, Frederic, TS (coordinator)– Scintillator: Mathias, Jiri– SDHCAL: Laurent

• Next TB: Si+SDHCAL next year (probably)

Next step: CALICE DAQ TF

Taikan Suehara, CALICE electronics and DAQ WS, 16 Dec. 2014 page 13

• The goal of to deliver the proof that the following combinations of running are possible, SiW-Ecal/SDHCAL, SiW-Ecal/AHCAL (or equivalently SiW-Ecal/ScW-Ecal), ScW-Ecal/AHCAL.

• DAQ task Force is to work out a set of technical questions (hardware and software) and propose and enact concrete means to answer these questions, based on the hardware that is currently available.

• It is asked to the group to report regularly at the Technical Board and provide a documentation summarising the solutions after one year. In the second year, the task consist in the critical expertise of the running setups of the combined tests.

Task Force: Mandate

Taikan Suehara, CALICE electronics and DAQ WS, 16 Dec. 2014 page 14

SiECAL ScE/AHCAL

SDHCAL

Manpower ** *** *

Strategy Minimal mod Full replace Minimal mod

CCC UK original ZedBoard DCC

CCC clock 50 MHz 40 MHz 50 MHz

8b/10b encode

yes No yes

BX clock (TB) 2.5 MHz 250 kHz

DIF-LDA HDMI HDMI USB+HDMI?

LDA GDCC ZedBoard Raspberry+DCC

LDA-PC Ethernet raw TCP TCP

Software Calicoes Labview(tentative)

DIM(from DELPHI)

Personal comparison

Taikan Suehara, CALICE electronics and DAQ WS, 16 Dec. 2014 page 15

• Common master clock frequency– To assure simultaneous BX counting

• Common BX clock frequency• BUSY treatment• Common CCC? or just clock synchronization?• High level DAQ software (EUDAQ?)

– Run control, event building, run number, monitoring,…

• Common data format (LCIO class)

• Partial or optional sharing of firmware and software

• etc.

Things to be considered

Taikan Suehara, CALICE electronics and DAQ WS, 16 Dec. 2014 page 16

• After the first meeting, my impression is that reaching to the agreement about things shown in the previous slide is not easy. we need some time to get consensus

• We will firstly get informed more about each system, by reporting about each system from each expert.

• Monthly regular meeting with flexibility to change the frequency.

How to Proceed

Taikan Suehara, CALICE electronics and DAQ WS, 16 Dec. 2014 page 17

• Effort to re-integrate CALICE DAQ is critical towards combined TB and real ILC detector.

• First trial of Si+Sc combination was successful though some issues remained.

• We shall move to more generic CALICE DAQ with an experts’ Task Force.

• Any inputs/opinions from experts/non-experts are highly welcome.

Summary