Altera® Cyclone IITM FPGA Prototype Board

Level-up QB-FPGA200EP2C Starter Kit

User’s Guide ver. 1.0

QuantumBase Inc, 101 changubguan, Korea Institute of Ceramic Eng. & Tech.(KICET)

233-5, Gasandong, Geumchongu, Seoul, 153-023, R.O.Korea

TEL: +82-70-7122-7728, FAX: +82-2-3282-7740,

Website: www.quantumbase.com, www.funchip.co.kr

Email: support@quantumbase.com

©2005-2009 by QuantumBase Inc., All rights reserved.

1

CONTENTS 1 Introduction ......................................................................................................................................................... 3

2 Items in QB-FPGA200EP2C Starter Kit............................................................................................................. 4

3 Component Description of QB-FPGA200EP2C Starter Kit ............................................................................... 6

Cyclone II EP2C5Q in the -8 speed grade FPGA Device .................................................................................. 6

QB-EP2C208-BK Main Board ............................................................................................................................ 8

QB-ALTERA-AT ByteBlasterII .......................................................................................................................... 8

4 QB-EP2C208-BK Main Board............................................................................................................................ 9

Board Installation .............................................................................................................................................. 10

Kyes................................................................................................................................................................... 11

DIP switch.......................................................................................................................................................... 12

FND(4 digit numeric display) ............................................................................................................................ 12

LEDs .................................................................................................................................................................. 14

Power Block ...................................................................................................................................................... 14

Extension Port (EXTA, EXTB, EXTC) .............................................................................................................. 14

Serial Communication Port (USART)................................................................................................................ 17

Character LCD................................................................................................................................................... 18

LCD Module initialization and Display Sequence ............................................................................................. 27

2

5 Port MAP........................................................................................................................................................... 29

6 Tutorial.............................................................................................................................................................. 32

6.1 Design Flow on Quartus II ......................................................................................................................... 33

6.2 A simple schematic design example ......................................................................................................... 35

6.2.1 Creating Your Own Project ......................................................................................................... 36

6.2.2 Setting Unused pins .................................................................................................................... 41

6.2.3 Create a New Schematic Design File ......................................................................................... 43

6.2.4 Pin Assignment............................................................................................................................ 49

6.2.5 Simulation .................................................................................................................................... 54

6.2.6 Programming FPGA..................................................................................................................... 60

6.3 A VHDL design example ........................................................................................................................... 65

6.3.1 Creating Your own Project.......................................................................................................... 66

6.3.2 Setting Unused pins .................................................................................................................... 71

6.3.3 Create a New VHDL Design File ................................................................................................ 73

6.3.4 Pin Assignment............................................................................................................................ 77

6.3.5 Simulation .................................................................................................................................... 82

6.3.6 Programming EPCS1 Configuration ROM................................................................................... 83

7 Useful Links ...................................................................................................................................................... 91

8 Appendix ........................................................................................................................................................... 92

3

1 Introduction Thank you for purchasing QuantumBase’ Level-up series QB-FPGA200EP2C Starter Kit. The FPGA kit has every thing you

need to start designing and learning with the powerful features of Altera® Cyclone II™ FPGA devices. The QB-FPGA200EP2C

Starter Kit allows you to implement your own designed digital circuit easily with minimal design overhead. Whenever you want to

learn about FPGA design, or have a specific design implementation to complete, the starter kit will jump-start of your own Cyclone

II™ efforts. The kit provides an Altera’s Byte Blaster II compatible QB-Altera-AT programmer, which supports Altera’s active

serial devices and JTAG devices.

Altera’s Quartus II is a state of the art software tool which allows coding, compilation and simulation of complex digital circuit

designs in a programmable logic environment, and the recent free version of Quartus II web edition can be downloaded from

Altera’s website http://www.altera.com/products/software/quartus-ii/web-edition/qts-we-index.html.

The SignalTap II Logic Analyzer, available with TALKBACK enabled, a software module in Quartus II, is a powerful system-

level debugging tool that captures and displays real-time signal behavior, allowing you to observe interactions between hardware

and software in system designs.The Quartus II software allows you to select the signals to capture, when signal capture starts, and

how many data samples to capture. You can use a QB-Altera-AT programmer we provide with to employ full features of the

SignalTap II Logic Analyzer. The Quartus II Web Edition is free for everyone regardless of its use. All the user has to do is enjoy it.

With Level-up QB-FPGA200EP2C Starter Kit, you can easily learn and enjoy designing, implementing, and system level

debugging of your own digital circuit

4

2 Items in QB-FPGA200EP2C Starter Kit QB-EP2C208BK main board

QB-Altera-AT ByteBlaster II compatible board

Male to male 25 pin parallel cable

Male to female 9 pin serial cable

DVD (Datasheets, Manual, Tutorial, Quartus II 8.1 Web edition )

(Note: Please keep the QB-EP2C208-BK and QB-Altera-AT board away from conducting materials while they are powered.)

(Note: External 9VDC, 2.1mm coaxial plug, center positive and >0.45A output current adaptor should be used for this kit.)

(a) (b)

Fig 2.1 (a)QB-EP2C208-BK Main board (b)QB-ALTERA-AT ByteBlasterII

5

(Warning! Please reserve all unused pins as inputs, tri-stated by select this option on the Unused Pins tab of the Device & Pin

Options dialogue box, in order to prevent the circuit board from being damaged by unwanted short current between the DIP switch

and unused FPGA pins)

(WARNING! When the Extension Ports are not used in your design, please DO NOT touch them with any conducting materials.

Reserving all unused pins as inputs, tri-stated can be the good choice to avoid damages by unwanted short current. )

Please refer to the tutorial chapter for reserving unused pins as inputs

Please DO NOT touch the pins

with any conducting materials!

DIP switch

ON

1 2 3 4 5 6 7 6

Please keep the switches off when the switches are not used in your design.

Fig 2.2 Location of the extension port and the DIP switch.

6

3 Component Description of QB-FPGA200EP2C Starter Kit

Cyclone II EP2C5Q in the -8 speed grade FPGA Device

Cyclone EP2C3Q FPGA device contain a two-dimensional row- and column-based architecture to implement custom logic. Column and row

interconnects of varying speeds provide signal interconnects between LABs and embedded memory blocks. The logic array consists of LABs, with

16 LEs in each LAB. An LE is a small unit of logic providing efficient implementation of user logic functions. LABs are grouped into rows and

columns across the device. EP2C5Q FPGA device has 4,608 LEs. M4K RAM blocks are true dual-port memory blocks with 4K bits of memory plus

parity (512 bits). These blocks provide dedicated true dual-port, simple dual-port, or single-port memory up to 36-bits wide. These blocks are

grouped into columns across the device in between certain LABs. The EP2C5Q device provides a global clock network and two PLLs. The gelobal

clock network consists of eight global clock lines that drive throughout the entire device. The global clock network can provide clocks for all

resources within the device, such as IOEs, LEs, and memory blocks. The global clock lines can also be used for control signals. The Cyclone €II

PLL provides general-purpose clocking with clock multiplication and phase shifting as well as external outputs for high-speed differential I/O

support.

Table 3.1 Cyclone II EP2C5Q Device Features

Logic Elements ( LEs ) 4,608 Phase Lock Loop Count ( PLL ) 2

M4K RAM Blocks ( 4608 bits/block ) 26 Maximum user I/O 158

Total RAM Bits 119,808

7

QB-EP2C208-BK Main Board

Specificat Descr

FPGA D EP2C5Q2 fault) Altera II FPGA Device ( upgradable to EP2C8Q208C8)

Configu EPCS1 (d Altera ration ROM(Active serial mode) (upgradable to EPCS4)

Clock 50MHz Main Clock 50MH

LCD 16 x 2 Character LCD Detac

LED 8 LEDs 8 LED

FND 4 Digits 4 Digi

4 Tactile switches User d

itch 8 bit DIP Switches User d

on I/O 34pin Extension Port 90 use

Power 5V,3.3V,1.5V DC Power ---

QB-ALTERA-AT ByteBlasterII

Byte Blaster II compatible QB-Altera-AT programmer su

Cyclone II, Stratix, Stratix II, EPSCX, and EPCX devices.

iption

Cyclone

Configu

8

z external clock is supplied to the CLK2 port of the FPGA device

hable character LCD

s

t Numeric Displays

efined Keys

efined switches

r IO, 6 of GNDs, 6 of 3.3V outputs

pports Altera’s active serial devices and JTAG devices such as

evice

ration

Keys

DIP Sw

Extensi

ion

08C8 (de

efault)

Altera’s

Cyclone,

4 QB-EP2C208-BK in Board

FND

Power S/W

50MHz Oscillator

Dip S/W

Ta ile S/W

Power Jack LCD Back Light Connector

LCD Connector

RS-232 Connector

Ma

Power Indicator

Active Serial Rom Conf. Port

JTAG port

ct

9

Extension Ports

Fig 4.1 QB- EP2C208-BK Baord Layout

10

Board Installation

.

+ - JTAG communication port for the EP2C5Q208 cyclone device

9V DC Power

Parallel cable connector for the communication between PC and QB-Altera-AT Byte blaster II

Active serial device communication port for EPCS1 configuration ROM

Fig 4.2 Board installation for programming the cyclone device directly through JTAG port

11

Kyes

4 tactile switches for keying in are installed with a 10 kohm pull up resistor as shown Fig 4.3. Thus the default values at the FPGA

pins connected to the keys are “Logic High.” Pressing a key down changes the value into “Logic Low.”

VDD VDD VDD VDD

KEY1 KEY2 KEY3 KEY4

(Pin# 67)(Pin# 64)

(Pin# 69)(Pin# 68)

FPGA

Fig 4.3 Tactile Switches

12

DIP switch

Another keying-in device installed is an 8 pole DIP switch, which would be helpful to set fixed parameter of a designed digital

circuit. When the switch is on, the FPGA pins connected shows it value as “Logic high”.

(Warning! When the DIP switch are not used in your design, please keep all the 8 switches off, or reserve all unused pins as inputs,

tri-stated by select this option on the Unused Pins tab of the Device & Pin Options dialogue box, in order to prevent the circuit

board from being damaged by unwanted short current between the DIP switch and unused FPGA pins)

FND(4 digit numeric display)

Fig. 4.4 shows internal component connection of the installed FND of 4 digit numeric display.

c

b

a

dpd

e

f

g

( a )

COM1 COM2 COM3 COM4

a b c d e f g dp( b )

Fig 4.4 Internal component connection of the FND

13

As shown in Fig. 4.4, COM1, COM2, COM3, and COM4 are the digit selection ports connected to the cathodes of LEDs for each 4

digits. In addition, a, b, c, d, e, f, g, and dp ports are the segment selection port of a digit, which are connected to the anodes of the

internal LEDs. By scanning COM1~COM4 ports with proper duration and frequency, 4 different digits can be simultaneously

displayed.

As shown Fig. 4.5, SEGa~g and SEGdp ports of the FNDs are connected through resistor arrays to limit the current flowing through

the segments.

Fig 4.5 Simplified Block diagram between FPGA and the 4 digit numeric display

14

LEDs

The QB-EP2C208-BK main board comes populated with 8 discrete indicator LEDs, which are connected through 330 ohm resistor

array to the FPGA ports. Asserting port will turn the connected LED on.

Power Block

The QB-EP2C208-BK has 3 regulator group which supply 1.5V, 3.3V, and 5V from a wall mount type 9VDC/500mA power supply

respectively.(US or Asian/European model, depending on which was ordered) When the power are supplied to the QB-EP2C208-

BK board properly, the power LED at upper right of the main board stays on.

Extension Port (EXTA, EXTB, EXTC)

Three 34-pin extension port groups, named EXTA, EXTB, EXTC are placed on top, right, and bottom sides of the QB-EP2C208-

BK main board. All pin headers of the extension port are placed on 0.1 inch spacing to allow the use of standard prototyping

module with the QB-EP2C208-BK. As shown in Fig. 4.6, among 34 pins of each extension port group, 2 pins are assigned to GND,

and the additional 2pins 3.3VDC power. A user should note that total power dissipation of the prototyping module must not exceed

150mA

(WARNING! When the Extension Ports are not used in your design, please DO NOT touch them with any conducting materials.

Reserving all unused pins as inputs, tri-stated can be the good choice to avoid damages by unwanted short current.)

15

(WARNING! Do not directly connect 5V devices to the QB-EP2C208-BK extension pins. See the Cyclone device handbook, which

can be downloaded at http://www.altera.com/literature/hb/cyc2/cyc2_cii5v1.pdf , for proper connection method.)

(WARNING! Improper connection to the extension ports may cause serious problem to the main FPGA device.)

Fig 4.6 Extension port configuration

16

17

Serial Communication Port (USART)

9pin D-sub connector is installed for RS-232 communication between the Cyclone II FPGA device, as shown in Fig. 4.7.

(Note: You can see blinking light of the TXD and RXD diodes during communication. They are installed on the upper right side of

the QB-EP2C208-BK main board.)

MCU RS-232 Transceiver

9Pin D-SUB( Female )

RxD

TxD

RXD1( #42 )

TXD1( #43 )

R2OUT R2IN

T2IN T2OUT

TD(#3)

RD(#2)

Fig 4.7 Block diagram of the USART block

18

Character LCD

Supplied 16 X 2 character LCD with QB-EP2C208-BK board is designed to be detachable from the board. It can be controlled

through the three control line and 8-bit data bus. The LCD’s main controller is widely used LCD controller IC of S6A0069

(Samsung semiconductor) and is easy to use.

A

12

14 13

K

Fig 4.8 16x2 Character LCD Module

Fig 4.9 shows how to attach the LCD module to the QB-EP2C208-BK Cyclone II main board. As shown in Fig. 4.9 it can be easily

installed by just connecting the pin header at the left side of the LCD module to the pin header socket on the FPGA main board. In

addition, LCD back lighting is possible by just connecting a jumper cable between A & K marked pads and the pin header at the

upper right of the FPGA main board ( The jumper cable for the back light is not supplied in the kit)

19

Please connect the pin header of the LCD into the pin header socket marked “Char. LCD” on the FPGA main board in order to use the 16x2 character LCD

A

12

14 13

K

A

K

When you want to use LCD back light, you can wire these pads. (Note that the only pads with the same mark should be connected each other.)

A

K

Fig 4.9 16x2 Character LCD Module Installation

Fig. 4.10 shows the connection scheme among the target FPGA, EXTB ports and the LCD. As shown in Fig. 4. 10, the control lines

and the data bus are shared by some of the extension ports of EXTB06 ~ EXTB16. Thus you should detach the LCD module from

20

the board when you need to use the extension ports freely.

( Pleaser refer to “Port MAP” in Chapter 5 for more connection details.)

Fig 4.10 Block diagram of the LCD connection among the target FPGA, EXTB ports and the LCD

21

Table 4.1 Character LCD’s timing

22

Fig 4.11 Write Mode Timing Diagram

Fig 4.12 Read Mode Timing Diagram

23

There are some important registers, flags, and memory in the LCD module as shown below, and a user need to understand them.

Busy Flag (BF) : When BF = “High”, it indicates that the internal operation is being processed. So during this time the

next instruction cannot be accepted. BF can be read, when RS = Low and R/W = High (Read Instruction Operation),

through DB7 port. Before executing the next instruction, be sure that BF is Low

Address Counter (AC) : AC stores DDRAM/CGRAM address, transferred from IR. After writing into (reading from)

DDRAM/CGRAM, AC is automatically increased (decreased) by 1. When RS = “Low” and R/W = “High”, AC can be

read through DB0 ~ DB6 ports.

Display Data RAM (DDRAM) : DDRAM stores display data of maximum 80 X 8 bits(80 characters), but the LCD

module installed can display 16 characters by 2 lines. Fig. 4.13 shows the DDRAM address with respect to the character

location.

00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F

40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F

Fig 4.13 The character location v.s DDRAM address(default)

Character Generator ROM (CGROM) : CGROM has 204 character patterns of 5 x 8 dots, and 32 character patterns of 5 x

11 dots as shown in Table 4.2.

24

Character Generator RAM (CGRAM) : CGRAM has up to 5 x 8 dots, 8 characters. By writing font data to CGRAM, user

defined characters can be used.

Table 4.2 Stored character sets

25

Table 4.3 shows the instruction sets of the LCD Module. When you make a LCD control logic, please special care must be taken to

grantee the execution time requirements of each instructions.

Table 4.3 Instruction Sets of the LCD Module

26

(When an FPGA logic with checking the Busy Flag (DB7) is made, it must be necessary 1/2 fosc is necessary for executing the next

instruction by the falling edge of the 'E' signal after the Busy Flag (DB7) goes to "LOW".)

Clear Display : clear all the display data by writing “0x20”(space code) to all DDRAM address, and set DDRAM address

27

to 0x00 into address counter. Return cursor to the original status,

Return Home : set DDRAM address to “0x00” into the address counter. Return cursor to its original site and return

display to its original status, if shifted. Contents of DDRAM does not changed

Entry Mode Set : set the moving direction of cursor and display. When I/D = “High”, cursor/blink moves to right and

DDRAM address is increased by 1. When I/D = “Low”, cursor/blink moves to left and DDRAM address is decreased by 1.

Display On/Off Control : control Display(D), cursor(C), and Blink(B) ON/OFF 1bit register. When the bit is set, the

function is enable.

Cursor or Display Shift : Shifting of right/left cursor position or display without writing or reading of display data.

Function Set : 8bit data interface(DL=1), 2 lines(N=1), and 5x8 font(F=0) is recommended to be selected in using QB-

EP2C208-BK board. Please refer to S6A0069 data sheet on the document CDROM for more details.

Set CGRAM address : Set CGRAM address to AC.

Set DDRAM address : Set DDRAM address to AC.

Read BF & address : Read Busy Flag(BF) and address counter.

LCD Module initialization and Display Sequence

Wait for the initialization of LCD Module( > 30ms) after system reset

Perform Display On/Off Control command

28

Perform Entry mode set command

Set DDRAM address(1st line)

Send character data to display in series (1st Line)

Set DDRAM address(2nd Line)

Send character data to display in series (2nd Line)

29

5 Port MAP FPGA Pin# Board Connection FPGA Pin# Board Connection FPGA Pin# Board Connection

Clock LED 68 KEY223 CLK0 35 LED1 (D1) 69 KEY127 CLK2 37 LED2 (D2) EXTA 131 CLK5 39 LED3 (D3) 70 EXTA30132 CLK4 40 LED4 (D4) 72 EXTA29

UART 41 LED5 (D5) 74 EXTA283 TXD 43 LED6 (D6) 75 EXTA274 RXD 44 LED7 (D7) 76 EXTA26

FND 45 LED8 (D8) 77 EXTA255 SEGE DIP S/W 80 EXTA246 SEGA 46 DIP1 81 EXTA238 SEGF 56 DIP2 82 EXTA22

10 SEGB 57 DIP3 84 EXTA2111 SEGG 58 DIP4 86 EXTA2012 SEGC 59 DIP5 87 EXTA1913 SEGDP 60 DIP6 88 EXTA1814 SEGD 61 DIP7 89 EXTA1730 FND4 63 DIP8 90 EXTA1631 FND3 KEY 92 EXTA1533 FND2 64 KEY4 94 EXTA1434 FND1 67 KEY3 95 EXTA13

“FPGA pin #” column shows the FPGA pin number itself, and “Board Connection” column peripheral information which connected

to the FPGA pins at the same row. (Note: Installed 50MHz clock is initially connected to pin 27, CLK2.)

30

(Continued) FPGA Pin# Board Connection FPGA Pin# Board Connection FPGA Pin# Board Connection

96 EXTA12 133 EXTB22 164 EXTB0197 EXTA11 134 EXTB21 EXTC 99 EXTA10 135 EXTB20 165 EXTC30101 EXTA09 137 EXTB19 168 EXTC29102 EXTA08 138 EXTB18 169 EXTC28103 EXTA07 139 EXTB17 170 EXTC27104 EXTA06 141 EXTB16 (DB7) 171 EXTC26105 EXTA05 142 EXTB15 (DB6) 173 EXTC25 106 EXTA04 143 EXTB14 (DB5) 175 EXTC24 107 EXTA03 144 EXTB13 (DB4) 176 EXTC23110 EXTA02 145 EXTB12 (DB3) 179 EXTC22 112 EXTA01 146 EXTB11 (DB2) 180 EXTC21

EXTB 147 EXTB10 (DB1) 181 EXTC20 113 EXTB30 149 EXTB09 (DB0) 182 EXTC19 114 EXTB29 150 EXTB08 (E) 185 EXTC18115 EXTB28 151 EXTB07 (RW_N) 187 EXTC17 116 EXTB27 152 EXTB06 (RS) 188 EXTC16117 EXTB26 160 EXTB05 189 EXTC15118 EXTB25 161 EXTB04 191 EXTC14127 EXTB24 162 EXTB03 192 EXTC13128 EXTB23 163 EXTB02 193 EXTC12

.(Note: The extension ports from EXTB06 to EXTB16 are shared by the character LCD control and data ports.)

.(Note: When you use EXTB06 ~ EXTB16 ports for the LCD, please set the I/O standards of the pin as 3.3V-PCI so that it can

safely communicate with the 5V operated LCD module)

31

(Continued) FPGA Pin# Board Connection

195 EXTC11197 EXTC10198 EXTC09199 EXTC08200 EXTC07201 EXTC06203 EXTC05205 EXTC04206 EXTC03207 EXTC02208 EXTC01

* Power output ports for external circuits

Power Output Port Extension port

DC 3.3V EXTA31, EXTA32, EXTB31,EXTB32 EXTC31, EXTC32

GND EXTA33, EXTA34, EXTB33,EXTB34 EXTC33, EXTC34

.(Warning: The total current of external circuits using the power from the extension ports should not be exceeded 200mA, so that

the FPGA board can be protected from unwanted electrical damage)

32

6 Tutorial Learning by example seems to be the best way to learn design and implementation procedures with Altera’s Quartus II and QB-

FPGA200EP2C starter kit. We are sure that you will learn the procedures easily just by following this tutorial.

Fist of all, please make sure if your QB-FPGA200EP2C starter kit have been installed properly as shown in Fig. 4.2. Secondly,

please check if Quartus II Web edition has been installed on your PC. If not, please download up-to-date version of Quartus II Web

edition with free of charge from Altera’s web site as shown below;

http://www.altera.com/products/software/quartus-ii/web-edition/qts-we-index.html.

and then install it on your PC.

The 8.1 or later version of the Quartus II is supplied completely free and doesn’t need any license to work.

Now, you are ready to do it yourself with this tutorial.

33

6.1 Design Flow on Quartus II

Yes

2. Make Design Files (Schematic, vhdl, or verilog HDL)

3. Compilation

Yes

Error?

No

No

Error?

4. Simulation

5. Programming & Verification

1. Creating a Project

Fig 6.1 Simplified design flow on Quartus II Environment

34

Fig. 6.1 shows the design flow on Quartus II environment. In order to design new circuits on Quartus II, user should create a new

Project managing all the design files easily. The file extention of the newly created Project file is .qpf (Quartus II Project File).

After creating the new project, user can start to design his or her own ciruit by schematic, VHDL or verilog HDL. The file

extentions of the shematic, VHDL, and verilog HDL design files are .bdf, .vhd, and .v, respectively. Whatever you may choose

your design method among shematic, vhdl and verilog, the rest procedures such as compilation, simulation and programing

procedure are exactly the same.

QuartusII compilation includes synthesis, place and route(fitting), and timing analysis procedures. During synthesis, QuartusII

analyzes the design files, optimizes the designed logic. After the synthesis, optimized logic is placed and routed on a user

specified FPGA and timiming analysis follows. After all the compilation process completes, device programming images, in the

form of Programmer Object Files (.pof ), and SRAM Object Files (.sof) are generated. Where the .pof is the file for programming

a configuration ROM and the .sof is the file for configurating a FPGA. If any error messages are found during the compilation

process, a user should go back to the first design stage, correct errors in his or her design file and recompile it.

After the successful compilation, a user can see how it works vertually by the simulation process. A user can make input vectors for

simulation easily by creating a Vector Waveform File (.vwf). The simulation results shows how the newly designed hardware would

response to the input vectors defined on the .vwf file. If the simulation results are exactly the same as a user expects, he or she can

verity the desinged hardware by programming FPGA or confgifuration ROM on the QB-EP2C208-BK board. Please refer to

http://www.altera.com/literature/manual/intro_to_quartus2.pdf for more details of the Quartus II software.

35

6.2 A simple schematic design example The tutorial in the section 6.2 shows a design procedure of a simple 2-input AND gate. The input and output device used in this

design are designated by red arrows in Fig. 6.3.1.

Connect Q

B-A

ltera

-A

T b

oard

(or Q

B

USB

bla

ste

r) to th

e JT

AG

port h

ere

for

pro

gra

mm

ing th

e C

yclo

ne II F

PG

A

LED

Keys

Fig. 6.2.1 The Key and LEDs used in this example

36

6.2.1 Creating Your Own Project Double clicking Quartus II web edition icon on your desktop starts the software tool. Fig. 6.2.1 shows the Quartus II graphical user

interface as it appears when you first start the software.

Fig. 6.2.1 Quartus II graphical user interface

37

In order to create your own project, choose File/New Project Wizard as shown in Fig. 6.2.2

Fig. 6.2.2 Choosing File/New Project Wizard

38

This invokes the “New Project Wizard:Directory, Name, Top-Level Entity” dialog box as shown Fig 6.2.3

Fig. 6.2.3 The first dialog box regarding “New Project Wizard”

Type the directory name in the working directory box or select the directory with Browse(…). Type a project name you are to create

in the project name box. In the top-level design entity box, top level entity name should be shown and it should be exactly the same

was the entity name in the design file. Let’s fill in the 3 boxes as shown in Fig. 6.2.3 in this tutorial course and click Next..

39

The Add Files page of the New Project Wizard appears. Since tutorial is a new project, there are no files to add to this project yet.

so just click Next.

(a) (b)

Fig. 6.2.4 (a)Add Files and (b)Family & Devices Settings pages of the New Project Wizard

Now the Family & Device Settings page of the New Project Wizard appears then. In the Family list, select Cyclone. In the Speed

grade list of the Filters group, select 8, and then select EP2C5Q208C8 in the Available devices box

40

To accept the default setting for the remaining wizard prompts and create the project, click Next and Finish in turn. The project is

now created. The top-level design entity name appears in the Hierarchy tab of the Project Navigator window.

(a) (b)

Fig. 6.2.5 (a)EDA Tool Settings and (b)Summary pages of the New Project Wizard

41

6.2.2 Setting Unused pins As mentioned in Chapter 2, users need to give care to unused pin status because the FPGA can be damaged seriously by

unintentional over current if both of the pin and a connected device are set as output and their output status are different from each

other. Reserving the unused pins as input and making it tri-stated is the very common method to address the problem. Thus users

can make the unused pins tri-stated by setting a option in Quartus II as shown below.

Fig. 6.2.6 Selecting Assignment menu

42

As shown in Fig. 6.2.6, choose Device… (Assignment menu). By clicking Device & Pin Options button as shown in Fig 6.2.7(a),

user can invoke Device & Pin Options dialogue box of Fig. 6.2.7(b). As shown in Fig. 6.2.7(b), select As inputs tri-stated in

Unused Pins Tab.

(a) (b)

Fig. 6.2.7 (a) Device Setting Window (b) Device & Pin Options dialogue box

43

6.2.3 Create a New Schematic Design File In this step you create a new schematic file called tutorial.gdf. this file is the top-level design entity of the tutorial project. Choose

File/NEW. When the Device Design Files tab of the NEW dialog box appears, select Block Diagram/Schematic File and click

OK.

Fig. 6.2.8 New dialogue box for creating new design file

44

In the invoked schematic editor as shown in Fig. 6.2.9, add 2-input AND gate, 2 input and 1 output pins by using the Symbol tool as

shown in Fig. 6.2.10(a) and Fig. 6.2.10(b).

Symbol tool

Orthogonal Node Tool

Fig. 6.2.9 Schematic Editor

45

(a) (b)

Fig. 6.2.10 Symbol tool when (a) a 2-input AND gate, named and2, is selected

and (b) a input pin, named input, is selected.

After adding the components, make connection between the AND gate and Pins by using the Orthogonal Node

Tools shown in Fig. 6.2.9. Please refer to Quaruts II hand book for more details about the schematic editor at

the Altera’s Website below;

http://www.altera.com/literature/hb/qts/quartusii_handbook.pdf

46

Now 2-input AND gate design on the schematic editor finished as shown in Fig. 6.2.11. Save the file as tutorial.bdf.

Fig. 6.2.11 Designed 2-input AND gate on the schematic editor

47

Now choose Processing/Start Compilation so that Quartus II makes full compilation of the .bdf file. If there are any errors, correct

errors and recompile it.

Fig. 6.2.12 Make full compilation of the Processing menu

48

“Full compilation was successful” message window appears when there are no errors in your schematic design.

Fig. 6.2.13 Captured image when the full compilation was successful

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6.2.4 Pin Assignment Since there are no errors in your design now, you should assign FPGA pins to physically connected peripheral resources. In

tutorial.bdf, 2 input pins of a and b, and 1 output pin c should be assigned to Key1, Key2, and LED1, respectively.

Referring to PORT MAP of Chapter 5, we can assign the input and output pins as shown in Table 6.2.1.

Table 6.2.1 Selected port map for this tutorial FPGA Pin# Board Connection Pin Name in the Design

69 KEY1 a68 KEY2 b35 LED1 c

Next page shows the way to assign pins in the Quartus II software tool.

50

Choose Assignment Editor (Assignment menu).

Fig. 6.2.14 Choosing Assignments/Assignment Editor for the pin assignment

51

Then the Assignment Editor appears with the Pin assignment category selected. In the Assignment Editor, double-click the To cell

and select the a input node name.

Fig. 6.2.15 Select port in the Assignment Editor

52

In the assignment Editor, double-click the Location cell and scroll down to select pin 69, an I/O pin.

Fig. 6.2.16 Select a pin in the Assignment Editor

53

Keep assigning remaining pins referring to Table 6.2.1

Fig. 6.2.17 Assignment Editor when all the pins are completely assigned.

After the pin assignment is completed, close the Assignment Editor, saving the assignment changes. Now choose Processing/Start

Compilation again, and you are ready to implementing your design into EP2C5Q208C8 FPGA with “Full compilation was

successful” message window.

54

6.2.5 Simulation In order to verify the designed circuit by simulation, a Vector Waveform File is needed defining input stimulus of each input ports.

Choose File/NEW. When the NEW dialog box appears, select Vector Waveform File on the Other Files tab, then click OK.

Fig. 6.2.18 Other Files Tab in New dialogue box for creating new Vector Waveform File.

55

On the created waveform editor of the Vector Waveform File, choose Insert Node or Bus… on the menu invoked by clicking the

right button of your Mouse at the arrowed region.

Point here by clicking the right button

of your Mouse

Fig. 6.2.19 A waveform editor of the Vector Waveform File..

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Now you can see the Insert Node or Bus dialogue box as shown in Fig. 6.2.20. Click Node Finder…, and the Node Finder

dialogue box opens as shown in Fig. 6.2.21.

Fig. 6.2.20 Insert Node or Bus dialogue box

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On the Node Finder dialogue box, click List button first and all the input and output ports will be shown on Node Found region.

Clicking >> button selects all the nodes shown in Node Found Region. Click OK on the Node Finder then click OK on Insert

Node or Bus dialogue box.

Fig. 6.2.21 Node Finder dialogue box

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If all the added nodes are shown on the waveform editor, you can define input stimulus easily by dragging the time region where

you want to change status of, and clicking control buttons for editing the wave form as shown in Fig. 6.2.22. Save this file as

tutorial.vwf.

Fig. 6.2.22 Vector Waveform file after defining input stimulus.

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Now choose Processing/Start Simulation, and you can find simulated output waveform on the Simulation Waveform window as

shown in Fig. 6.2.23.

Fig. 6.2.23 Simulation result on the Simulation Waveform window.

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6.2.6 Programming FPGA The programmer allows you to use files generated by the Compiler to program and/or configure all Altera® devices supported by

the Quartus® II software. You can program or configure the EP2C5Q208C8 device in JTAG mode.

Fig. 6.2.24 Choosing Programmer in the Tools menu

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Choose Programmer (Tools menu), A new CDF(Chain Device File) opens in the Programmer window automatically listing the

tutorial.sof file as the current programming file

Fig. 6.2.25 Programmer window in the Tools menu

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In the Mode list of the Programmer window, select JTAG. When the Programmer window is first invoked, “No Hardware”

message would be shown at the right of the Hardware Setup… button. Then you need to set up programming hardware first. Clik

Hardware Setup and the Hardware Setup dialog box appears as shown Fig. 6.2.26(a)

(a) (b)

Fig. 6.2.26 (a)Hardware Setup and (b) Add Hardware dialog box.

Now, click Add Hardware and the Add Hardware dialog Box appears as shown Fig. 6.2.26(b). In the Hardware type list, select

ByteBlasterMV or ByteBlasterII and select LPT1 in the Port list. Click OK in the Add Hardware dialog Box and click Close in

the Hardware Setup dialog Box. Then save the current hardware setup information by choosing Save (File menu).

63

Fig. 6.2.27 Programmer window when the programming procedure was completed

Select Program/Configure check box of the tutorial.sof file, and click Start. “Configuration succeeded -- 1 device(s) configure”

message in the System tab, shows the success in the programming the FPGA device. On finishing programming, the

EP2C5Q208C8 FPGA device on the QB-EP2C208-BK board start to operate as you designed. LED1 will be on and off depending

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on the status of Key1 and Key2, based on the 2-input AND gate logic table. The design procedure in this tutorial is not optimal but

simple for novices. In order to learn the optimal design procedure, please refer to Quartus II handbook at the Altera’s Website

below;

http://www.altera.com/literature/hb/qts/quartusii_handbook.pdf

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6.3 A VHDL design example The tutorial in the section 6.3 shows a design procedure of the digital circuit to turn 8 LEDs on and off in regular sequence from left

to right. The input and output device used in this design are designated by red arrows in Fig. 6.3.1.

LEDs

Connect Q

B-A

ltera

-A

T b

oard

(or Q

B-U

SB

Bla

ste

r) to th

e A

ctiv

e S

eria

l Config

ura

tion p

ort

here

for p

rogra

mm

ing th

e E

PC

S1 R

OM

Use the KEY as

the Reset Key

Fig. 6.3.1 The Key and LEDs used in this example

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6.3.1 Creating Your own Project Double clicking Quartus II web edition icon on your desktop starts the software tool. Fig. 6.3.2 shows the Quartus II graphical user

interface as it appears when you first start the software.

Fig. 6.3.2 Quartus II graphical user interface

67

In order to create your own project, choose File/New Project Wizard as shown in Fig. 6.3.3

Fig. 6.3.3 Choosing File/New Project Wizard

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This invokes the “New Project Wizard:Directory, Name, Top-Level Entity” dialog box as shown Fig 6.3.4

Fig. 6.3.4 The first dialog box regarding “New Project Wizard”

Type the directory name in the working directory box or select the directory with Browse(…). Type a project name you are to create

in the project name box. In the top-level design entity box, top level entity name should be shown and it should be exactly the same

was the entity name in the design file. Let’s fill in the 3 boxes as shown in Fig. 6.3.4 in this tutorial course and click Next..

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The Add Files page of the New Project Wizard appears. Since tutorial is a new project, there are no files to add to this project yet.

so just click Next.

(a) (b)

Fig. 6.3.5 (a)Add Files and (b)Family & Devices Settings pages of the New Project Wizard

Now the Family & Device Settings page of the New Project Wizard appears then. In the Family list, select Cyclone. In the Speed

grade list of the Filters group, select 8, and then select EP2C5Q208C8 in the Available devices box

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To accept the default setting for the remaining wizard prompts and create the project, click Next and Finish in turn. The project is

now created. The top-level design entity name appears in the Hierarchy tab of the Project Navigator window.

(a) (b)

Fig. 6.3.6 (a)EDA Tool Settings and (b)Summary pages of the New Project Wizard

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6.3.2 Setting Unused pins As mentioned in Chapter 2, users need to give care to unused pin status because the FPGA can be damaged seriously by

unintentional over current if both of the pin and a connected device are set as output and their output status are different from each

other. Reserving the unused pins as input and making it tri-stated is the very common method to address the problem. Thus users

can make the unused pins tri-stated by setting a option in Quartus II as shown below.

Fig. 6.3.7 Selecting Assignment menu

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As shown in Fig. 6.3.7, choose Device… (Assignment menu). By clicking Device & Pin Options button as shown in Fig 6.3.8(a),

user can invoke Device & Pin Options dialogue box of Fig. 6.3.8(b). As shown in Fig. 6.3.8(b), select As inputs tri-stated in

Unused Pins Tab.

(a) (b)

Fig. 6.3.8 (a) Device Setting Window (b) Device & Pin Options dialogue box

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6.3.3 Create a New VHDL Design File In this step you create a new VHDL file called tutorial.vhd. this file is the top-level design entity of the tutorial project. Choose

File/NEW. When the Device Design Files tab of the NEW dialog box appears, select VHDL File and click OK.

Fig. 6.3.9 Device Design Files tab of the New dialogue box

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In the invoked editor, type the VHDL code as shown Fig 6.3.10, and save it as the file named tutorial.vhd by choosing Save (File

menu)

Fig. 6.3.10 VHDL code example for the tutorial

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Now choose Processing/Start Compilation so that Quartus II makes full compilation of the VHDL code. If there are any errors,

correct errors and recompile it.

Fig. 6.3.11 Make full compilation of the Processing menu

76

“Full compilation was successful” message window appears when there are no errors in the VHDL code.

Fig. 6.3.12 Captured image when the full compilation was successful

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6.3.4 Pin Assignment Since there are no errors in your design now, you should assign FPGA pins to physically connected peripheral resources. Referring

to the entity definition in the tutorial.vhd, you can notice that RstN, Clk, and 8bit LedOut port should be assigned.

Since 50MHz external clock is supplied to CLK2 (Pin number: 27) of the EP2C5Q208C8 FPGA device, you can assign pin 27 to

the input port Clk of the entity. Then assign pin 69 to input port RstN of the entity, pin 45 to LedOut[7], pin 44 to LedOut[6], pin

43 to LedOut[5], pin 41 to LedOut[4], pin 40 to LedOut[3], pin 39 to LedOut[2], pin 37 to LedOut[1], and pin 35 to LedOut[0].

Table 6.3.1 Selected port map for this tutorial FPGA Pin# Board Connection FPGA Pin# Board Connection FPGA Pin# Board Connection

23 CLK0 45 LED8 40 LED427 CLK2 44 LED7 39 LED369 KEY1 43 LED6 37 LED2

41 LED5 35 LED1

Next page shows the way to assign pins in the Quartus II software tool.

78

Choose Pins (Assignment menu).

Fig. 6.3.13 Choosing Assignments/Pin for the pin assignment

79

Then the Assignment Editor appears with the Pin assignment category selected. In the Assignment Editor, double-click the To cell

and select the Clk input node name.

Fig. 6.3.14 Select port in the Assignment Editor

80

In the assignment Editor, double-click the Location cell and scroll down to select pin 27, dedicated clock I/O pin.

Fig. 6.3.15 Select a pin in the Assignment Editor

81

Keep assigning remaining pins referring to Table 6.3.1

Fig. 6.3.16 Assignment Editor when all the pins are completely assigned.

After the pin assignment is completed, close the Assignment Editor, saving the assignment changes. Now choose Processing/Start

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Compilation again, and you are ready to implementing your design into EP2C5Q208C8 FPGA with “Full compilation was

successful” message window.

6.3.5 Simulation Simulation procedure is the same as that of the schematic based design as shown in the section 6.2.5. Thus the simulation procedure

is not included intentionally.

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6.3.6 Programming EPCS1 Configuration ROM In section 6.2, we show the programming procedure which configures FPGA using JTAG. Port. FPGA is the SRAM based device

and the configuration data get erased when the power switch is turned off. However, if we program the EPCS1 configuration ROM

installed on the QB-EP2C208-BK board, we can make the FPGA configured automatically by the EPCS1 ROM every time the

power supplied to the board. In order to do this, connect the flat cable of the QB-Altera-AT board to the Active Serial Conf. port

marked in Fig. 6.3.17. ( Please refer to Appendix of this document to learn how to set the EPCS1 as a configuration ROM. )

Connect Q

B-A

ltera

-A

T b

oard

(or Q

B-

USB

Bla

ste

r) to th

e A

ctiv

e S

eria

l

Config

ura

tion p

ort h

ere

for p

rogra

mm

ing

the E

PC

S1 R

OM

Fig. 6.3.17 Connection of the QB-Alter-AT ByteblasterII board for programming EPCS1 ROM

84

The programmer allows you to use files generated by the Compiler to program and/or configure all Altera® devices supported by

the Quartus® II software. You can program or configure the EPCS1 device in Active Serial mode.

Fig. 6.3.17 Choosing Programmer in the Tools menu

85

Choose Programmer (Tools menu), A new CDF opens in the Programmer window automatically listing the tutorial.sof file as the

current programming file. Since .sof file is for FPGA configuration, we need to change the programming file for the EPCS1 device.

Fig. 6.3.18 Programmer window in the Tools menu

86

In the Mode list of the Programmer window, select Active Serial Programming and click Yes on the following dialogue box.

Click Add File and select tutorial.pof as the programming file.

Fig. 6.3.19 Programmer window after the mode change

87

When the Programmer window is first invoked, “No Hardware” message would be shown at the right of the Hardware Setup…

button. Then you need to set up programming hardware first. Clik Hardware Setup and the Hardware Setup dialog box appears

as shown Fig. 6.3.20(a)

(a) (b)

Fig. 6.3.20 (a)Hardware Setup and (b) Add Hardware dialog box.

Now, click Add Hardware and the Add Hardware dialog Box appears as shown Fig. 6.20(b). In the Hardware type list, select

ByteBlasterMV or ByteBlasterII and select LPT1 in the Port list. Click OK in the Add Hardware dialog Box and click Close in

the Hardware Setup dialog Box. Then save the current hardware setup information by choosing Save (File menu).

88

Fig. 6.3.21 Programmer window when the programming procedure was completed

Select Program/Configure check box of the tutorial.pof file, and click Start. “Successfully performed operation” message in the

System tab, shows the success in the programming the FPGA device. Remove the flat cable of the QB-Altera-AT board from the

89

QB-EP2C208-BK board and the 8 LEDs, from LED1 to LED8 on the QB-EP2C208-BK board will start to turn on and off in turn.

Let’s turn off the power switch of the board and turn it on again. You can see the FPGA works same as before.

Although a simulation procedure is not shown in this tutorial, it is very important procedure for a hardware designer. Thus users

must learn how to make a simulation of their own designed hardware referring to QuartusII handbook. Moreover, SignalTapII

embedded logic analyzer of the QuartusII software is fully available in the QB-EP2C208-BK board. Thus you can observe the

signals of the designed hardware easily in the QB-EP2C208-BK board as shown in Fig. 6.3.22.

Fig. 6.3.22 Real time signal observation with the embedded SignalTap II Logic Analyzer

90

The Quartus II handbook by Altera will be helpful to you to learn the SignalTap II logic analyzer.

91

7 Useful Links How to use Quartus II

http://www.altera.com/literature/manual/intro_to_quartus2.pdf

http://www.altera.com/literature/hb/qts/quartusii_handbook.pdf

Cyclone II Device specification http://www.altera.com/literature/hb/cyc2/cyc2_cii5v1.pdf

Free HDL tutorial site

http://www.doulos.com/knowhow/

http://www.vhdl-online.de/tutorial/

Recommanded Books

Douglas J. Smith, “Hdl Chip Design: A Practical Guide for Designing, Synthesizing & Simulating Asics & Fpgas

Using Vhdl or Verilog,” Doone Publiscations, 1996

Bob Zeidman, and Robert M. Zeidman, “Verilog Designer’s Libaray,” Prentice Hall, 1999

Weng Fook Lee, “VHDL Coding and Logic Synthesis with Synopsys,” Academic Press, 2000

Roth, Charles H., Jr, “Digital System Design Using VHDL”, Thomson Learning, 1998

Wakerly, John F., “Digital Design : Principles and Practices” Prentice Hall, 1990

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8 Appendix As you can see in QB-EP2C208-BK Main Board feature table on page 7 in this document, the QB-EP2C208-BK board has a

EPCS1 configuration ROM. In order to make Quartus II generate proper configuration file for EPCS1, you should select the proper

configuration ROM (EPCS1) for your configuration ROM.

In order to do this, please choosing Assignment/Device… on the menu as shown below.

93

Then you can see the device setting dialog box as shown below.

Now please click the Device and Pin Options.. button to show the Device and Pin Options dialog box.

94

Finally, select EPCS1 as the configuration device and check “Generate compressed bitstreams”. Now you can genterate

configuration ROM file for EPCS1 by just recompile your project.

95

If there are any questions about our Level-up QB-FPGA200EP2C starter Kit, please feel free to send an

email at support@quantumbase.com or leave a message on our Web site, www.quantumbase.com.

Thank you!