SystemVerilog HDL - Electronics and Computer...
Transcript of SystemVerilog HDL - Electronics and Computer...
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SystemVerilog HDL - a programming language
module hdl1;
integer A, B, C;initial
beginA = 3;B = 10;$display( A, B, C );C = A+B;$display( A, B, C );for ( A = 3 ; A > 0 ; A = A-1 )
beginC = C*B;$display( A, B , C );
endend
endmodule
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SystemVerilog HDL - a programming language
Output
Compiling source file "hdl1.sv"Highest level modules:hdl1
3 10 x3 10 133 10 1302 10 13001 10 13000
Notes
• Operators include+ - / * != == > < >= <= && || !
• Constructs includeif else while repeat for case
• C is initially undefined: x
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SystemVerilog HDL - for hardware description
module hdl2;
timeunit 1ns; timeprecision 10ps;
logic [7:0] A, B, C, E; logic D;initial
beginA = 10;
#2.5ns B = 3;#2.5ns C = A + B;#4 D = A + B;#333ps E = {A[3:0],A[7:4]} + (B << 1);
end
initial$monitor( A," ",B," ",C," ",D," ",E," @time ",$realtime," ns");
endmodule
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SystemVerilog HDL - for hardware description
Output
10 x x x x @time 0 ns10 3 x x x @time 2.5 ns10 3 13 x x @time 5 ns10 3 13 1 x @time 9 ns10 3 13 1 166 @time 9.33 ns
Notes
• Time is cumulative.
• timeunit 1ns #4 is interpreted as #4ns
• timeprecision 10ps #333ps is rounded to #0.33ns
• $monitor monitors all changes in specified variables
• logic [n− 1:0] declares an n-bit variable
when A+B is assigned to D only the least significant bit is stored.
• Bit Manipulation Operators include: [:] {,} << <<< >> >>> & | ˆ ˜
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SystemVerilog HDL - for hardware description
Waveforms for hdl2
D
A
B
C 13
10
0 5ns 10ns
E
3
166
3
13
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SystemVerilog HDL - concurrency
module hdl3;timeunit 1ns; timeprecision 1ns; logic [7:0] A, B, C;
initialbegin
A = 1; B = 5;$display("%d %d %d @ %.2f", A, B, C, $realtime );#100 C = A * B;$display("%d %d %d @ %.2f", A, B, C, $realtime );
end
initial#30 A = 3;
always#15 B = B+1;
endmodule
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SystemVerilog HDL - concurrency
Output
1 5 x @ 0.003 11 33 @ 100.00
Notes
• The three procedural blocks operate concurrently.
• begin and end are optional where only one statement exists within a block.
• This example doesn’t terminate.
• $display supports formatted output.
%b %d %x %s %f
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SystemVerilog HDL - concurrency
module hdl4;timeunit 1ns; timeprecision 1ns; logic [7:0] A, B, C;
initialbegin
A = 1; B = 5;#100 C = A * B;
endinitial #30 A = 3;always #15 B = B+1;
initialbegin
$monitor("%d %d %d @ %.2f", A, B, C, $realtime );#115 $finish;
endendmodule
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SystemVerilog HDL - concurrency
Output
1 5 x @ 0.001 6 x @ 15.003 7 x @ 30.003 8 x @ 45.003 9 x @ 60.003 10 x @ 75.003 11 x @ 90.003 11 33 @ 100.003 12 33 @ 105.00
Notes
• $monitor allows us to track all variable changes.
• $finish is used to force the simulation to end.
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SystemVerilog HDL - concurrency
Waveforms for hdl3/hdl4
B
C
0 50ns 100ns
126 7 8 9 10 11
33
31
5
A 3
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SystemVerilog HDL - modelling
module hdl5;timeunit 1ns; timeprecision 1ns;logic Clear; logic [2:0] Count;
initial begin Clear = 1; #25 Clear = 0; end
always#10
if (Clear == 1) Count = 0; else Count = Count + 1;
initialbegin
$display("Clear Count @time");$monitor(" %b %b (%d) %5.1f",Clear,Count,Count,$realtime);#115 $finish;
endendmodule
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SystemVerilog HDL - modelling
Output
Clear Count @time1 xxx (x) 0.01 000 (0) 10.00 000 (0) 25.00 001 (1) 30.00 010 (2) 40.00 011 (3) 50.00 100 (4) 60.00 101 (5) 70.00 110 (6) 80.00 111 (7) 90.00 000 (0) 100.00 001 (1) 110.0
NotesHere a simple counter is modelled. The counter increments when Clear is notasserted. The three bit count rolls over from 7 to 0 since 8 is not valid.
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SystemVerilog HDL - modelling
Waveforms for hdl5
1 2 3 4 5 6 7 0 1
Clear
Count
0 50ns 100ns
0
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SystemVerilog HDL - modelling
module hdl6;timeunit 1ns; timeprecision 1ns;logic Clear, Clock; logic [2:0] Count;
initial begin Clear = 0; #17 Clear = 1; #10 Clear = 0; endalways begin Clock = 1; #5 Clock = 0; #5 Clock = 1; end
always@(posedge Clock)
if (Clear == 1) Count = 0; else Count = Count + 1;
initialbegin
$display("Clear Count @time");$monitor(" %b %b (%d) %5.1f",Clear,Count,Count,$realtime);#115 $finish;
endendmodule
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SystemVerilog HDL - modelling
Output
Clear Count @time0 xxx (x) 0.01 xxx (x) 17.01 000 (0) 20.00 000 (0) 27.00 001 (1) 30.0
...0 111 (7) 90.00 000 (0) 100.00 001 (1) 110.0
NotesWe can wait on a signal rather than waiting for a time.
• @(signal)
• @(negedge signal)
• @(signal1, signal2)
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SystemVerilog HDL - modelling
Waveforms for hdl6
1 2 3 4 5 6 7 0 10
Clear
Clock
Count
0 50ns 100ns
Since Clear is synchronous, Count goes to zero on the rising edge of Clock onceClear is high.
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SystemVerilog HDL - modelling
module hdl7;timeunit 1ns; timeprecision 1ns;logic nReset, Clock; logic [2:0] Count;
initial begin nReset = 1; #17 nReset = 0; #10 nReset = 1; endalways begin Clock = 1; #5 Clock = 0; #5 Clock = 1; end
always @(posedge Clock, negedge nReset)if (nReset == 0) Count = 0; else Count = Count + 1;
initialbegin
$display("nReset Count @time");$monitor(" %b %b (%d) %5.1f",nReset,Count,Count,$realtime);#115 $finish;
endendmodule
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SystemVerilog HDL - modelling
Output
nReset Count @time1 xxx (x) 0.00 000 (0) 17.01 000 (0) 27.01 001 (1) 30.01 010 (2) 40.01 011 (3) 50.01 100 (4) 60.01 101 (5) 70.01 110 (6) 80.01 111 (7) 90.01 000 (0) 100.01 001 (1) 110.0
Notes
• includes active low asynchronous nReset
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SystemVerilog HDL - modelling
Waveforms for hdl7
1 2 3 4 5 6 7 0 10
nReset
Clock
Count
0 50ns 100ns
Since nReset is asynchronous, Count goes to zero on the falling edge of nReset
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SystemVerilog HDL - hierarchy
module hdl8_stim;timeunit 1ns; timeprecision 1ns;logic nReset, Clock;wire [2:0] Count;
initial begin nReset = 1; #17 nReset = 0; #10 nReset = 1; endalways begin Clock = 1; #5 Clock = 0; #5 Clock = 1; end
hdl8 unit1(.Count, .Clock, .notReset(nReset));
initialbegin
$display("nReset Count @time");$monitor(" %b %b (%d) %5.1f",nReset,Count,Count,$realtime);#115ns $finish;
endendmodule
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SystemVerilog HDL - hierarchy
Notes
• hdl8 stim will be the top level module in the hierarchy.
• hdl8 stim contains the stimulus and monitoring information.
• This module calls an instance of the counter module, hdl8. The name of thisinstance is unit1.
• nReset and Clock are generated here and passed to the counter module.They are declared to be of type var (logic ≡ var logic).
• Count is generated elsewhere (in the counter module) and is declared to be oftype wire (wire ≡ wire logic).
• Port connection is by name, indicated by this format: .<signal name>
• Since the names of the two reset signals do not match, we use a different formatfor the connection: .<sub module port name>(<our name>)
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SystemVerilog HDL - hierarchy
module hdl8(output logic [2:0] Count,input Clock,input notReset
);
timeunit 1ns; timeprecision 1ns;
always_ff @(posedge Clock, negedge notReset)if (notReset == 0)
Count = 0;else
Count = Count + 1;
endmodule
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SystemVerilog HDL - hierarchy
module hdl8(output logic [2:0] Count,input Clock,input notReset
);
timeunit 1ns; timeprecision 1ns;
always_ff @(posedge Clock, negedge notReset)if (notReset == 0)
Count <= 0;else
Count <= Count + 1;
endmodule
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SystemVerilog HDL - hierarchy
Notes
• hdl8 contains the model of the counter.
• hdl8 is synthesizable.
• notReset and Clock are generated elsewhere and are declared to be of typewire (input ≡ input wire logic).
• Count is generated here and passed to the parent module module. It is de-clared to be of type variable (output logic ≡ output var logic).
• always ff simulates the same as always but hints to the synthesis programthat synchronous sequential logic is intended.
• <= indicates a non-blocking assignment and is used by default within always ffblocks.
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SystemVerilog HDL - hierarchy
Waveforms for hdl8
1 2 3 4 5 6 7 0 10
1 2 3 4 5 6 7 0 10
100ns50ns0
unit1.Count
unit1.Clock
unit1.notReset
Count
Clock
nReset
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SystemVerilog HDL - hierarchy
module hdl9_stim;timeunit 1ns; timeprecision 1ns;logic nReset, Clock;wire Max; wire [2:0] Count;
initial begin nReset = 1; #17 nReset = 0; #10 nReset = 1; endalways begin Clock = 1; #5 Clock = 0; #5 Clock = 1; end
hdl9 unit1(Max, Count, Clock, nReset);
initialbegin
$display(" Count Max @time");$monitor("%b (%d) %b %5.1f",Count,Count,Max,$realtime);#115 $finish;
endendmodule
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SystemVerilog HDL - hierarchy
module hdl9(output logic Max,output logic [2:0] Count,input Clock,input notReset
);timeunit 1ns; timeprecision 1ns;
assign Max = Count[2] && Count[1] && Count[0];
always_ff @(posedge Clock, negedge notReset)if (notReset == 0)
Count <= 0;else
Count <= Count + 1;
endmodule
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SystemVerilog HDL - hierarchy
Output
Count Max @timexxx (x) x 0.0000 (0) 0 17.0001 (1) 0 30.0
....110 (6) 0 80.0111 (7) 1 90.0000 (0) 0 100.0001 (1) 0 110.0
Notes
• Continuous Assignment
The assign statement offers one way to model combinational logic.
• Port connection by position in ordered list
An alternative to connection by name – should be used with care.
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SystemVerilog HDL - hierarchy
Waveforms for hdl9
1 2 3 4 5 6 7 0 10
1 2 3 4 5 6 7 0 10
unit1.Max
unit1.Count
unit1.Clock
unit1.notReset
Max
Count
Clock
nReset
0 50ns 100ns
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