SystemC Users Forum - Japanon SystemC for VHDL and Verilog Designer with additional two-day...
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SystemC Users Forum - Japan February 1, 2001
Transcript of SystemC Users Forum - Japanon SystemC for VHDL and Verilog Designer with additional two-day...
SystemC Users Forum -Japan
February 1, 2001
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Agenda
Why SystemC ?Organizational UpdateThe Growing SystemC Marketplace SystemC v2.0 Roadmap v2.0 Capabilities and Benefitsv1.2beta Capabilities and Benefits
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SystemC Mission - Model Concept to RTL
Architecture
Co-Design
Implement
Co-Verify
Verify
Implement
Verify
SW Code HW Design
Implement
Verify
DesignReuse
IPCodeReuse
IP
Software
Product
Hardware
Environment
Specify
Conceptto
RTL & Software
RTLto
GDSIIReusable
IPIntegration
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SystemC - Enabling System Level Design
HWImplementation
Verification &Analysis
SWImplementation
C-Compiler
Syst
em
SystemLevel IP
Soft IPRTL
Hard IP
Phys
ical
Why SystemC ?
Stan KrolikoskiVice PresidentSystem Level Design GroupCadence Design Systems
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The Evolution of SystemC
Synthesis / Place & Route etc.
Advanced & Functional Verification
Links to Verification and Implementation
Algorithm Design
System ArchitectureDesign SpaceExploration
Full System Specification
1.0
2.0
2.x/3.y
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We’ve been here before
During the 1960/1970’s, many SW languages were created– Lack of compatibility between SW modules became a real issue
Even single languages had multiple dialects– Eventually C/C++ became the de facto standard
Others still being used, e.g., Ada, Lisp,...
During the 1970/1980’s, multiple HDLs started to be developed– Strong actions by the US department of defense helped create VHDL– Market dominance helped Cadence establish Verilog– Not many alternative HDLs are being used today
But we still ended up with two!
Let’s not repeat the past!
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We are at a fork in the road
System level design is becoming necessary– The size, speed and complexity of the latest designs require a
higher level of abstraction than RTLGood system languages will be crucial in enabling system-level design – Even in systems that are GUI based
Therefore, we need to develop system languages, but….Can we afford to have many system level languages?
NO!!!!!!
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There must be AA language for system design
We cannot get into the mess we were with SW languagesWe cannot even afford to have two dominant languages as in the HDL worldWe need a single language that can serve as– A “backbone” for system-level design tools– A common format for system level IP exchange and tool
interoperabilityOther languages may still be used for specialized tasks, but we need a common system-level language
That Language is SystemC
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We need everyone’s help!
SystemC must meet the needs of both users and vendorsThis requires a strong cooperation between companies– Even between strong rivals-- we are all in this together
The SystemC group already has a good mixture of vendors and users from around the worldBut we need more members, and we need more user participation in evolving SystemC
If SystemC is OUR language, then WE must develop it
Organizational Update
Pete HardeeDirector, Product MarketingCoWare
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Open SystemC Initiative Delivers !
Fast Innovation – SystemC v2.0 Specification
major step in system level modelingcross industry contributions - Cadence, CoWare, Fujitsu, Motorola, STM, Synopsys
– SystemC v1.2 beta SoftwareCommon, Open Industry Solution – OSCI incorporated NOW as non profit organization– OSI-compliant Open Source license
Broad industry adoption and success !
Open SystemC Initiative Steering Group
ARMCadence*CoWareEricssonFujitsuInfineonLucent
Motorola*NEC*STMicroelectronicsSonySynopsysTexas Instruments
Motorola*NEC*STMicroelectronicsSonySynopsysTexas Instruments
*elected 6/00
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Strong User Adoption and Success
Over 7,000 Licensees at over 500 companies/institutionsOver 12,000 successful downloads of SystemC source codeSystemC successes presented at numerous venues– DATE, FDL, HDL Con, IP/SoC, ASP/DAC, ESP, …– CSELT, Infineon, Siemens, STM, ...
Commercial projects featured on web based SystemC Forum at www.systemc.org
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A year of Strong SystemC Adoption
SystemC v1.0/1.1betaReleased
02000
4000
60008000
10000
12000
14000
Use
rs/D
ownl
oads
Sep-
99
Nov
-99
Jan-
00
Mar
-00
May
-00
Jul-0
0
Sep-
00
Nov
-00
Downloads
Licensed Users
SystemC Solutions
Kevin KranenDirector, Strategic ProgramsSynopsys, Inc.
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SystemC Value Chain is Building
Solutions include EDA, IP and ServicesOver 20 Companies / over 25 Products announced or released– EDA tools - 20 – Training - 6– IP - 2
See http://www.systemc.org/products.html for exhaustive list
SystemC Product Briefs
All product claims contained within are provided by the respective supplying company.
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BlueWaveBlue Pacific Computing
Blue Pacific’s BlueWave is a simulation GUI, including waveform viewer that can be used to view and analyze VCD results on Linux, Unix, Windows, including SystemC outputs. BlueWaveStudent version is free.Enables visualization and analysis of SystemC modelingContact Blue Pacific at: [email protected] of find us on the web at www.bluepc.com, phone: (858) 484-7500
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SystemC ClassesBlue Pacific Computing
Three-day SystemC On-Site Classes focussing on SystemC for VHDL and Verilog Designer with additional two-day foundational course on C and C++Teaches SystemC modeling and simulation to people with traditional Verilog or VHDL background.Contact Blue Pacific at [email protected] or find us on the web at www.bluepc.com, phone: (858) 484-7500
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SYSTEMSIM™
Multilingual simulator, supporting Verilog, Superlog, C, C++ and SystemC, without interfaces or co-simulation
Allows SystemC models to be called from alternative language constructs to provide a fast, usable method to solve alternative language IP and legacy code issues Contact Co-Design Automation, Inc, www.co-design.com, [email protected]
Superlog SystemCSYSTEMSIM
C / C++ HDL
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Vip Library: a wide set of customizable and flexible system level Intellectual Property Soft Cores to answer Information and Communication Technologies Product requirements
Availability of SystemC Core description to stress architectural exploration before HW/SW partitioning is performed.
Contact CSELT S.p.A, [email protected],Visit Booth 4653 at DAC 2000.
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CoWare N2CTM
CoWare N2C - Napkin to Chip in Half the Time. Full SystemC Co-Design Environment featuring:– Specification– Partitioning– Co-implementation– Co-verification
Read in and write out SystemC from CoWare N2C– CoWareC or SystemC in– CoWareC, SystemC, VHDL and Verilog out
Visit DAC booth #4745 or www.CoWare.com
Analysis at every stage}
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CoWare N2C System-Level Design Flow
Behavioral C Behavioral C System DesignSystem Designand Partitioningand Partitioning
CycleCycle--Accurate C Accurate C HWHW--SW CoSW Co--designdesignand Multiand Multi--levellevelCoCo--verificationverification
SystemCSystemC ExecutableExecutableImplementable Implementable SpecSpec
Refine Refine
Testbench
"Traditional""Traditional"HWHW--SW CoSW Co--verificationverification
RTL RTL ImplementationImplementation
SW O
ptimization
Interface Interface
SynthesisSynthesis
GenerateH
DL
RTLRTLSystemCSystemC
HW
Design
IP and Performance Models
Function
Algorithms, Controland Testbench ANSI C/C++, SystemC
or CoWare C
Architecture
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Databahn Memory Subsystem Generator
Databahn, an on-line tool, generatessynthesizable memory controller cores and automatically produces all C-level verification support for the associated memory subsystemProduces SystemC models of these coresContact: Steven Shrader (208) 376-6030, [email protected] or visit our website at www.denalisoft.com
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Proven SystemC-based architectural explorationInteractive C-to-HDL design flowOptimized implementationHigh level design re-useASIC and FPGASilicon proven for :– ultra-low power applications– telecom base-band processing– consumer speech processing
Contact [email protected]
EDS2001
Booth DT511
EDS2001EDS2001
Booth DT511Booth DT511
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Automatic SystemC-to-HDLWhat You Write Is What You GetProduces hierarchical Mealy MachineVHDL and Verilog outputASIC and FPGAAutomatic test-bench generationContact [email protected]://www.frontierd.com
Compute process(combinatorial)
Clk Reset Enable
Inputs Outputs
Compute
Update
Update process(sequential)
EDS2001
Booth DT511
EDS2001EDS2001
Booth DT511Booth DT511
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VStation Co-Modeling
Ultra high-performance Co-Modeling between behavioral models running on a workstation and implementation models running on IKOS VStation.– Based on the world’s first high-performance transaction
interface– System verification productivity at emulation speed
Enables SystemC models to be used in conjunction with emulation– Bring the value of high performance emulation earlier in the
verification process– Utilizing your SystemC environment throughout the design
cyclehttp://www.ikos.com
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Closing The VerificationProductivity Gap
4 seconds4 seconds
1.25 years1.25 years
1.5 months1.5 months
OvernightOvernight
Run 4 seconds Run 4 seconds realreal--time time verification inverification in……5 minutes5 minutes
RealRealHardwareHardware
GateGate--LevelLevel
RTL HDLRTL HDL
MixedMixed--LevelLevelCC
UntimedUntimedCC
Des
ign
Flow
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Visual SLD
Systems-Level Design environment for defining and verifying system architecture, Hardware/Software
co-verification, Register Definition. Includes Embedded Systems support, Complete code-coverage debug and analysis. Built upon the strongest graphic entry tool in the industry, Visual HDL. Truth-table, flowchart, Finite-State Machine, Block DiagramLanguage design via SystemC, C/C++, Verilog, VHDL
come see Innoveda at booth (3101), www.innoveda.com, or (800) 223-8439
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Visual SLD
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TestBencher Pro
Graphical environment for generating bus-functional modelsTestBencher generates SystemC test benches from language independent timing diagrams.– Generates all the class code for each diagram, including port
mappings and sensitivity listsVisit www.syncad.com and download an evaluation versionContact SynaptiCAD at [email protected] or 800-804-7073
TestBencher ProGenerates SystemC Code
CoCentricTM Tools
a.out+
FunctionalityArchitecture
CoCentricTM
System Studio
SystemCCoCentricTM
SystemC Compiler
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HW/SW Co-Design propelled by SystemC
CoCentricTM
System Studio
integrated system level tool for… performance analysis of
system architecture and function… concurrent design of HW and SW
at multiple levels of abstraction
Contact [email protected] or visit www.synopsys.com for more information
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CoCentricTM
SystemC CompilerComplete synthesis from SystemC to hardware
Design CompilerPhysical CompilerFPGA Compiler II
CoCentricSystemC Compiler
Behavioralor RTL
C/SystemC synthesis… refine & synthesize from C/C++ executable spec… path to FPGAs for system designers… powerful constructs for RTL designers
Complete… behavioral & RTL… SoCs, ASICs, FPGAs
Contact [email protected] or visit www.synopsys.com for more information
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SystemC-HDL Co-Simulation
InterfaceLibrary HDLHDL
VCS, Scirocco, MTI-VHDL
Model import & export
Contact [email protected] or visitwww.synopsys.com for more information
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SystemC-VERA I/F
High performance, direct kernel interface for integrating VERA with SystemCUses the powerful, verification related features in VERA to verify system designs described in SystemCContact [email protected] or visit the website at www.synopsys.com for more information
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TT VTOC
Converts from Synthesisable Verilog to C/C++– Compiles multiple Verilog modules totalling up to about
100K gates into one large, highly-efficient, cycle-based C or C++ implementation.
– Provides a mechanism for efficient linking of separately compiled modules.
– Main applications are fast simulation and generation of a system-level emulator for the software team.
SystemC is one of the output formatsWeb site is www.tenisontech.com
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SuperC™
A very fast SystemC Simulator that writes a highly compressed data format. This wave form data is compressed by 15-50X and can be displayed almost instantly by the Undertow waveform viewer regardless of file size.Veritools provides the SuperC™ C++ class compile library for the Veritools SuperC™simulatorContact Veritools at [email protected] or Robert Schopmeyer at [email protected]
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Undertow Suite
A waveform viewer and Source Code debugging program for the SystemC/SuperC™ Simulator that reads the the highly compressed data format that is written directly by the SuperC™ simulator. This waveform data can be displayed almost instantly by the Undertow waveform viewer regardless of file size while providing linkage and synchronization with the SystemC source code. Undertow uses the highly compressed “Fast file” format from SuperC™ while providing Source Code debug facilities for SystemC Source Code.Contact Veritools at [email protected], or Robert
Schopmeyer at [email protected]
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Undertow
A very powerful waveform viewer for the SystemC/SuperC™ Simulator. This wave form data can be displayed almost instantly by the Undertow waveform viewer regardless of file data size
Undertow uses the SystemC native waveform data or the highly compressed “Fast file” format from SuperC™
Contact Veritools, Inc. at [email protected] or Robert Schopmeyer at [email protected]
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From Virtual Prototyping to SystemC
Evaluate, experience, and design embedded IP platforms from your browser!
Explore pre-configured embedded platforms, create high-level system models, and generate SystemC to link your designs to implementation.
For more information contact [email protected] or visit our web site at www.virtio.com.
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Training: Modeling with SystemC.– Introduction to modeling with C/C++ and the SystemC
class libraries. Learn how to write, compile, execute, and debug system and hardware descriptions with SystemC.
SystemC for High Level Synthesis(HLS)– Learn HLS concepts, SystemC coding style required for
HLS, testbenches and RTL co-simulation.
For more information or for class schedules email to [email protected], or visit website at www.whdl.com
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Language Rule Checker
Complete language rule checkerPerforms netlist, general coding style and synthesis coding style checks on your SystemC code. Contact Willamette HDL, [email protected]
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Open SystemC Initiative Delivers !
Fast Innovation – cross industry contribution
Common, Open Industry Solution – OSCI incorporating NOW as non profit organization– OSI-compliant Open Source license
Broad industry adoption and success !
SystemC v2.0 Roadmap
Takashi Hasegawa, Director of Strategic Software Systems, World Wide System LSI Technologies - Fujitsu
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SystemC v2.0 Innovation
SystemC v1.0– RTL & behavioral level modeling (HDL & beyond)– integrated with higher level C/C++ functional modeling
SystemC v2.0– provides higher levels of abstraction– enables modeling of HW / SW interaction– flexible communication channel refinement
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v2.0Production
• User Validation
v2.0 Detailed Spec
SystemCv2.0 LRM
v2.0beta
SystemC Evolution
v1.2beta
• v2.0 model of time • Dynamic sensitivity• Code fixes
New SystemCFoundation for Systems• Channels & Events• Comms Refinement• Backward compatibility
Feb2001
Q22001
Q32001
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SystemC Release Roadmap
1.0 - Hardware Design Flow– RTL and Behavioral Hardware Modeling
1.x - Master-Slave Communication Library– RPC-based untimed & timed functional modeling down to
RTL for bus protocol based systems
2.0 - System Design Flow– General purpose communication and synchronization– Communication Refinement– Multiple, customizable models of computation
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SystemC Release Roadmap (cont)
2.X - Extensions to System Design Flow– Dynamic thread creation, fork / join– Interrupt / abort for behavioral hierarchy– Performance modeling support– Timing specification and constraints
3.X Software Design Flow– Abstract RTOS modeling– Scheduler modeling
4.X - Analog / Mixed Signal Systems Modeling
SystemC 2.0 Specificationand Benefits
Thorsten GrötkerSynopsys, Inc.
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Motivation
SystemC 1.0HW modeling (RTL and behavioral)
SystemC 2.0extend scope to System-Level Modeling
System-Level Modeling– functional models– transaction-level platform models– high-level architecture models
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MoC: Model of Time
SystemC 1.0Relative floating-point model of time (double)
SystemC 2.0Absolute (64 bit) unsigned integer model of time
Why?– Avoid finite precision effects, e.g. underflow– Use absolute model of time: define time units
(IP exchange)
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MoC: Rules for Process Activation
SystemC 1.0– Static sensitivity
Processes are made sensitive to a fixed set of signals during elaboration
SystemC 2.0– Static sensitivity– Dynamic sensitivity
The sensitivity (activiation condition) of a process can be altered during simulation (after elaboration)Main features: events and extended wait() method
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Events
Events are objects (sc_event)Events can be notified (sc_event::notify())Channels use events (Signals use events to indicate value changes.)Modules can use eventsProcesses can wait for events(Dynamic sensitivity)
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Waitingwait(); // as in SystemC 1.0
wait(event); // wait for event
wait(e1 | e2 | e3); // wait for first event
wait(e1 & e2 & e3); // wait for all events
wait(200, SC_NS); // wait for 200ns
// wait with timeout
wait(200, SC_NS, e1 | e2);
wait(200, SC_NS, e1 & e2);
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MoC: Communication
SystemC 1.0– Fixed set of communication channels (sc_signal, …)
and ports (sc_in, sc_out, …).SystemC 2.0– user-defined
interfaceschannelsports
– richer set of predefined channels(HW signals, FIFO, semaphore, mutex, …)
Define your own bus, message queue, … etc.
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Interfaces and Channels
An interface is a set of methods implemented by a channel.
A channel can implement multiple interfaces.
struct write_if : public sc_interface{
virtual void write(char) = 0;virtual void reset() = 0;
};
struct read_if : public sc_interface{
virtual void read(char &) = 0;virtual int num_available() = 0;
};
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Ports
Ports …– connect modules and channels– specify the required interface (e.g. sc_port<IF>)– give modules (processes) access to interface methods
sc_port<write_if> p;
void some_process() {...p->reset();p->write(‘X’);...
}
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Primitive and Hierarchical Channels
Primitive channels– are atomic entities– have no visible internal structure– can use request-update scheme (HW signals)
Hierarchical channels– are modules that implement interfaces– can have ports– can contain processes, modules, and channels
Both implement interfaces
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Architecture of SystemC 2.0
Methodology-specific and User-Defined Channels
SystemC Scheduler
Events, Dynamic Sensitivity
Channels, Interfaces, Ports
Elementary channels(signals, FIFOs, …)
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Model of Computation
Very powerful and flexibleSupports well known MoCs such as– discrete-event models
RTL / behavioral HW modelsnetwork modelingtransaction-level SoC platform modeling
– Kahn process networksstatic multi-rate data flowdynamic data flow
– Communicating Sequential Processes
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Benefits of SystemC v2.0
Enables, fast smooth system design– Communication can modeled and refined independent of
functionSupports virtually all system modeling needs– Flexible semantic foundation additions support most
models of computation within one environment– Leverages all existing v1.0 and v1.1beta capabilities
Broadly applicable, “best of breed” solution– Designed by 12 experts from six different EDA and System
IC companies– Tuned for both EDA tool and IP use
SystemC v1.2 beta Capabilities and Benefits
Dundar
Panel Session
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Panelist names and titles
