System IC Design: Timing Issues and DFT

Hung-Chih Chiang

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Outline

SoC Timing IssuesTiming terminologiesSynchronous vs. asynchronous designInterfaces and timing closureClocking issuesReset

Design for Testability (DFT)SoC Test PlanScan, ATPG, memory BISTDFT design rules

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SoC Clock Issues

Clock/OSC

Microprocessor

DataCache

Instr.Cache

Memory High Speed I/O Ctrl

MemoryCtrl HS IP Bus

Bridge

LS I/OUARTGPIOIntrCtrlTimer

High Speed Bus

Peripheral Bus

Clock/OSC

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SoC Clock Domains

Clock GeneratorOSC

CLK2

CLK3

CLK4

CLK5

CLK6

CLK1

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Timing Terminologies

Setup time, hold time, release time, width, period and skew

Cell delay and wire delay

Best case, typical case, worst case and pseudo worst case

Loading and driving capacity

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Basic Cell Timings

IAIB O

D Q

CK

RN

SN

QNInterconnection Delay

Cell Delay

Cell Delay

Recovery Width Skew

CK1

CK2

SetupHold

D

CK CK

RN

Width

Period

CK

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Best, Typical, Worst & Pseudo Worst CasesBest Casehighest operation voltage, lowest temperature, fast processeg. 0.25µm@2.75V, 0°C, fast processTypical Casestandard operation voltage, room temperature, typical process

eg. 0.25µm@2.5V, 25°C, typical processPseudo Worst Caselowest operation voltage, highest temperature, typical process

eg. 0.25µm@2.25V, 125°C, typical processWorst Caselowest operation voltage, highest temperature, slow process

eg. 0.25µm@2.25V, 125°C, slow process

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Loading and Cell Delay

Linear Delay Modelt typical = t intrinsic + (K load * C load )

(Databook)

Non-Linear Delay Model (Table Lookup) t typical = F(trf , C load )

(EDA Timing Model)

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Cell Datasheet: NAND2 (1)

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Cell Datasheet: NAND2 (2)

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Cell Datasheet: DFF (1)

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Cell Datasheet: DFF (2)

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Cell Datasheet: DFF (3)

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Clock-Based Timing (single clock source)

d1 d2

D Q

CK

D Q

CK

combination logic

d1 + d2max < TCK – tsetupd1 + d2min> thold

D Q

CK

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Outline

SoC Timing IssuesTiming terminologiesSynchronous vs. asynchronous designInterfaces and timing closureClocking issuesReset

Design for Testability (DFT)SoC Test PlanScan, ATPG, memory BISTDFT design rules

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Synchronous vs. Asynchronous Design

Synchronous DesignFlip-flop based (clock based)Easy timing handlingDFT compliant

AsynchronousLatch based Timing ambiguity cause problemsNot DFT compliant

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Flip-Flop (Clock) Based Design

D Q

CK

D Q

CKcombination logic

Poor HDL coding of combination logics can produce unintentional latchesAvoid using flip-flops with enable inputUse positive clock edge trigger for flip-flops for module RTL coding if flip-flops in cell library is triggered at positive clock edge

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Flip-Flop Clock Edge• If negative edge triggered flip-flops are required in a design while Cell

Library contains positive edge triggered flip-flops, invert the clock phase first and then write RTL codes using positive edge triggered flip-flops to avoid inverters being inserted at clock inputs of each modules during logic synthesis.

D Q

CK

D Q

CK

D Q

CK

D Q

CK

D Q

CK

D Q

CK

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Problem of Latch: timing ambiguity

D Q

E

D Q

E

CK

Din

outputoutput

CK

setup

setup

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Problem of Latch: possible D/E race

D Q

E

CK

D

E

D QCK

D QCK

CK

D

Q

E

Q

• Need to ensure there is enough hold time for D after the falling edge of E

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Problem of Latch: DFT

scan path

normal operation path

D Q

E

D Q

CK

D Q

CK

D Q

CK

scan_enable

Q is generally not controllable by D due to E=> A latch can not be part of a scan chain

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Outline

SoC Timing IssuesTiming terminologiesSynchronous vs. asynchronous designInterfaces and timing closureClocking issuesReset

Design for Testability (DFT)SoC Test PlanScan, ATPG, memory BISTDFT design rules

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Interfaces and Timing ClosureA proper design of block interfaces makes timing closure a local problem.

A major timing issue in deep submicron technology is the wire delay due to wire load capacitance and RC delay can be much larger than intrinsic cell delays.

Timing driven APR helps deal with this problem by taking into account the wire load model.

Physical synthesis takes a further stride in achieving timing closure by combining synthesis and timing driven placement.

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Macro Interfaces

Macro AMacro A Macro B

Both inputs and outputs should be registered.This gives a full clock cycle to propagate the outputs of one macro to inputs of another.

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Sub-block Interfaces

Macro ASubblock A Subblock B

Any block that is synthesized as a unit should have its own outputs registered.Any block that is floorplanned as a unit should have its own inputs and outputs registered.

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Example: interface specification

Valid

3nsCK3ns

DT Don’t care Don’t care

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Example: registered vs. unregistered inputs

d1 + tsetup < 3ns ?

Combination D Q

CK

d2 + tsetup < 3ns

D Q

CK

Combination D Q

CK

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Outline

SoC Timing IssuesTiming terminologiesSynchronous vs. asynchronous designInterfaces and timing closureClocking issuesReset

Design for Testability (DFT)SoC Test PlanScan, ATPG, memory BISTDFT design rules

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Clocking Issues

Clock skew and clock tree

Divided clocks

Asynchronous clock interface

Clock gating

Synchronize Hard IP

Other considerations

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Clock Skew

D Q

CK

D Q

CK

CK

Din

Combination

FF0/CK FF1/CK

SkewFF0/CK

FF1/CK

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Clock Skew May Cause Errors

FF0/CK

FF1/CK

Din Din

D0 Q0

CK

D1 Q1

CK

CK

Din

FF0/CK FF1/CK

FF0/CK

Q0

Q1

FF1/CK

Q0

Q1

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Clock Tree

Insert clock tree during APRClock tree can significantly increase power consumption

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Clock Tree Example

∆ + Skew

Match∆

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Clock Tree Example

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Divided Clocks

ClockGenerator

Module A

Module B

Module C

CK0 (f Hz)

Ck2 (f/4 Hz)

CK1 (f/2 Hz) ∆1+skew1

∆0+skew0

∆2+skew2

t0 t1 t2

CK0

CK1

CK2

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An Alternative Design Approach for a Divided Clock Domain

ClockGenerator

Module A

Module B

Module C

Ck

CK

En1

En2

∆+skew

En1

En2

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Asynchronous Clock Interface

Ck1

XD Q

CKCk2

Block 1

Combination

Da QaCK1a

Db QbCK1b

da

db

Y

Z

Dangerous design!!!Random logic errors may occur due to the delay time difference between da and db.

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Asynchronous Errors CK2

CK1/CLK2

X

Y (Da)

Z (Db)

E.g. 01

10

X=0 X=101

11

X=0/1 X=1/0

00

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Clock Synchronization

Synchronization

Ck1

DinD Q

CKCk2

D’in

Block A

Not all asynchronous inputs need to be synchronized!A single flip-flop may not be good enough for clock synchronization.

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ASIC Flip-Flop

CK

CK

CK

CK

CKN

CKN

CKN

CKN

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Metastability

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Standard Asynchronous Interface

D Q

CK

D Q

CKCk1

DinD Q

CKCk2

Block A

Two staged flip-flop to reduce the probability of metastability

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Dual Flip-Flop Synchronization

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Peak Power Reduction

ClockGenerator

A

B

C

Ck

Sync. I/F

Sync. I/F

Sync. I/F

ClockGenerator

A

B

C

Ckb

Async. I/F

Async. I/F

Async. I/F

Cka

Ckc

CKa

CKb

CKc

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Clock Gating For Low Power Design

ClockGenerator

Module A

Module B

Module C

Clock

Enable

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Clock Delays For Hard Blocks

ClockGenerator

∆1+skew1

∆2+skew2

Take into account insertion delays of hard macros

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Bypass PLL & Clock Gating For Debugging

ClockPLL

Test_en

Clock

Gate_enor Test_en

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Clock Planning GuidelinesThe system clock generation and control logic should be separate from all function blocks of the systemDocument clock domain information- frequencies, PLL- interface timing (input and output)- skew requirement among clocksUse the standard synchronization interface for asynchronous inputs

Compensate insertion delays of hard macrosBypass clock gating and PLL in test mode

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Outline

SoC Timing IssuesTiming terminologiesSynchronous vs. asynchronous designInterfaces and timing closureClocking issuesReset

Design for Testability (DFT)SoC Test PlanScan, ATPG, memory BISTDFT design rules

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Chip Reset Issues

Synchronous or Asynchronous ?

External or Internal Power On Reset?

Voltage Detector for Power Down Reset ?

Hard Reset and Soft Reset ?

Each Module Individually Resettable for Debugging Purposes ?

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Synchronous Reset

D Q

CK QN

D Q

CK QN

D Q

CK QNReset

Easy to synthesize since reset is treated as a logic signalReset slightly affect data timingNeed at least one active clock edge for reset to take place. This could become a problem at power on

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Asynchronous Reset

D Q

CK

RN

QN

D Q

CK

SN

QN

D Q

CK

RN

QN

No clock required during reset periodReset does not affect data timingLike clock, a reset tree is usually required during APR

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Avoid logical signal reset

D Q

CK

RN

QN

D Q

CK

RN

QN

Avoid using a logic signal as a reset signal

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Reset Guideline

Asynchronous reset is preferred.

Reset must be synchronously de-asserted so that all state machine flip-flops starts at the same active clock edge.

All flip-flops/latches should be reset to a pre-defined state (“0” or “1”) to avoid ambiguity voltage output of sequential elements.

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Outline

SoC Timing IssuesTiming terminologiesSynchronous vs. asynchronous designInterfaces and timing closureClocking issuesReset

Design for Testability (DFT)SoC Test PlanScan, ATPG, memory BISTDFT design rules

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Design For TestabilityIC testing vs. verification

- manufacturing defect vs. functional defectImportance of IC testing

- cost of RMATest phases:

- wafer test (Chip Probing), - final test (packaged IC testing) Test principle:

- different kinds of blocks require different test strategies

- use a test controller at top level to sequence the test of different function blocks

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An Example of SoC Test Plan

Test Mode Register

Test Circuits

Test Mode:Processor TestRAM BISTROM Check SumSCAN/ATPGFunctional TestAnalog Macros ...

T_CK

T_M

S_I

S_O

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SCAN Chain & ATPG

D QCK

RNQN

D QCK

SNQN

Scan_en

Reset_n

combination logic

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Memory BIST

Software Memory BISTHardware Memory BIST

MemoryModule

A/D/En

Do

PatternGenerator

Compressor

A/Di/En

clock

test_crtl q

So

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DFT Guidelines - 1

Avoid internally gated clocks or derived clocks

ClockD Q

CKGated clock

D Q

CK Derived clock

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DFT Guidelines - 2

Avoid using latches Controllable

D Q

E

Uncontrollable

A latch can not be inserted into a scan chain due to the uncontrollable enable input

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DFT Guidelines - 3

Avoid using flip-flops with an enable input (synthesis)

D Q

E

CK

Enable is not controllable

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DFT Guidelines - 4

Avoid combinational feedback

Race/unstableATPG is not applicable

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DFT Guidelines - 5

Avoid uncontrollable asynchronous signals

D Q

CK

RN

QN

Uncontrollable

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DFT Guidelines - 6

Avoid feeding data path with clocks

D Q

CK

RN

QN

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DFT Guidelines - 7

Provide test control for uncontrollable signals

ClockPLL

ClockTest_en

Gate_enor Test_en

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SummariesRecommend flip-flop based design. Use Latches only when you know what you are doing.

A proper design of block interfaces makes timing closure a local problem.

Clock domains require special cares.

A global reset signal is recommended.

A proper SoC test plan is important to reduce RMA costs.

DFT rules must be followed to ensure the testability of designs.