System BusesSystem Buses

Program ConceptProgram Concept

Hardwired systems are inflexibleHardwired systems are inflexible General purpose hardware can do General purpose hardware can do

different tasks, given correct control different tasks, given correct control signalssignals

Instead of re-wiring, supply a new set Instead of re-wiring, supply a new set of control signalsof control signals

What is a program?What is a program?

A sequence of stepsA sequence of steps For each step, an arithmetic or For each step, an arithmetic or

logical operation is donelogical operation is done For each operation, a different set of For each operation, a different set of

control signals is neededcontrol signals is needed

Function of Control UnitFunction of Control Unit

For each operation a unique code is For each operation a unique code is providedprovided• e.g. ADD, MOVEe.g. ADD, MOVE

A hardware segment accepts the A hardware segment accepts the code and issues the control signalscode and issues the control signals

ComponentsComponents

The Control Unit and the Arithmetic and The Control Unit and the Arithmetic and Logic Unit constitute the Central Logic Unit constitute the Central Processing UnitProcessing Unit

Data and instructions need to get into the Data and instructions need to get into the system and results outsystem and results out• Input/outputInput/output

Temporary storage of code and results is Temporary storage of code and results is neededneeded• Main memoryMain memory

Computer Components:Computer Components:Top Level ViewTop Level View

Instruction CycleInstruction Cycle

Two steps:Two steps:• FetchFetch• ExecuteExecute

Fetch CycleFetch Cycle

Program Counter (PC) holds address of next Program Counter (PC) holds address of next instruction to fetchinstruction to fetch

Processor fetches instruction from memory Processor fetches instruction from memory location pointed to by PClocation pointed to by PC

Increment PCIncrement PC• Unless told otherwiseUnless told otherwise

Instruction loaded into Instruction Register Instruction loaded into Instruction Register (IR)(IR)

Processor interprets instruction and Processor interprets instruction and performs required actionsperforms required actions

Execute CycleExecute Cycle

Processor-memoryProcessor-memory• data transfer between CPU and main memorydata transfer between CPU and main memory

Processor I/OProcessor I/O• Data transfer between CPU and I/O moduleData transfer between CPU and I/O module

Data processingData processing• Some arithmetic or logical operation on dataSome arithmetic or logical operation on data

ControlControl• Alteration of sequence of operationsAlteration of sequence of operations• e.g. jumpe.g. jump

Combination of aboveCombination of above

Example of Program ExecutionExample of Program Execution

Instruction Cycle State DiagramInstruction Cycle State Diagram

InterruptsInterrupts

Mechanism by which other modules (e.g. I/O) may Mechanism by which other modules (e.g. I/O) may interrupt normal sequence of processinginterrupt normal sequence of processing

ProgramProgram• e.g. overflow, division by zeroe.g. overflow, division by zero

TimerTimer• Generated by internal processor timerGenerated by internal processor timer• Used in pre-emptive multi-taskingUsed in pre-emptive multi-tasking

I/OI/O• from I/O controllerfrom I/O controller

Hardware failureHardware failure• e.g. memory parity errore.g. memory parity error

Program Flow ControlProgram Flow Control

Interrupt CycleInterrupt Cycle Added to instruction cycleAdded to instruction cycle Processor checks for interruptProcessor checks for interrupt

• Indicated by an interrupt signalIndicated by an interrupt signal If no interrupt, fetch next instructionIf no interrupt, fetch next instruction If interrupt pending:If interrupt pending:

• Suspend execution of current program Suspend execution of current program • Save context into STACK (memory)Save context into STACK (memory)• Set PC to start address of interrupt handler Set PC to start address of interrupt handler

routine (interrupt Vector)routine (interrupt Vector)• Process interruptProcess interrupt• Restore context and continue interrupted Restore context and continue interrupted

programprogram

Transfer of Control via InterruptsTransfer of Control via Interrupts

Interrupt Vector

Instruction Cycle with InterruptsInstruction Cycle with Interrupts

Program Timing Short I/O WaitProgram Timing Short I/O Wait

Program Timing Long I/O WaitProgram Timing Long I/O Wait

Instruction Cycle (with Instruction Cycle (with Interrupts) - State DiagramInterrupts) - State Diagram

Multiple InterruptsMultiple Interrupts

Disable interruptsDisable interrupts• Processor will ignore further interrupts whilst Processor will ignore further interrupts whilst

processing one interruptprocessing one interrupt• Interrupts remain pending and are checked Interrupts remain pending and are checked

after first interrupt has been processedafter first interrupt has been processed• Interrupts handled in sequence as they occurInterrupts handled in sequence as they occur

Define prioritiesDefine priorities• Low priority interrupts can be interrupted by Low priority interrupts can be interrupted by

higher priority interruptshigher priority interrupts• When higher priority interrupt has been When higher priority interrupt has been

processed, processor returns to previous processed, processor returns to previous interruptinterrupt

Multiple Interrupts - SequentialMultiple Interrupts - Sequential

Multiple Interrupts – NestedMultiple Interrupts – Nested

Time Sequence of Multiple InterruptsTime Sequence of Multiple Interrupts

ConnectingConnecting A computer consists of a set of components or modules of A computer consists of a set of components or modules of

three basic types(up,mmry,I/O) that communicate with three basic types(up,mmry,I/O) that communicate with each other. each other.

Different type of connection for different type of unitDifferent type of connection for different type of unit• Memory: consists of N words of equal length. Each word Memory: consists of N words of equal length. Each word

is assigned a unique numerical address (0,1,…,N-1). A is assigned a unique numerical address (0,1,…,N-1). A word of data can be read from or written into memory. word of data can be read from or written into memory.

• Input/Output : refer to each of the interface to an Input/Output : refer to each of the interface to an external device as a port and give each a unique external device as a port and give each a unique address (e.g.,0,1,…M-1). There are external data paths address (e.g.,0,1,…M-1). There are external data paths for the input and output of data external device and I/O for the input and output of data external device and I/O module may be able to send interrupt signals.module may be able to send interrupt signals.

• Processor : reads an instructions and data, writes out Processor : reads an instructions and data, writes out data after processing, and uses control signals to control data after processing, and uses control signals to control the overall system and also receives interrupt. the overall system and also receives interrupt.

Computer ModulesComputer Modules

Memory ConnectionMemory Connection

Receives and sends dataReceives and sends data Receives addresses (of locations)Receives addresses (of locations) Receives control signals Receives control signals

• ReadRead• WriteWrite• TimingTiming

Input/Output Connection(1)Input/Output Connection(1)

Similar to memory from computer’s Similar to memory from computer’s viewpointviewpoint

OutputOutput• Receive data from computerReceive data from computer• Send data to peripheralSend data to peripheral

InputInput• Receive data from peripheralReceive data from peripheral• Send data to computerSend data to computer

Input/Output Connection(2)Input/Output Connection(2)

Receive control signals from Receive control signals from computercomputer

Send control signals to peripheralsSend control signals to peripherals• e.g. spin diske.g. spin disk

Receive addresses from computerReceive addresses from computer• e.g. port number to identify peripherale.g. port number to identify peripheral

Send interrupt signals (control)Send interrupt signals (control)

CPU ConnectionCPU Connection

Reads instruction and dataReads instruction and data Writes out data (after processing)Writes out data (after processing) Sends control signals to other unitsSends control signals to other units Receives (& acts on) interruptsReceives (& acts on) interrupts

BusesBuses

There are a number of possible There are a number of possible interconnection systemsinterconnection systems

Single and multiple BUS structures Single and multiple BUS structures are most commonare most common

e.g. Control/Address/Data bus (PC)e.g. Control/Address/Data bus (PC) e.g. Unibus (DEC-PDP)e.g. Unibus (DEC-PDP)

What is a Bus?What is a Bus?

A communication pathway A communication pathway connecting two or more devicesconnecting two or more devices

Usually broadcast Usually broadcast Often groupedOften grouped

• A number of channels in one busA number of channels in one bus• e.g. 32 bit data bus is 32 separate single e.g. 32 bit data bus is 32 separate single

bit channelsbit channels Power lines may not be shownPower lines may not be shown

Data BusData Bus

Provide a path for moving data between Provide a path for moving data between system modules.system modules.

May consists of from 32 to hundreds of May consists of from 32 to hundreds of separate lines, number of lines refer to bus separate lines, number of lines refer to bus width and determines how many bits can width and determines how many bits can be transferred at a time.be transferred at a time.

The width of the data bus is a key factor in The width of the data bus is a key factor in determine overall performance. WHY?determine overall performance. WHY?

Address busAddress bus

Identify the source or destination of Identify the source or destination of datadata

e.g. CPU needs to read an instruction e.g. CPU needs to read an instruction (data) from a given location in (data) from a given location in memorymemory

Bus width determines maximum Bus width determines maximum memory capacity of systemmemory capacity of system• e.g. 8080 has 16 bit address bus giving e.g. 8080 has 16 bit address bus giving

64k address space64k address space

Control BusControl Bus Transmit both command and timing information between Transmit both command and timing information between

system modules. Timing signal indicate the validity of data system modules. Timing signal indicate the validity of data and address information. Command signal specify operations and address information. Command signal specify operations to be performed.to be performed.

- Memory writeMemory write: data on bus to be written into the adress : data on bus to be written into the adress locationlocation

- Memory readMemory read: data from the addressed location to be placed : data from the addressed location to be placed on buson bus

- I/O writeI/O write: data on the bus to be output to the addressed I/O : data on the bus to be output to the addressed I/O portport

- I/O readI/O read: data from the addressed I/O port to be placed on : data from the addressed I/O port to be placed on the busthe bus

- Transfer ACKTransfer ACK: Indicate data has been accepted from or : Indicate data has been accepted from or placed on the busplaced on the bus

Cont..Cont..

Bus requestBus request: indicates that a module needs to : indicates that a module needs to gain control of the busgain control of the bus

Bus grantBus grant: indicates that a requesting module : indicates that a requesting module has been granted control of the bushas been granted control of the bus

Interrupt requestInterrupt request: indicates that an interrupt is : indicates that an interrupt is pendingpending

Interrupt ACKInterrupt ACK: Acknowledges that the pending : Acknowledges that the pending interrupt has been recognizedinterrupt has been recognized

ClockClock: used to synchronize operations: used to synchronize operations ResetReset: initializes all modules: initializes all modules

Bus Interconnection SchemeBus Interconnection Scheme

Physical Realization of Bus Physical Realization of Bus ArchitectureArchitecture

Single Bus ProblemsSingle Bus Problems

Lots of devices on one bus leads to:Lots of devices on one bus leads to:• Propagation delaysPropagation delays

Long data paths mean that co-ordination of Long data paths mean that co-ordination of bus use can adversely affect performancebus use can adversely affect performance

If aggregate data transfer approaches bus If aggregate data transfer approaches bus capacitycapacity

Most systems use multiple buses to Most systems use multiple buses to overcome these problemsovercome these problems

Traditional (ISA)Traditional (ISA)(with cache)(with cache)

High Performance BusHigh Performance Bus

Bus TypesBus Types

DedicatedDedicated• Separate data & address linesSeparate data & address lines

MultiplexedMultiplexed• Shared linesShared lines• Address valid or data valid control lineAddress valid or data valid control line• Advantage - fewer linesAdvantage - fewer lines• DisadvantagesDisadvantages

More complex controlMore complex control Ultimate performanceUltimate performance

Bus ArbitrationBus Arbitration

More than one module controlling the More than one module controlling the busbus

e.g. CPU and DMA controllere.g. CPU and DMA controller Only one module may control bus at Only one module may control bus at

one timeone time Arbitration may be centralised or Arbitration may be centralised or

distributeddistributed

Centralised or Distributed Centralised or Distributed ArbitrationArbitration

CentralisedCentralised• Single hardware device controlling bus Single hardware device controlling bus

accessaccess Bus ControllerBus Controller ArbiterArbiter

• May be part of CPU or separateMay be part of CPU or separate DistributedDistributed

• Each module may claim the busEach module may claim the bus• Control logic on all modulesControl logic on all modules

TimingTiming

Co-ordination of events on busCo-ordination of events on bus SynchronousSynchronous

• Events determined by clock signalsEvents determined by clock signals• Control Bus includes clock lineControl Bus includes clock line• A single 1-0 is a bus cycleA single 1-0 is a bus cycle• All devices can read clock lineAll devices can read clock line• Usually sync on leading edgeUsually sync on leading edge• Usually a single cycle for an eventUsually a single cycle for an event

Synchronous Timing DiagramSynchronous Timing Diagram

Asynchronous Timing – Read Asynchronous Timing – Read DiagramDiagram

Asynchronous Timing – Write Asynchronous Timing – Write DiagramDiagram

PCI BusPCI Bus

Peripheral Component Peripheral Component Interconnection.Interconnection.

Develop in 1990 for Pentium-based Develop in 1990 for Pentium-based system and released all patents to system and released all patents to the public domain.the public domain.

PCI may be configured as a 32 or 64 PCI may be configured as a 32 or 64 bitbit

49 mandatory signal lines.49 mandatory signal lines.

Example of PCI configurationsExample of PCI configurationsTypical desktop systemTypical desktop system

Exmple: Typical server systemExmple: Typical server system

PCI Bus Lines (required)PCI Bus Lines (required) Systems linesSystems lines : include the clock and reset pins : include the clock and reset pins

Address & DataAddress & Data : include 32 lines that are time multiplexed for address : include 32 lines that are time multiplexed for address and data. The other lines in this group are used to interpret and validate and data. The other lines in this group are used to interpret and validate the signal lines that carry the address and data.the signal lines that carry the address and data.

Interface ControlInterface Control : control the timing of transactions and provide : control the timing of transactions and provide coordination among initiators and targetscoordination among initiators and targets

ArbitrationArbitration : these are not shared lines and each PCI master has its : these are not shared lines and each PCI master has its own pair of arbitration lines that connect it directly to the PCI bus arbiter.own pair of arbitration lines that connect it directly to the PCI bus arbiter.

Error linesError lines : used to report parity and other error : used to report parity and other error

PCI Bus Lines (Optional)PCI Bus Lines (Optional) Interrupt pinsInterrupt pins : provide for PCI devices that must generate requests for : provide for PCI devices that must generate requests for

service. Each PCI device has its own interrupt line or lines to an interrupt service. Each PCI device has its own interrupt line or lines to an interrupt controller.controller.

Cache support pinCache support pin : these pins are needed to support a memory on PCI : these pins are needed to support a memory on PCI that can be cached in the processor or another device.that can be cached in the processor or another device.

64-bit bus extension pin64-bit bus extension pin : include 32 lines that are time multiplexed for : include 32 lines that are time multiplexed for address and data and that are combined with the mandatory address/data address and data and that are combined with the mandatory address/data lines to form a 64-bit address/data bus. Other lines in this group are used to lines to form a 64-bit address/data bus. Other lines in this group are used to interpret and validate the signal lines that carry the address and data. There interpret and validate the signal lines that carry the address and data. There are two lines that enable two PCI devices to agree to use 64 bit capability.are two lines that enable two PCI devices to agree to use 64 bit capability.

JTAG/boundary scan pinsJTAG/boundary scan pins : These signal lines support testing procedures : These signal lines support testing procedures define in IEEE stabdard 1149.1.define in IEEE stabdard 1149.1.

PCI CommandsPCI Commands

Transaction between initiator Transaction between initiator (master) and target(master) and target

Master claims busMaster claims bus Determine type of transactionDetermine type of transaction

• e.g. I/O read/writee.g. I/O read/write Address phaseAddress phase One or more data phasesOne or more data phases

PCI Read Timing DiagramPCI Read Timing Diagram

PCI Bus ArbiterPCI Bus Arbiter

PCI Bus ArbitrationPCI Bus Arbitration