1 ECE 545 Introduction to VHDL Introduction to VHDL for Synthesis Lecture 2.
Synthesis Of VHDL Code
description
Transcript of Synthesis Of VHDL Code
![Page 1: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/1.jpg)
Chapter 6 1
Synthesis Of VHDL Code
RTL Hardware Design
![Page 2: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/2.jpg)
Chapter 6 2
1. Fundamental limitation of EDA software2. Realization of VHDL operator3. Realization of VHDL data type4. VHDL synthesis flow5. Timing consideration
RTL Hardware Design
Outline
![Page 3: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/3.jpg)
Chapter 6 3
Can “C-to-hardware” be done? EDA tools:
◦ Core: optimization algorithms◦ Shell: wrapping
What does theoretical computer science say?◦ Computability ◦ Computation complexity
RTL Hardware Design
1. Fundamental limitation of EDA software
![Page 4: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/4.jpg)
Chapter 6 4
A problem is computable if an algorithm exists.
E.g., “halting problem”:◦ can we develop a program that takes any
program and its input, and determines whether the computation of that program will eventually halt?
any attempt to examine the “meaning” of a program is uncomputable
RTL Hardware Design
Computability
![Page 5: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/5.jpg)
Chapter 6 5
How fast an algorithm can run (or how good an algorithm is)?
“Interferences” in measuring execution time: ◦ types of CPU, speed of CPU, compiler etc.
RTL Hardware Design
Computation complexity
![Page 6: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/6.jpg)
Chapter 6 6RTL Hardware Design
Big-O notation f(n) is O(g(n)):
if n0 and c can be found to satisfy: f(n) < cg(n) for any n, n > n0
g(n) is simple function: 1, n, log2n, n2, n3, 2n
Following are O(n2):
![Page 7: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/7.jpg)
Chapter 6 7
Filter out the “interference”: constants and less important terms
n is the input size of an algorithm The “scaling factor” of an algorithm:
What happens if the input size increases
RTL Hardware Design
Interpretation of Big-O
![Page 8: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/8.jpg)
Chapter 6 8RTL Hardware Design
E.g.,
![Page 9: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/9.jpg)
Chapter 6 9
Intractable problems: ◦ algorithms with O(2n)◦ Not realistic for a larger n◦ Frequently tractable algorithms for sub-optimal
solution exist Many problems encountered in synthesis
are intractable
RTL Hardware Design
![Page 10: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/10.jpg)
Chapter 6 10
Synthesis software does not know your intention
Synthesis software cannot obtain the optimal solution
Synthesis should be treated as transformation and a “local search” in the “design space”
Good VHDL code provides a good starting point for the local search
RTL Hardware Design
Theoretical limitation
![Page 11: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/11.jpg)
Chapter 6 11
What is the fuss about:◦ “hardware-software” co-design?◦ SystemC, HardwareC, SpecC etc.?
RTL Hardware Design
![Page 12: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/12.jpg)
Chapter 6 12
Logic operator◦ Simple, direct mapping
Relational operator◦ =, /= fast, simple implementation exists◦ >, < etc: more complex implementation, larger
delay Addition operator Other arith operators: support varies
RTL Hardware Design
2. Realization of VHDL operator
![Page 13: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/13.jpg)
Chapter 6 13RTL Hardware Design
Operator with two constant operands:◦Simplified in preprocessing◦No hardware inferred◦Good for documentation ◦E.g.,
![Page 14: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/14.jpg)
Chapter 6 14RTL Hardware Design
Operator with one constant operand:◦Can significantly reduce the hardware complexity
◦E.g., adder vs. incrementor◦E.g
y <= rotate_right(x, y); -- barrel shiftery <= rotate_right(x, 3); -- rewiringy <= x(2 downto 0) & x(7 downto 3);
◦E.g., 4-bit comparator: x=y vs. x=0
![Page 15: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/15.jpg)
Chapter 6 15RTL Hardware Design
An example 0.55 um standard-cell CMOS implementation
![Page 16: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/16.jpg)
Chapter 6 16
Use and synthesis of ‘Z’ Use of ‘-’
RTL Hardware Design
3. Realization of VHDL data type
![Page 17: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/17.jpg)
Chapter 6 17RTL Hardware Design
Use and synthesis of ‘Z’ Tri-state buffer:
◦ Output with “high-impedance”◦ Not a value in Boolean algebra ◦ Need special output circuitry (tri-state buffer)
![Page 18: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/18.jpg)
Chapter 6 18
Major application:◦ Bi-directional I/O pins◦ Tri-state bus
VHDL description:y <= 'Z' when oe='1' else a_in;
‘Z’ cannot be used as input or manipulatedf <= 'Z' and a;y <= data_a when in_bus='Z' else data_b;
RTL Hardware Design
![Page 19: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/19.jpg)
Chapter 6 19RTL Hardware Design
Separate tri-state buffer from regular code:◦ Less clear:with sel select y <= 'Z' when "00", '1' when "01"|"11", '0' when others;◦ better:with sel select tmp <= '1' when "01"|"11", '0' when others; y <= 'Z' when sel="00" else tmp;
![Page 20: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/20.jpg)
Chapter 6 20RTL Hardware Design
Bi-directional i/o pins
![Page 21: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/21.jpg)
Chapter 6 21RTL Hardware Design
![Page 22: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/22.jpg)
Chapter 6 22RTL Hardware Design
![Page 23: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/23.jpg)
Chapter 6 23RTL Hardware Design
Tri-state bus
![Page 24: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/24.jpg)
Chapter 6 24RTL Hardware Design
![Page 25: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/25.jpg)
Chapter 6 25RTL Hardware Design
Problem with tri-state bus◦ Difficult to optimize, verify and test ◦ Somewhat difficult to design: “parking”, “fighting”
Alternative to tri-state bus: mux
![Page 26: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/26.jpg)
Chapter 6 26RTL Hardware Design
Use of ‘-’ In conventional logic design
◦ ‘-’ as input value: shorthand to make table compact◦ E.g.,
![Page 27: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/27.jpg)
Chapter 6 27RTL Hardware Design
◦ ‘-’ as output value: help simplification◦ E.g.,
‘-’ assigned to 1: a + b‘-’ assigned to 0: a’b + ab’
![Page 28: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/28.jpg)
Chapter 6 28RTL Hardware Design
Use ‘-’ in VHDL As input value (against our intuition): Wrong:
![Page 29: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/29.jpg)
Chapter 6 29RTL Hardware Design
Fix #1:
Fix #2:
![Page 30: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/30.jpg)
Chapter 6 30RTL Hardware Design
Wrong:
• Fix:
![Page 31: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/31.jpg)
Chapter 6 31RTL Hardware Design
‘-’ as an output value in VHDL May work with some software
![Page 32: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/32.jpg)
Chapter 6 32
Synthesis: ◦ Realize VHDL code using logic cells from the
device’s library◦ a refinement process
Main steps:◦ RT level synthesis ◦ Logic synthesis◦ Technology mapping
RTL Hardware Design
4. VHDL Synthesis Flow
![Page 33: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/33.jpg)
Chapter 6 33RTL Hardware Design
![Page 34: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/34.jpg)
Chapter 6 34
Realize VHDL code using RT-level components
Somewhat like the derivation of the conceptual diagram
Limited optimization Generated netlist includes
◦ “regular” logic: e.g., adder, comparator◦ “random” logic: e.g., truth table description
RTL Hardware Design
RT level synthesis
![Page 35: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/35.jpg)
Chapter 6 35
“regular” logic can be replaced by pre-designed module◦ Pre-designed module is more efficient◦ Module can be generated in different levels of
detail◦ Reduce the processing time
RTL Hardware Design
Module generator
![Page 36: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/36.jpg)
Chapter 6 36
Realize the circuit with the optimal number of “generic” gate level components
Process the “random” logic Two categories:
◦ Two-level synthesis: sum-of-product format◦ Multi-level synthesis
RTL Hardware Design
Logic Synthesis
![Page 37: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/37.jpg)
Chapter 6 37RTL Hardware Design
E.g.,
![Page 38: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/38.jpg)
Chapter 6 38
Map “generic” gates to “device-dependent” logic cells
The technology library is provided by the vendors who manufactured (in FPGA) or will manufacture (in ASIC) the device
RTL Hardware Design
Technology mapping
![Page 39: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/39.jpg)
Chapter 6 39RTL Hardware Design
E.g., mapping in standard-cell ASIC
Devicelibrary
![Page 40: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/40.jpg)
Chapter 6 40RTL Hardware Design
Cost: 31 vs. 17
![Page 41: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/41.jpg)
Chapter 6 41RTL Hardware Design
E.g., mapping in FPGA With 5-input LUT (Look-Up-Table) cells
![Page 42: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/42.jpg)
Chapter 6 42
Logic operators: software can do a good job Relational/Arith operators: manual
intervention needed “layout” and “routing structure”:
◦ Silicon chip is 2-dimensional square◦ “rectangular” or “tree-shaped” circuit is easier to
optimize
RTL Hardware Design
Effective use of synthesis software
![Page 43: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/43.jpg)
Chapter 6 43RTL Hardware Design
![Page 44: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/44.jpg)
Chapter 6 44
Propagation delay Synthesis with timing constraint Hazards Delay-sensitive design
RTL Hardware Design
5. Timing consideration
![Page 45: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/45.jpg)
Chapter 6 45RTL Hardware Design
Propagation delay Delay: time required to propagate a signal
from an input port to a output port Cell level delay: most accurate Simplified model:
The impact of wire becomes more dominant
![Page 46: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/46.jpg)
Chapter 6 46RTL Hardware Design
E.g.
![Page 47: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/47.jpg)
Chapter 6 47RTL Hardware Design
System delay The longest path (critical path) in the
system The worst input to output delay E.g.,
![Page 48: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/48.jpg)
Chapter 6 48RTL Hardware Design
“False path” may exists:
![Page 49: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/49.jpg)
Chapter 6 49
RT level delay estimation:◦ Difficult if the design is mainly “random” logic◦ Critical path can be identified if many complex
operators (such adder) are used in the design.
RTL Hardware Design
![Page 50: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/50.jpg)
Chapter 6 50
Multi-level synthesis is flexible It is possible to reduce by delay by adding
extra logic Synthesis with timing constraint
1. Obtain the minimal-area implementation2. Identify the critical path3. Reduce the delay by adding extra logic4. Repeat 2 & 3 until meeting the constraint
RTL Hardware Design
Synthesis with timing constraint
![Page 51: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/51.jpg)
Chapter 6 51RTL Hardware Design
E.g.,
![Page 52: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/52.jpg)
Chapter 6 52RTL Hardware Design
Area-delay trade-off curve
![Page 53: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/53.jpg)
Chapter 6 53RTL Hardware Design
Improvement in “architectural” level design (better VHDL code to start with)
![Page 54: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/54.jpg)
Chapter 6 54
Propagation delay: time to obtain a stable output
Hazards: the fluctuation occurring during the transient period ◦ Static hazard: glitch when the signal should be
stable◦ Dynamic hazard: a glitch in transition
Due to the multiple converging paths of an output port
RTL Hardware Design
Timing Hazards
![Page 55: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/55.jpg)
Chapter 6 55RTL Hardware Design
E.g., static-hazard (sh=ab’+bc; a=c=1)
![Page 56: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/56.jpg)
Chapter 6 56RTL Hardware Design
E.g., dynamic hazard (a=c=d=1)
![Page 57: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/57.jpg)
Chapter 6 57RTL Hardware Design
Dealing with hazards Some hazards can be eliminated in theory E.g.,
![Page 58: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/58.jpg)
Chapter 6 58
Eliminating glitches is very difficult in reality, and almost impossible for synthesis
Multiple inputs can change simultaneously (e.g., 1111=>0000 in a counter)
How to deal with it? Ignore glitches in the transient period and retrieve the data after the signal is stabilized
RTL Hardware Design
![Page 59: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/59.jpg)
Chapter 6 59
Boolean algebra ◦ the theoretical model for digital design and most
algorithms used in synthesis process◦ algebra deals with the stabilized signals
Delay-sensitive design ◦ Depend on the transient property (and delay) of
the circuit◦ Difficult to design and analyze
RTL Hardware Design
Delay sensitive design and its danger
![Page 60: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/60.jpg)
Chapter 6 60RTL Hardware Design
E.g., hazard elimination circuit: ac term is not needed
E.g., edge detection circuit (pulse=a a’)
![Page 61: Synthesis Of VHDL Code](https://reader030.fdocuments.net/reader030/viewer/2022033018/56815ff3550346895dcef1be/html5/thumbnails/61.jpg)
Chapter 6 61
What’s can go wrong:◦ E.g., pulse <= a and (not a);◦ During logic synthesis, the logic expressions will be
rearranged and optimized.◦ During technology mapping, generic gates will be
re-mapped◦ During placement & routing, wire delays may
change◦ It is bad for testing verification
If delay-sensitive design is really needed, it should be done manually, not by synthesis
RTL Hardware Design