Synchronization Using Phase-Locked Loops

EECS 270C / Winter 2013 Prof. M. Green / Univ. of California, Irvine 1

Synchronization Using Phase-Locked Loops

Example: 16:1 Multiplexer

Input parallel data

625 Mb/s

Input reference clock

625 MHz

Output serial data10 Gb/s

16

10 GHz high-speed clock

Clock multiplier unit

(CMU)

16:1

How can we generate the 10 GHz clock to be synchronized with the 625 MHz reference clock?


Ideally, we wish to have Vout = 16·Vin.

Let the op-amp be modeled with a 1st-order transfer function:

p

A0

At DC:

Voltage Amplification

R

15R

Vin

VoutV

+

_

Vf


Frequency Multiplication

Fin

Fout

Ff

Vc

frequencydetector

voltage-controlledoscillator

frequencydivider

frequency transfer function:

Since frequency ratio is not exactly N, exact synchronization is not possible.

feedforward

feedback


Achieving Exact Synchronization (1)

Consider replacing the amplifier with an ideal integrator:

R

15R

Vin

VoutV

+

_

Vf

0

A0


Achieving Exact Synchronization (2)

Consider a sine function:

Define instantaneous angular frequency:

If we can arrange to have the detector respond to phase difference (instead of frequency difference), then integration is naturally introduced into the loop ...


Phase-Locked Loop

in

f

Vc

phasedetector

voltage-controlledoscillator

frequencydivider

feedforward

feedback

^

^

^

inherentintegration

exactsynchronization

jitter frequency

Jitter Transfer Function:

^

^

^


Jitter-free clockcarrier frequency fc

Jitter amplitude = = 0.25 UI

Jitter frequency fj =

Illustration of Sinusoidal Jitter

Clock withadded jitter


PLL Step Response

Vin

VcPD VCO

^Vout

Example for N = 1:

0

input phase step

^

^

^

^


PLL Frequency Response

in

f

^Vc

PD VCO out

N

NClosed-looptransfer function:

Unity-gainfrequency:

^

Loop gain:^


Jitter Transfer Functions

in

f

^Vc

PD VCO out

vco

++

lowpasscharacteristic

highpasscharacteristic 0

N

1


Disadvantages of 1st-Order PLL

• Higher-order transfer function would provide better attenuation of jitter.

• Kpd & Kvco have circuit-related constraints; designer would prefer more degrees of freedom.

• Phase detector operation requires filtering, which adds poles/zeros to the transfer function.


Phase Detectors

1. Analog Multiplier

Detector characteristic is sensitive to bothphase and amplitude.

Vin, Vf

Vd

- +


CMOS Multiplier Realization

ISS

RLRL

Vf+ Vf-

Vin+ Vin-Vin- Vin+

_ +Vout

M2 M2

M1 M1 M1 M1

VDD

Large input amplitudes:

Describes an “XNOR” gate...

Small input amplitudes: linear operation


Vin

Vf

Vd

Vin

Vf

Vd

2. XNOR (“Digital Multiplier”)

+-

Kpd negative

Kpd positive

Digital operation allows limiting Vd independent of input amplitudes


Properties of XNOR Phase Detector

+-

unstable equilibrium

stable equilibrium

Vswing

Vin

Vf

Vd

• Useful PD range is [-, 0]

• Vd = 0 corresponds to = -/2 steady-state phase offset

• In order to extract the average value of Vd, a loop filter is needed...


Loop Filters (1)

A loop filter is used to average the PD output and provide a higher-order jitter transfer function.

Vd VcR

C

Consider a simple RC LPF:

0 reduced, but phase margin also reduced!Resulting jitter peaking is undesirable.

−20 dB/decade

−40 dB/decade

0 dB


Loop Filters (2)

Vd VcR1

C

R2

LPF with added transmission zero:

• 0 once again in 1-pole rolloff region no jitter peaking• Parasitic elements will add high-frequency poles;

detailed loop simulations required in practice.• Any PLL with one pole at s = 0 is said to be “Type 1.”

p z

−20 dB/dec.

−40 dB/dec.

−20 dB/dec.


Steady-State Phase Error^

Loop gain:

Errortransfer function:

Input frequency step:

If

then locking cannot occur!

R1

R2 CActive loop filter:

additional pole at 0

Type II PLL

|G|

0

−40 dB/decade

−20 dB/decade

Vin

Vf

Lock Acquisition (1)

Consider the case where fin > ff and both (constant) frequencies are applied to an XOR:

If the frequencies are close together, periods where Vpd is mostly positive or mostly negative can be observed.



^

out increases (correct direction)

out decreases (wrong direction)

in - out

Suppose initially out < in :

Then phase difference moves to the right in the PD characteristic:

When out increases, decreases, and slows down.When out decreases, increases, and speeds up.



t

t

VC

slows down

speeds up

speeds up

VP = “Pull-in voltage”

Since VP > 0, on average out will increase, thereby moving closer to lock

After many of these cycles, the frequency is “pulled in.”

Pull-in time:int loop filter integration time constant

initial frequency difference



fin = 1 GHzKvco = 5 MHz/VK = 106 rad/sec = 100 ns

fout(0) = 1.002 GHz

Control voltage transient showing pull-in:

cycle slips


3. Combinational circuit version

To lengthen the stable region of PD characteristic, we use edge detection instead of level detection:

Idea:

Vin

Vf

Vd

Vin

Vf

Vd

Realization:

+-

PD characteristic:

Entire region [0,2] now usable!


4. Phase-Frequency Detector (PFD)

Vin

Vf

Vup

Vdn

Vin

Vf

Vup

Vdn

Phase detection behavior:

Vin leads Vf Vin in phase with Vf


+2 +4

-4 -2

PFD Response to Frequency Difference:

Vin

Vf

Vup

Vdn

PFD exhibits faster frequency acquisition than conventional phase detector.


Charge Pump Phase Detector

Iout

Ich

-Ich

2

-2

Vin

Vfb

Vup

Vdn

Ich

Ich

VCIout

R

C Cp

|Zf|

z p

−20 dB/dec.


CMOS Charge Pump Realizations

Ich

Ich

Iout

Vdn

Vup

Single-ended:

cmfb

IchIch

Vdn

VdnVup

VupVdn

Vup Vdn

Vup

Differential:

Iout+ Iout-

PFD

Ich

Ich

VCO

KVCO

VC

in

out

fb

|G|

z p

−20 dB/dec.

−40 dB/dec.

−40 dB/dec.


Type II PLL with PFD & Charge Pump

^

For :


Effect of Parasitic Pole

Larger Cp lower p jitter peaking

p = 0

p = 0/10

p = 100

p = 0/10

p = 100

p = 0

Open-Loop Freq. Response:

Closed-Loop Freq. Response:


Measured PLL Locking

Design parameters:

Settling time (10%) ≈ 15 µs


Motivation for CDR: Deserializer (1)

If input data were accompanied by a well-synchronized clock, deserialization could be done directly.

Input clock

Input data

channel

1:2DMUX

1:2DMUX

1:2DMUX


• Providing two high-speed channels (for data & clock) is expensive.

• Alignment between data & clock signals can vary due to different channel characteristics for the different frequency components. Hence retiming would still be necessary.

Clock

Data

Motivation for CDR (2)

input data ClockRecovery

circuit

retimed data

recovered clock

PLLs naturally provide synchronization between external and internal timing sources.A CDR is often implemented as a PLL loop with a special type of PD...


f

Return-to-Zero vs. Non-Return-to-Zero Formats

NRZ

RZ

1 0 1 1 0 1 0

Tb

RZ spectrum has energy at 1/Tb conventional phase detector can be used.

NRZ spectrum has null at 1/Tb ??

f


Phase Detection of RZ Signals

Vdata

VRCK

Vd

Vdata

VRCK

Vd

• Phase detection operates same as for clock signals for logic 1.

• Vd exhibits 50% duty cycle for logic 0.

• Kpd will be data dependent.


Phase Detection of NRZ Signals

Vdata

VRCK

Vd

Vdata

VRCK

Vd

Since data rate is half the clock rate, multiplying phase detection is ineffective.

• RZ signals can use same phase detector as clock signals

• RZ data path circuitry requires bandwidth that is double that of NRZ.

• Different type of phase detection required for NRZ signals.


Idea: Mix NRZ data with delayed version of itself instead of with the clock.

Example: 1010 data pattern (differential signaling)

X X

= =

Tb

fundamental generated


Operation of D Flip-Flips (DFFs)

CMOS transmission gate:

D

CK

CK

CK

CK

QI

latch:

D

CK

CK

CK

CK

QICK

CK CK

CK

Q

Master Slave

DFF:

Ideal waveforms:

D

CK

Q

D0 D1 D2

D0 D1 D2

Symbol:

D Q

No bubble Q changes following rising edge of CK


DFF Setup & Hold Time

tsetup thold

When a data transition occurs within the setup & hold region, metastability occurs.

D

CK

Q

At CK rising edge, the master latches and the slave drives.


DFF Clock-to-Q Delay

D

CK

CK

CK

CK

QICK

CK CK

CK

Q

Master Slave

D0 D1 D2

D0 D1 D2

D

CK

Q

tck-q

tck-q is determined by delays of transmission gate and inverter.


Din

RCK

P

Q

Delay between Din to Q is related to phase between Din & RCK

Realization of Data/Data Mixing :

Q

P

D0

D0

D1

D1

D2

D2

D3

D3

D4

D1 D2 D3

D0 D1 D2 D3

Din

RCK

RCK early:

D0 D1 D2 D3

D0 D1 D2 D3

D0

D1

D1

D2

D2

D3

D3

D4

RCK synchronized:

Same as Din, synchronized with RCK


Define zero phase difference as a data transition coinciding with RCK falling edge; i.e., RCK rising edge is in center of data eye.

Q

P

Din

RCK

RCK early ( < 0): RCK synchronized ( = 0):

Tb

t

Tb

t


Din

RCK

P

Q

Phase detector characteristic also depends on transition density:

0011… pattern:

In general,

where average transition density

0101… pattern:

Q

P

Din

RCK

Vswing


Both slope and offset of phase-voltage characteristicvary with transition density!

Constructing CDR PD Characteristic

- +

= 0.25 = 0.5

= 1

slope:

intercept:


To cancel phase offset:

Din

RCK

P

Q

R

QR

D0 D1 D2 D3

D0 D1 D2 D3

Q

RCK

QR

R

C. R. Hogge, “A self-correcting clock recovery circuit,” IEEE J. Lightwave Tech., vol. 3, pp. 1312-1314, Dec. 1985.

Always 50% duty cycle;average value is

Kpd still varies with ,but offset variation cancelled.

-+

+1/2

-1/2

= 1

= 0.5


Transconductance Block

ISS ISS

P+ P- R- R+

Iout+ Iout-


Due to inherent mixing operation, Hogge PD is not a good frequency detector. A frequency acquisition loop with a reference clock is usually needed:

J. Cao et al., “OC-192 transmitter and receiver in 0.18 CMOS,” JSSC. vol. 37, pp. 1768-1780, Dec. 2002.


Non-Idealities in Hogge Phase Detector:A. Clock-to-Q Delay (1)

Din

RCK

P

Q

R

QR

tck-Q

tck-Q


Din

RCK

Q

QR

P

R

tck-Q

tck-Q

+

-os


Result is an input-referred phase offset:


Din

RCK

tck-Q

CDRDin

Dout

RCK

Phase offset moves RCK away fromcenter of data, making retiming lessrobust.




Din

RCK

P

Q

R

QR

tck-Q

tck-Q

t

Set

Dt

Din

Dt

RCK

Q

QR

P

R

Use a compensating delay:


Non-Idealities in Hogge Phase Detector:B. Delay Between P & R (1)

Din

RCK

P

Q

R

QR

Din

RCK

Q

QR

P

R

P and R are offset by 1/2 clock period


P

R

Din

RCK

P

Q

R

QR

Vcontrol

to VCO


Average value of Vcontrol is well-controlled, but resulting ripplecauses high-frequency jitter.


Idea: Based on R output, create compensating pulses:

Din

RCK DFF

latch

latch

latch

Din

RCK

Q

QR

P (up)

R (dn)

Vcontrol

Standard Hogge/charge pump operation for single input pulse:



Din

RCK DFF

latch

latch

latchQ4

Q3

Q2

Q1

Din

RCK

Q4

Q3

Q2

Q1

Vcontrol

P (up)

R (dn)

P’(dn)

R’(up)

Cancels out effect of next pulse



Other Nonidealities of Hogge PD (1)

PD

Dif

fere

ntia

l Out

put

(mV

)

0

-20

-40

-60

60

40

20

0 10p 20p 30p 40p 50p-30p-40p-50p

-20p -10p

Data Delay in regard to Clock (s)

response from ideal linear PD

simulated result of one linear PD


Effect of Transition Density:



Effect of DFF bandwidth limitation:



Effect of XOR bandwidth limitation:

Since the PD output signals are averaged, XOR bandwidth limitation has negligible effect.



Effect of XOR Asymmetry:



Binary Phase Detectors

Idea: Directly observe phase alignment between clock & data

Clock falling edge early:Decrease Vcontrol

Clock falling edge late:Increase Vcontrol

Clock falling edge centered:No change to Vcontrol

Ideal binary phase-voltage characteristic:

+1/2

-1/2

Also known as “bang-bang” phase detector


D Flip-Flop as Phase Detector

Early clock:Data transitions align

with clock low

Late clock:Data transitions align

with clock high

Din

RCK

Din

RCK

RCK VP

Realization using double-clocked DFF; note that RCK/Din connections are reversed:

VPRCK=

Top (bottom) DFF detects on Din rising (falling) edge; DFF selected by opposite Din edge to avoid false transitions due to clock-q delay.


What happens if =0?

tsetup

thold

D

CK

Q

• If transition at D input occurs within setup/hold time, metastable operation results.

• Q output can “hang’’ for an arbitrarily long time if zero crossings of D & CK occur sufficiently close together.

• Metastable operation is normally avoided in digital circuit operation(!)


Dog Dish Analogy

???

A dog placed equidistant between two dog dishes will starve (in theory).


Non-Idealities in Binary DFF Phase Detector

1. Metastable operation difficult to characterize & simulate, varies widely over processing/temperature variations. Kpd (and therefore jitter transfer function parameters) are difficult to analyze. Exact value of Kpd depends on metastable behavior and varies with input jitter.

2. Large-amplitude pattern-dependent variation is present in phase detector output while locked.

3. During long runs phase detector output remains latched, resulting in VCO frequency changing continuously:

VP

RCK


Idea: Change VCO frequency for only one clock period

VP

RCK

RCK early RCK late

Circuit realization should sample data with clock (instead of clock with data)while maintaining bang-bang operation.


Alexander Phase Detector

RCK

Q1Q2

Q3 Q4

UP

DN

RCKQ1

Q2

Q3

Q4

UP

DN

RCK early

Q1 leads Q3; Q2/Q4 in phase

RCK late

Q3 leads Q1; Q1/Q4 in phase


Simulation Results: Alexander PD

DFF outputs

VCO controlvoltage


Binary PDLinear PD

Simulation Comparison: Linear vs. Binary

• very small freq. acquisition range• low steady-state jitter

• high freq. acquisition range• high steady-state jitter

Vcontrol Vcontrol


Half-Rate CDRs

To relax speed requirements for a given fabrication technology, a half-rate clock signal can be recovered:

Din

RCK

RCK2

input data

full-rate recovered clock

half-rate recovered clock

• Can be used in in applications (e.g., deserializer) where full-rate clock is not required.

• Duty-cycle distortion will degrade bit-error ratio & jitter tolerance compared to full-rate versions.


Idea 1: Input data can be immediately demultiplexed with half-rate clock

Din

RCK2

DA

DB

Din

RCK2

DA

DB

D0 D1 D2 D3 D4

D0 D2 D4

D1 D3

synchronized withclock transitions


Din

RCK2latch latch

latch latch

DAXA

XB DB

Splitting D flip-flopsinto individual latches:

synchronized with RCK2DB

RCK2

Din

XA

XB

DA

synchronized withboth RCK2 & Din

These pulse widths contain phase information.


DB

RCK2

Din

XA

XB

DA

RCK2

Din

P R

XA

XB

DA

DB

Complete Linear Half-Rate PD

J. Savoj & B. Razavi, “A 10Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector,” JSSC, vol. 36, pp. 761-768, May 2001.


Idea 2: Observe timing between Din, RCK and quadrature RCKQ

Din

RCK

RCKQ

S0 S1 S2

Clock late

Din

RCK

RCKQ

S0 S1 S2

Clock early

S0, S2 sampled with RCK transitions S1 sampled with RCKQ transitions

Phase logic:

clock early

clock late

no transition


Din

RCK

RCKQ

DI

DQ

VPD

Din

RCK

RCKQ

DI

DQ

VPD

Din

RCK

RCKQ

DI

DQ

VPD

Clock early Clock late

J. Savoj & B. Razavi, “A 10-Gb/s CMOS clock and data recovery circuit with a half-rate binary phase detector,” JSSC, vol. 38, pp. 13-21, Jan. 2003.


DLL-Based CDRs

fref CMUphase generator

phaseMUX

VC

C

PDDin

Dout

retimer

fck• CMU JBW can be optimized

to minimize fck jitter.

• No VCO inside CDR loop; less jitter generation.

• Can be arranged to have faster lock time.

CDR loop


Fast-Lock CDR for Burst-Mode Operation

Gated ring oscillator:EN

EN high: 7-stage ring oscillatorEN low: no oscillation

CDR based on 2 gated ring oscillators:

Din

RCK

Each ring oscillation waveform is forced to sync with one of the Din phases.

Synchronization Using Phase-Locked Loops

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