Synch on Izer

8/9/2019 Synch on Izer

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Synchonizer

Lecture b

EC2354 VLSI Design

R. Sivarajan, Assistant Professor

Department of ECE

Adhiparasakthi Engineering College


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Introduction Sequencing element characterize by setup and hold

time

If D changes before setup time, output reflects new

value after bounded propagation delay

If D changes after hold time, output reflects old value

a er oun e propaga on e ay

If D changes during aperture between setup and hold

time, output may be unpredictable

Properly designed synchronous circuits guarantee that

D is stable during aperture However many systems must interface with data

coming from source are not synchronized to same clock


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Contd

Synchronizer circuit accepts an input that canchange at arbitrary time and produce an output aligned

to synchronizers clock

Because in ut can chan e durin s nchronizers

aperture, synchronizer has nonzero probability ofproducing metastable output


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Metastability Latch bistable device

It has 2 stable state 0 and 1

Under right condition, latch enter a metastable state in

which output at an indeterminate level between 0 and 1

Figure below shows the simple model for a static latch

cons s ng o sw c es an nver ers


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Contd

While latch transparent, sample switch closed and hold

switch opened

While latch opaque, sample switch opened and hold

switch closed

Figure below shows DC transfer characteristics of the 2inverters


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Contd


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Contd

Because A=B when latch is opaque, stable states are

A=B=0 and A=B=VDD

Metastable state is A=B=Vm, where Vm is not a legal

logic level

This point is called metastable because voltages are selfconsistent and remain there indefinitely


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Simple

Synchronizer

Accepts input D and clock

Produces output Q that ought to be valid some boundeddelay after clock

Synchronizer has an aperture defined by setup and

If D stable during aperture, Q=D

If D changes during aperture, Q chosen arbitrary

Impossible to build perfect synchronizer because

duration of metastability can be unbounded


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Contd Figure below shows a simple synchronizer built from

pair of flip flops


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Contd F1 samples D

Output X be metastable for some time, but settle to agood level with high probability if we wait long enough

F2 samples X and produces output Q that should be

Synchronizer has a latency of one clock cycle Tc

It can fail if X has not settled to a valid level by a setup

time before second clock edge


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Contd


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Contd

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