Syllabus (VTU)

1

M.TECH-MICROELECTRONICS AND CONTROL SYSTEMS (EMS) I SEMESTER

12MAT11 APPLIED MATHEMATICS Subject Code 12MAT11 IA Marks 50

No. of Lecture Hours/Week 04 Exam Hours 03

Total No. of Lecture Hours 52 Exam Marks 100

Numerical Methods: Solution of algebraic and transcendental equations- iterative methods based on second degree equation – Muller method,(no derivation) Chebyshev method, general iteration method (first order),acceleration of convergence, system of non-linear equations, and complex roots – Newton-Raphson method, polynomial equations – Birge –Vieta method and Bairstow’s method. Numerical Solution of Partial Differential Equations: Classification of second order equations, parabolic equations- solution of one dimensional heat equation, explicit method ,Crank-Nicolson method and Du Fort-Frankel method, hyperbolic equations- solution of one dimensional wave equation. System of Linear Algebraic Equations and Eigen Value Problems: Iterative methods - Gauss-Seidal method, SOR method, Eigen value problems – Gerschgorian circle, Eigen values and Eigen vectors of real symmetric matrices -Jacobi method, Givens method. Interpolation: Hermite interpolation, spline interpolation, numerical solution of differential equations – Numerov method. Optimization: Linear programming- formulation of the problem, graphical method, general linear programming problem, simplex method, artificial variable technique -M-method. Graph Theory: Basic terminologies, types of graphs, sub graphs, graphs isomorphism, connected graphs-walks, paths, circuits, connected and disconnected graphs, operations on graphs, Eulerian paths and circuits, Hamiltonian paths and circuits, applications of graphs.

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Linear Algebra:Vector spaces, linear dependent, independence, basis and dimension, elementary properties, examples. Linear Transformations: Definition, properties, range and null space, rank and nullity, algebra of linear transformations- invertible, singular and non-singular transformations, representation of transformations by matrices. REFERENCE BOOKS 1. M K Jain, S R K Iyengar and R K Jain, “Numerical Methods for

Scientific and Engineering Computations”, New Age International, 2004.

2. M K Jain, “Numerical Solution of Differential Equations”, 2nd Edition, New Age International, 2008.

3. Dr. B.S. Grewal, “Numerical Methods in Engineering and Science”, Khanna Publishers, 1999.

4. Dr. B.S. Grewal, “Higher Engineering Mathematics”, 41st Edition, Khanna Publishers, 2011.

5. Narsingh Deo, “Graph Theory with Applications to Engineering and Computer Science”, PHI, 2012.

6. Kenneth Hoffman and Ray Kunze, “Linear Algebra”, 2nd Edition, PHI, 2011.

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12EMS12 ANALYSIS OF LINEAR SYSTEMS Subject Code 12EMS12 IA Marks 50



Linear Control Systems: Review, analytic & experimental modeling, review of transfer Function representation, analysis-time & harmonic response, frequency response specifications, random inputs. State Space Analysis: SISO, MIMO system analysis-solution-impulse response matrix, controllability-observability, observers, observer based feedback, composite system-parallel, feedback & tandem-concept of state feedback, state estimators-pole placement methods. Stability Analysis: Lyapunov’s stability criteria, generating Lyapunov function, testing for stability, introduction to phase lag, lag- lead, lead, PID controllers, digital control systems, sampling &data reconstruction, sampling theorem, hold operation, Z-transform-properties, inverse, solution of difference equation, system function, Pole- Zero location, frequency consideration, state variable methods of analysis of digital control systems, PID controller brief introduction, stability analysis of digital control systems by Jury’s criteria and bilinear transformation. REFERENCE BOOKS 1. Ogata.K., “Discrete Time Control Systems”,2nd Edition, PHI, 2011. 2. Gopal.M., “Digital Control and State Variable Methods”,TMH,2011. 3. Franklin,Powell., “Digital Control Systems”, Pearson Education,2006. 4. Charles L Phillips,H Troy Nagle, “Digital Control Systems Analysis

Design”,Prentice –Hall,1994.

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12EMS13 VLSI DESIGN

Subject Code 12EMS13 IA Marks 50



MOS Transistor Theory: n MOS / p MOS transistor, threshold voltage equation, body effect, MOS device design equation, sub threshold region, channel length modulation. mobility variation, tunneling, punch through, hot electron effect MOS models, small signal AC characteristics, CMOS inverter, βn / βp ratio, noise margin, static load MOS inverters, differential inverter, transmission gate, tristate inverter, BiCMOS inverter. CMOS Process Technology: Lambda based design rules, scaling factor, semiconductor technology overview, basic CMOS technology, p well / n well / twin well process, current CMOS enhancement (oxide isolation, LDD, refractory gate, multilayer inter connect) , circuit elements, resistor , capacitor, interconnects, sheet resistance & standard unit capacitance concepts delay unit time, inverter delays , driving capacitive loads, propagate delays, MOS mask layer, stick diagram, design rules and layout, symbolic diagram, mask feints, scaling of MOS circuits. Basics of Digital CMOS Design: Combinational MOS logic circuits-introduction, CMOS logic circuits with a MOS load, CMOS logic circuits, complex logic circuits, transmission gate, sequential MOS logic circuits - introduction, behavior of hi-stable elements, SR latch circuit, clocked latch and flip flop circuits, CMOS D latch and triggered flip flop, dynamic logic circuits - introduction , principles of pass transistor circuits, voltage boot strapping synchronous dynamic circuits techniques, dynamic CMOS circuit techniques. CMOS Analog Design: Introduction, single amplifier, differential amplifier, current mirrors, band gap references, basis of cross operational amplifier.

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Dynamic CMOS and Clocking: Introduction, advantages of CMOS over NMOS, CMOS\SOS technology, CMOS\bulk technology, latch up in bulk CMOS., static CMOS design, domino CMOS structure and design, charge sharing, clocking- clock generation, clock distribution, clocked storage elements. REFERENCE BOOKS 1. Neil Weste and K. Eshragian, “Principles of CMOS VLSI Design: A

System Perspective,” 2nd Edition, Pearson Education (Asia) Pte. Ltd., 2000.

2. Wayne, Wolf, “Modern VLSI design: System on Silicon”,4th

Edition,PHI,2011. 3. Douglas A Pucknell & Kamran Eshragian,“Basic VLSI Design”,3rd

Edition,PHI,2011. 4. Sung Mo Kang & Yosuf Lederabic Law, “CMOS Digital Integrated

Circuits: Analysis and Design”,3rd Edition, McGraw- Hill,2002.

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12EMS14 EMBEDDED SYSTEMS Subject Code 12EMS14 IA Marks 50



Overview of Embedded Systems, Design Aspects of Custom Processors: Logical synthesis design, RTL design, selection of standard processors, study of Microcontroller/DSP/ ARM architectures, embedded system development process, embedded system components and interfacing, hardware aspects, embedded system design examples. Embedded System Software Architecture, Embedded System Programming: 8051/6800/ARM programming, RTOS, programming handheld devices, Linux solution for embedded system development, RTOS case studies. REFERENCE BOOKS 1. Frank Vahid and Tony Givargis,“Embedded System Design”, Wiley,

2002. 2. David E. Simon,“An Embedded Software Primer”,Addison

Wesley,1999. 3. Daniel W.Lewis,“Fundamentals of Embedded System Software”,

PH,2002. 4. John Castsoulis,“Designing Embedded Hardware”,O’Reilly Media,

Inc,2005. 5. Tim Wilmherst,“ An Introduction to Design of Small Scale Embedded

Systems”, Palgrave (Publishers),2001.

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ELECTIVE - I

12EMS151 NON LINEAR SYSTEMS Subject Code 12EMS151 IA Marks 50


Total No. of Lecture Hours 52 Exam Marks 100 Introduction : Nonlinear phenomena, types, characteristics, methods of analysis of nonlinear systems, piecewise (Local) linearization. Phase-Plane Analysis: Introduction, general second order linear systems- singular (Equilibrium) points-classification and trajectories, multiple singular points and evaluation of type, sketching phase plane portrait for linear/nonlinear systems-isocline method, delta method, Pells’ method, limit cycles-prediction of existence and classification. Describing Function Method: Introduction, assumptions and definition, evaluation of describing function for functions like x2, x3, |x|x and common nonlinearities like relay, saturation, dead zone, hysterisis, backlash and a combination of these, Nyquist stability criteria, analysis of nonlinear systems using describing function method-evaluation of existence of limit cycle and calculation for magnitude and frequency of oscillation, dual input describing function, sub harmonic and jump phenomena. Lyapunov’s Method: Introduction, sign definiteness, Sylvester’s criteria, notion of stability-definitions, direct method, generation of Lyapunov function for linear and nonlinear systems-Krasovskii’s method, variable gradient method, Lure's criteria, Popov's method, circle criteria and its application, BIBO stability Relay control analysis, Hamels & Tsypkin loci, introduction to sliding mode control and its applications REFERENCE BOOKS 1. Gibson J. E., “Non linear Automatic Control”, McGraw Hill-1963. 2. J. C. Hsu and A. U. Mayer, “Modern Control Principles and Applications”, McGraw Hill,

1968. 3. H. K. Khalil, “Non Linear Systems”, 3rd Edition, Prentice Hall Intl. Inc.2001. 4. D. P. Atherton, “Non linear Control Engineering”, Chapman and Hall,1982. 5. M. Vidyasagar, “Nonlinear Systems Analysis”, 2nd Edition,Prentice Hall Intl. Inc. 2002. 6. K. Ogata, “Modern Control Engineering”,5th Edition,EEE,PHI,2011.

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12EMS152 PROCESS CONTROL AND INSTRUMENTATION Subject Code 12EMS152 IA Marks 50



Introduction to Process Control: Objectives and benefits,classification of control strategies, process control & block diagrams, analog & digital control. Mathematical Modeling: Principles, dynamic vs steady state models, general model principles,models of processes. Behavior of Process Control Systems: Dynamic Behavior of 1st and 2ndorder systems, standard process inputs, response of 1st and 2nd order systems, feedback controllers,PID controller, stability analysis and controller tuning. Control System Instrumentation: Temperature measurement using IC temperature sensor, RTD & thermocouple, measurement of strain, force, displacement, weight, flow, liquid level and pressure, signal conditioning & transmission, 4-20mA current transmitter for LVDT, signal conditioning for low level DC & AC signals, concept of shielding, grounding & EMI.

REFERENCE BOOKS 1. Thomas E Marlin, “Designing Process & Control Systems for Dynamic

Performance”,2nd Edition, McGraw-Hill,2000. 2. Robert B Northorp,“Insrumentation and Measurements”,2nd

Edition,CRC,Taylor &Francis,2005. 3. Surekha Bhanot, “Process Control:Principles and Applications”,Oxford

University Press,2008. 4. Seborg Edgar &Mellichamp, “Process Dynamics & Control”, 3rd Edition

New York, Wiley, 2010. 5. Curtis Johnson, “Process Control Instrumentation Technology”, PHI,

2011. 6. A.K.Sawhney,“Electrical & Measurement and Instrumentation”,

Dhanpat Rai & Co, 2012.

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12EMS153 ARTIFICIAL NEURAL NETWORKS Subject Code 12EMS153 IA Marks 50


Total No. of Lecture Hours 52 Exam Marks 100 Introduction: History, structure and function of single neuron, neural net architectures, neural learning, use of neural networks. Supervised Learning: single layer networks, perceptions, linear separability, perceptron training algorithm, guarantees of success, modifications. Multiclass Networks-I, multilevel discrimination, back propagation, setting parameter values, theoretical results, accelerating learning process, application, Madaline adaptive multilayer networks. Prediction networks, radial basis functions, polynomial networks, regularization, unsupervised learning, winner-take-all networks. Learning vector quantizing, counter propagation networks, adaptive resonance theorem, topologically organized networks, distance based learning, recognition. Associative Models: Hop Field networks, brain state networks, Boltzmann machines, hetero associations. Optimization using Hopfiled networks, simulated annealing, random search, evolutionary computation. REFERENCE BOOKS

1. R. Schalkoff, “Artificial Neural Networks”, McGraw Hill, 1997. 2. Kishan Mehrotra, C. K. Mohan, Sanjay Ranka , “Elements of Artificial

Neural Networks”, Penram,2010. 3. Hagan, Demuth and Beale, “Neural Network Design”,2nd

Edition,Cengage. 4. J. Zurada , “Introduction To Artificial Neural Systems”, Jaico, 2006. 5. Haykin Simon , “Neural Networks” , Pearson Education,2008. 6. B.Yegnanarayana, “Artificial Neural Networks”, PHI,2011.

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M.TECH-MICROELECTRONICS AND CONTROL SYSTEMS (EMS) II SEMESTER

12EMS21 OPTIMAL CONTROL SYSTEMS Subject Code 12EMS21 IA Marks 50



Introduction: S tatic and dynamic optimization,parameter optimization. Calculus of Variations: Problems of Lagrange,Mayer and Bolza. Euler-Lagrange equation and transversality conditions, Lagrange multipiliers. Pontryagin’s Maximum Principle: Theory, application to minimum time, energy and control effort problems, and terminal control problem. Dynamic Programming: Belaman’s principle of optimality, multistage decision Processes, application to optimal control. Linear Regulator Problem: Matrix Riccati equation and its solution, tracking problem, computational methods in optimal control, application of mathematical programming, singular perturbations, practical examples. REFERENCE BOOKS 1. D.E.Kirk, “Optimal Control Theory”,Dover Publication,2004. 2. A.P.Sage and C.C.White II, “Optimum Systems Control”, 2nd Edition,

Prentice-Hall, 1977. 3. D.Tabak and B.C.Kuo, “Optimal Control by Mathematical

Programming”, Prentice-Hall, 1971. 4. B.D.O. Anderson and J.B.Moore, “Linear Optimal Control”, Prentice-

Hall, 1998.

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12EMS22 MODERN POWER ELECTRONICS - I Subject Code 12EMS22 IA Marks 50


Total No. of Lecture Hours 52 Exam Marks 100 Introduction: Review of line commutated converters, inverters,voltage control & power factor improvement. Power Devices: BJT, MOSFET, IGBT and GTOs – operating characteristics and gate drive requirements and circuits. Switched Mode Rectifier:Various power circuit configurations & wave shaping techniques. Synchronous Link Rectifiers: Power circuit configurations, control techniques, application of these converters in load compensation, series compensators, multi-level converters. Inverters: Voltage source inverters - single phase & six step inverters, voltage control & PWM strategies, and implementation aspects, modification of power circuit for four quadrant operation. Current Source Inverters: Single phase and three-phase power circuit configuration and analysis. Load Commutated Inverters: principle of operation, modification of power circuit configuration for low frequency operation, phase controllers. REFERENCE BOOKS 1. Ned Mohan, Tore M. Undeland, William P. Robbins, “Power Electronics

Converters, Applications, and Design”, 3rd Edition. Wiley India Pvt Ltd, 2010. 2. Rashid M.H,“Power Electronics: Circuits Devices and Applications”,3rd Edition,

Pearson,2011. 3. Joseph Vithyathil, “Power Electronics- Principles and Applications”, TMH,

2011. 4. M D Singh & Kanchandani, “Power Electronics”,2nd Edition,TMH.

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12EMS23 HARDWARE DESCRIPTION LANGUAGES Subject Code 12EMS23 IA Marks 50



Hardware Design Environment: Digital system design process, Hardware Description Languages (HDLs), hardware simulation, hardware synthesis, structure of HDL module, styles of descriptions, delay models. Basic Language Elements: Identifiers, operators, expressions and signal assignment, data objects, data types, dataflow descriptions, behavioral descriptions, structural descriptions, procedures, tasks, and functions, mixed type description, advanced HDL descriptions, mixed language descriptions, writing test bench, examples of design using VHDL and Verilog. REFERENCE BOOKS 1. Z Navabi, “VHDL, Analysis & Modeling of Digital Systems”, 2nd

Edition,TMH,2007. 2. Nazeih M. Botros, “HDL Programming VHDL and Verilog”, Dreamtech

Press,2006. 3. J Bhaskar, “A VHDL Primer”,3rd Edition,PHI,2011. 4. J Bhaskar, “A Verilog HDL Synthesis-A Practical Primer”, BSP, 2001.

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12EMS24 CAD TOOLS FOR VLSI DESIGN Subject Code 12EMS24 IA Marks 50


Total No. of Lecture Hours 52 Exam Marks 100 High level Synthesis: CDFG representation, partitioning algorithms, scheduling algorithms, allocation algorithms. . Logic Synthesis & Verification: Introduction to combinational logic synthesis, binary decision diagram, cube representation, Kernels & co-Kernals, two level synthesis, PLA, PLA folding, ROBDD, ITE graphs, sequential synthesis. VLSI Automation Algorithms : Partitioning, problem formulation, classification of partitioning algorithms, group migration algorithms, simulated annealing & evolution, other partitioning algorithms, placement, floor planning & pin assignment, problem formulation, simulation base placement algorithms, other placement algorithms, constraint based floor planning, floor planning algorithms for mixed block & cell design. General & channel pin assignment. Global Routing: Problem formulation, classification of global routing algorithms, Maze routing algorithm, line probe algorithm, Steiner Tree based algorithms, ILP based approaches. Detailed Routing: problem formulation, classification of routing algorithms, single layer routing algorithms, two layer channel routing algorithms, three layer channel routing algorithms, and switchbox routing algorithms. Over the Cell Routing & via Minimization: Two layers over the cell routers, constrained & unconstrained via minimization. Compaction: Problem formulation, one-dimensional compaction, two dimension based compaction, hierarchical compaction. .

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REFERENCE BOOKS

1. Naveed Shervani, “Algorithms for VLSI Physical Design

Automation”,3rd Edition, Springer (BSP). 2. Deniel Gajski, Nikil Dutt and Allen Wu, “High level

Synthesis”,Springer,1992. 3. Christophn Meinel & Thorsten Theobold, “Algorithm and Data

Structures for VLSI Design”, Springer,1998. 4. Rolf Drechsheler : “Evolutionary Algorithm for VLSI”, 2nd Edition,Lap

Lambert Academic Publishers,2011. 5. Trimburger, “Introduction to CAD for VLSI”, Kluwer Academic

Publisher, 2002.

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ELECTIVE-II 12EMS251 MIXED MODE VLSI DESIGN Subject Code 12EMS251 IA Marks 50


Total No. of Lecture Hours 52 Exam Marks 100 Introduction : To CMOS analog circuits, MOS transistor. DC and AC small signal parameters from large signal model, common source amplifier with resistive load, diode load and current source load, source follower. Amplifiers: Common gate amplifier, cascade amplifier, folded cascade, frequency response of amplifiers, current source/sink/mirror, matching, Wilson current source and regulated cascade current source, band gap reference, differential amplifier, Gilbert cell. Opertional Amplifiers: Design of 2 stage op-amp, DC and AC response, frequency compensation, slew rate, offset effects, PSRR, noise, comparator, sense amplifier, sample and hold, sampled data circuits, switched capacitor filters, DAC, ADC, RF amplifier, oscillator, PLL, mixer. REFERENCE BOOKS 1. Razavi B, “Design of Analog CMOS Integrated Circuits”, McGraw Hill,

2001. 2. Razavi B., “RF Microelectronics”, Pearson, 2008. 3. Baker, Li, Boyce, “CMOS: Circuit Design, Layout and Simulation”,

John Wiley & Sons, 2011. 4. E. Allen, Douglas R. Holberg, “CMOS Analog Circuit Design”, Oxford

University Press, 2011.

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12EMS252 LOW POWER VLSI DESIGN Subject Code 12EMS252 IA Marks 50


Total No. of Lecture Hours 52 Exam Marks 100 Low Power VLSI Chips: Need, sources of power dissipation on digital integrated circuits. Emerging low power approaches, physics of power dissipation in CMOS devices. Device & Technology Impact on Low Power: Dynamic dissipation in CMOS, transistor sizing & gate oxide thickness, impact of technology scaling, technology & device innovation. Power Estimation, Simulation Power Analysis: SPICE circuit simulators, gate level logic simulation, capacitive power estimation, static state power, gate level capacitance estimation, architecture level analysis, data correlation analysis in DSP systems, Monte Carlo simulation. Probabilistic Power Analysis: Random logic signals, probability & frequency, probabilistic power analysis techniques, signal entropy. Low Power Design Circuit Level: Power consumption in circuits, flip flops & latches design, high capacitance nodes, low power digital cells library. Logic Level: Gate reorganization, signal gating, logic encoding, state machine encoding, pre-computation logic. Low Power Architecture & Systems: Power & performance management, switching activity reduction, parallel architecture with voltage reduction, flow graph transformation, low power arithmetic components, low power memory design. Low Power Clock Distribution: Power dissipation in clock distribution, single driver Vs distributed buffers, zero skew Vs tolerable skew, chip & package co design of clock network.

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Algorithm & Architectural Level Methodologies: Introduction, design flow, algorithmic level analysis & optimization, architectural level estimation & synthesis. REFERENCE BOOKS 1. Gary K. Yeap, “Practical Low Power Digital VLSI Design”, Springer

Verlag, 2009. 2. Rabaey, Pedram, “Low Power Design Methodologies”, Springer Verlag,

2010. 3. Kaushik Roy, Sharat Prasad, “Low-Power CMOS VLSI Circuit Design”

John Wiley, 2011.

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12EMS253 ADVANCED DIGITAL SIGNAL PROCESSING &APPLICATIONS Subject Code 12EMS253 IA Marks 50


Total No. of Lecture Hours 52 Exam Marks 100 Discrete Time Signals: Sequences; representation of signals on orthogonal basis, sampling and reconstruction of signals. Discrete Systems: Attributes, Z-Transform, analysis of LSI systems, frequency analysis, inverse systems, Discrete Fourier Transform (DFT), Fast Fourier Transform algorithm, implementation of Discrete Time Systems. Design of FIR Digital Filters: Window method, Park-McClellan's method. Design of IIR Digital Filters: Butterworth, Chebyshev and Elliptic approximations, lowpass, bandpass, bandstop and high pass filters, effect of finite register length in FIR filter design, parametric and non-parametric spectral estimation, introduction to multirate signal processing, application of DSP to speech and radar signal processing. REFERENCE BOOKS 1. A.V. Oppenheim and Schafer, “Discrete Time Signal Processing”,

Prentice Hall, 2001. 2. John G. Proakis and D.G. Manolakis, “Digital Signal Processing:

Principle, Algorithms and Applications”, Pearson Education, 2012. 3. L.R. Rabiner and B. Gold, “Theory and Application of Digital Signal

Processing”, Prentice Hall, 2009. 4. J.R. Johnson, “Introduction to Digital Signal Processing”, PHI, 2011.

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M.TECH-MICROELECTRONICS AND CONTROL SYSTEMS (EMS) III SEMESTER

12EMS31 HIGH SPEED VLSI DESIGN Subject Code 12EMS31 IA Marks 50



Introduction to High Speed Digital Design: Frequency, time and distance, capacitive and inductive effects, high speed properties of logic gates, speed and power, wire modeling and transmission lines. Signaling Convention and Circuits: Signaling modes for transmission lines, signaling over RC interconnect, driving lossy LC lines, bi-directional signaling, terminators, signaling standards, chip-to-chip, communication networks, ESD protection. Power Distribution and Noise: Power supply network, IR drops, power supply isolation,noise sources in digital system, cross talk, inter symbol interference. Timing Convention and Synchronization: Timing fundamentals, clocking styles, clock jitter, clock skew, clock generation, clock distribution, synchronization failure and meta-stability, PLL and DLL based clock aligners, asynchronous clocking techniques. Clocked & Non Clocked Logics: Single-rail domino logic, dual-rail domino structures, latched domino structures, clocked pass gate logic, static CMOS, DCVS logic, non-clocked pass gate families. Latching Strategies: Basic latch design, and latching single-ended logic and differential logic, race free latches for pre-charged logic asynchronous latch techniques.

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REFERENCE BOOKS 1. Kerry Bernstein & et. al, “High Speed CMOS Design Styles”, Kluwer,

1999. 2. Evan Sutherland, Bob stroll, David Harris, “Logical Efforts, Designing

Fast CMOS Circuits”, 1st Edition Morgan Kaufmann, 1999. 3. David Harris, “Skew Tolerant Domino Design”, 1st Edition, Morgan

Kaufmann,2005. 4. William S. Dally & John W. Poulton, “Digital Systems Engineering”,

Cambridge University Press, 1998. 5. Howard Johnson & Martin Graham, “High Speed Digital Design: A

Hand Book of Black Magic”, Prentice Hall PTR, 1993. 6. Jan M. Rabaey, et al, “Digital Integrated Circuits: A Design

Perspective”, 2nd Edition, PHI, 2011.

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ELECTIVES-III 12EMS321 DIGITAL SYSTEM DESIGN WITH FPGA Subject Code 12EMS321 IA Marks 50


Total No. of Lecture Hours 52 Exam Marks 100 Digital Design: Introduction, hierarchical design, controller(FSM), case study, FSM issues, timing issues, pipe lining, resource sharing, meta stability, synchronization, MTBF analysis, setup/hold time of various types of flip-flops, synchronization between multiple clock domains, reset recovery, proper resets. VHDL: Different models, simulation cycles, process, concurrent and sequential statements, loops, delay models, library, packages, functions, procedures, coding for synthesis, test bench. FPGA: Logic block and routing architecture, design methodology, special resources, Virtex-II, stratix architectures, programming FPGA, constraints, STA, timing closure, case study. REFERENCE BOOKS 1.Wakerly J F, Digital Design, “Principles and Practices, Pearson Education, 2009. 2. Kevin Skahil, “VHDL for Programmable Logic”, Addison Wesly,1996. 3. FPGA Data sheets and application notes.

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12EMS322 MODERN POWER ELECTRONICS - II Subject Code 12EMS322 IA Marks 50


Total No. of Lecture Hours 52 Exam Marks 100 DC- DC Converters - Principle of operation of buck, boost, buck-boost, Cuk, fly back, forward, push-pull, half bridge, full bridge & isolated Cuk converters, input & output filter design, multi-output operation of isolated converters, MMF equations, design of transformers and inductors. Modeling : Of the above converters using state averaging techniques, resonant inverters ,DC link inverters, modified circuit topologies for DC link voltage clamping. Voltage Control : PWM techniques (sigma, sigma - delta modulation) quasi resonant inverters, series resonant and parallel resonant, application of zero voltage and zero current switching for DC-DC converters (buck & boost). Inverters: Induction heating and UPS. REFERENCE BOOKS 1. Ned Mohan, Tore M. Undeland, William P. Robbins, “Power Electronics

Converters, Applications, and Design”, 3rd Edition. Wiley India, 2010. 2. D.M.Mitchell, “DC-DC Switching Regulator Analysis”, McGraw

Hill,1998. 3. Rashid M.H,“Power Electronics: Circuits Devices and Applications”,3rd

Edition, Pearson,2011. 4. Joseph Vithayathil, “Power Electronics: Principles and Applications”,

TMH, 2011. 5. R. Jai P Agarwal, “Power Electronic Systems – Theory and Design”,

Pearson Education, 2011.

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12EMS323 COMPUTER CONTROL OF INDUSTRIAL DRIVES Subject Code 12EMS323 IA Marks 50



Review of Micro Controllers in Industrial Drives System: Typical micro controller- 8 bit /16 bit (only block diagram), digital data acquisition system, voltage sensors, current sensors, frequency sensors and speed sensors. Evolution of Power Electronics in Drives: Power semiconductors devices used for drives control, GTO, BJT, power MOSFET, IGBT, MCT and IGCT structures, Ratings, comparison and their applications. Block diagram of power integrated circuit for D C motor drives. A C Machine Drives: General classification and National Electrical Manufacturer Association (NEMA) classification, speed control of Induction motors with variable voltage constant frequency, constant voltage variable frequency, (v/f) constant operation, drive operating regions, variable stator current operation, effect of harmonics. Synchronous Machine Drives: Wound field machine, comparison of Induction and wound field Synchronous machines, torque angle characteristics of salient pole synchronous machines, synchronous reluctance permanent magnet synchronous machines (SPM), variable reluctance machines (VRM). Phase Controlled Converters: Converter controls, linear firing angle control, cosine wave crossing control, phase locked oscillator principle, electro magnetic interference (EMI) and line power quality problems, cyclo converters, voltage fed converters, rectifiers, current fed converters. Principle of Slip Power Recovery Schemes: Static Kramer’s drive system, block schematic diagram, phasor diagram and limitations, static Scherbius scheme system using D.C link converters with cyclo-converter modes of operation, modified Scherbius drive for variable source, constant frequency (VSCF) generation.

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Principle of Vector Control of A C Drives: Phasor diagram, digital implementation block diagram, flux vector estimation, indirect vector control block diagram with open loop flux control, synchronous motor control with compensation. Expert System Application to Drives: (only block diagram approach), Expert system shell, design methodology, ES based P-I tuning of vector controlled drives system, fuzzy logic control for speed controller in vector control drives, structure of fuzzy control in feedback system. REFERENCE BOOKS 1. Bimal K.Bose, “Power Electronics and Motor Drives”, Elsevier, 2010. 2. Bimal K.Bose,“Modern Power Electronics & Drives”, PHI, 2011. 3. Badri Ram “Fundamentals of Microprocessors and Applications”, Dhanpat Rai, 2001. 4. W. Leonard “Control of Electric Drives”, Springer Verlag, 2001. 5. Haitham Abu-Rub,Atif Iqbal, Jaroslaw Guzinski “High Performance Control of AC Drives”,Wiley, 2012.

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ELECTIVE-IV 12EMS331 ADVANCED COMPUTER ARCHITECTURE Subject Code 12EMS331 IA Marks 50


Total No. of Lecture Hours 52 Exam Marks 100 Elements of Modern Architecture: System attributes to performance. RISC and CISC, Amdahl’s law multiprocessors and multi computers. Multi Vector and VLSI Models : VLSI complexity models, architectural development tracks, advanced pipelining and instruction level parallelism, linear pipeline processors, instruction level parallelism, pipeline hazards, dynamic scheduling, score board and Tomasulo approaches, reducing branch penalties with dynamic hardware prediction,compiler support for exploiting ILP, hardware support for extracting more parallelism, non linear pipeline processors, reservations table, latency analysis & collision free scheduling. Memory Hierarchy Technology: Hierarchical Memory Technology, inclusion, coherence and locality & memory capacity planning. Virtual Memory Technology: Virtual memory models TLB, paging, segmentation, memory replacement policies. Bus, Cache and Shared Memory: Back plane bus system, cache memory organization, shared memory organizations, sequential and weak consistency models. Multi Processors and Multi Computers: Multi processor systems intercom nects, cache coherence and synchronization mechanisms, message passing mechanisms scalable, multi-threaded and data flow architectures, latency hiding techniques, principle of multithreading, fine grain multi-computer, scalable and multi- threaded architectures, dataflow and hybrid architectures. Storage Systems: Types of storage devices, buses connecting I/O Devices to CPU/Memory I/O performance measures. reliability,availability and RAID, interfacing to an operating system, designing an I/O system, Unix file system performance.

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Parallel Language and Compilers: Code optimization and scheduling, loop parallelization & pipelining. REFERENCE BOOKS 1. Kaittwang, “Advanced Computer Architecture-Parallelism, Scalability,

Programmability”, McGraw Hill 2011. 2. Hamacher V.C. et al. “Computer Organization”, 2nd Edition, Mc Graw

Hill,2012. 3. J.L. Hennessy and D.A. Patterson, “Computer Architecture-A-

Quantitative Approach, 2nd Edition, Morgan Kanfmann, Publications 2006.

4. Kai Hwang F.A. Briggs, “Computer Architecture & Parallel Processing”, McGraw-Hill Book Company-Koga, 1985.

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12EMS332 ASIC DESIGN Subject Code 12EMS332 IA Marks 50 No. of Lecture Hours/Week 04 Exam Hours 03 Total No. of Lecture Hours 52 Exam Marks 100 Introduction: Full Custom with ASIC, semi-custom ASICS, standard cell based ASIC, gate array based ASIC, channeled gate array, channel less gate array, structured get array, programmable logic device, FPGA design flow, ASIC cell libraries data logic cells, data path elements, adders, multiplier, arithmetic operator, I/O cell, cell compilers . ASIC Library Design: Logical effort- practicing delay, logical area and logical efficiency logical paths, multi-stage cells, optimum delay, optimum no. of stages, library cell design. low-level design entry, schematic entry, hierarchical design, the cell library, names, schematic, icons & symbols, nets, schematic entry for ASIC’S, connections, vectored instances and buses, edit in place attributes, net list, screener, back annotation. Programmable ASIC: Programmable ASIC logic cell, ASIC I/O cell. Low Level Design Language: Introduction, EDIF, PLA tools, an introduction to CFI designs representation., half gate ASIC, introduction to synthesis and simulation, ASIC construction floor planning and placement and routing, physical design, CAD tools, system partitioning, estimating ASIC size, partitioning methods, floor planning tools, I/O and power planning, clock planning, placement algorithms, iterative placement improvement, time driven placement methods, physical design flow global routing, local routing, detail routing, special routing, circuit extraction and DRC. Note: All Designs are to be based on VHDL REFERENCE BOOKS 1. M.J.S.Smith,“Application - Specific Integrated Circuits”, Pearson Education,

2011. 2. Malcolm R.Haskard; Lan. C. May, “Analog VLSI Design - NMOS and CMOS”

Prentice Hall, 1998. 3. Jose E.France, Yannis Tsividis, “Design of Analog-Digital VLSI Circuits for

Telecommunication and Signal Processing”,2nd Edition. Prentice Hall, 1993. 4. Mohammed Ismail and Terri Fiez,“Analog VLSI Signal and Information

Processing”, McGraw Hill, 1994.

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12EMS333 TESTING AND VERIFICATION OF VLSI CIRCUI TS Subject Code 12EMS333 IA Marks 50


Total No. of Lecture Hours 52 Exam Marks 100 Scope of Testing and Verification : In VLSI design process, issues in test and verification of complex chips, embedded cores and SOCs. Fundamentals of VLSI Testing: Fault models, automatic test pattern generation, design for testability, scan design, test interface and boundary scan, system testing and test for SOCs, Iddq testing, delay fault testing, BIST for testing of logic and memories, test automation. Design Verification Techniques: Based on simulation, analytical and formal approaches, functional verification, timing verification, formal verification, basics of equivalence checking and model checking, hardware emulation. REFERENCE BOOKS 1. M. Bushnell and V. D. Agrawal, "Essentials of Electronic Testing for

Digital, Memory and Mixed-Signal VLSI Circuits", Kluwer Academic Publishers, 2000.

2. M. Abramovici, M. A. Breuer and A. D. Friedman, "Digital Systems Testing and Testable Design", IEEE Press, 1994.

3. T.Kropf, "Introduction to Formal Hardware Verification", 1st Edition, Springer Verlag, 2010.

4. P. Rashinkar, Paterson and L. Singh, "System-on-a-Chip Verification-Methodology and Techniques",Springer,1st Edition, 2000.

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