SYEN 3330 Digital Systems

SYEN 3330 Digital Systems Jung H. Kim Chapter 2-8 1

SYEN 3330 Digital Systems

Chapter 2 -Part 8

SYEN 3330 Digital Systems Chapter 2-8

Exclusive OR/ Exclusive NOR

The Exclusive OR (EXOR) function is an important Boolean function used extensively in logic circuits. Uses for the EXOR gate include:

1. Adders/subtractors 2. Parity Generators/Checkers 3. Signature analyzers 4. Pseudo-random sequence generators

Definitions

The EXclusive OR relation is defined as: xy = x'y + xy'

The EXclusive NOR relation, otherwise known as Equivalence is defined as: (xy)' = xy + x'y'


Tables for EXOR/ EXNOR

Operator Rules: EXOR EXNOR

x y xy x y (xy)' or xy

0 0 0 0 0 1 0 1 1 0 1 0 1 0 1 1 0 0 1 1 0 1 1 1

The Exclusive Or function means:

x OR y, but NOT BOTH

The Exclusive Nor function, denoted by the operator , is sometimes known as the "Equivalence" function. Why?


EXOR/EXNOR ExtensionsThe EXOR function can be extended to 3 or more variables. For more than 2 variables, it is called a modulo 2 sum (Mod 2 sum), not EXOR:

w(xy) = w(xy)' + w'(xy) = w(xy'+x'y)' + w'(xy'+x'y) = w[(xy')'(x'y)'] + w'xy' + w'x'y = w[(x'+y)(x+y')] + w'xy' + w'x'y = w[x'x+x'y'+xy+yy']+w'xy'+w'x'y = w[0+x'y'+xy+0]+w'xy'+w'x'y = wx'y'+wxy+w'xy'+w'x'y

These identities can be shown to hold:

x0 = x x1 = x' xx = 0 xx' = 1 xy' = (xy)' x'y = (xy)'

Further commutative and associative laws apply thus:

xy = yx (xy)z = x(yz) = xyz


EXOR Implementations

XY

X

Y

The simple SOP implementation uses the following structure:

A NAND only implementation is:


EXOR Implementations (Cont.)

The AND-OR implementation is simply a SOP form of the equation defining the EXOR function:

xy = x'y + xy'

The multiple level NAND implementation is a little more interesting. The last two stages implement the SOP form for:

xy = xT + yT where: T = (xy)' = (x'+y')

Substituting for T we get: xy = x(x'+y')+ y(x'+y') = xx' + xy' + x'y +yy' = 0 + xy' + x'y + 0 = xy' + x'y


Odd FunctionGoing back to 3-input Mod 2 Sum definition:

w(xy) = w(xy)' + w'(xy)

which becomes: (100) (111) (010) (001)

= wx'y'+wxy+w'xy'+w'x'y

We see that the function value is "1" for one, or three "ones" in the input variables.

This extends to an "N" input EXOR function which attains a value of "1" if and only if the number of ones in the input variable set is odd. Thus the Mod 2 Sum function is called the Odd Function.

Multiple input EXOR functions are difficult to implement in practice, so a multilevel tree structure is used to implement the function, using 2-input EXOR gates as blocks.


Odd Function Implementation

Three-Input Odd Function:

Four Input Odd Function:

These structures are also called parity trees, since the ODD Function is really a parity function.


K-Maps of ODD and EVEN

x

y

z

w

x

y

z

w

1

1

1

1

1

1 1

1

1

1

1

1

1 1

1 1

Odd Function Even Function

x

y

z

w

x

y

z

w

1

1

1

1

1

1 1

1

1

1

1

1

1 1

1 1

Odd Function of Five Bits

v=0 v=1

Note: n bit Odd or Even function, there will be (2**n)/2 or 2**(n-1) product terms of n variables (minterms)!


Parity Generators/Checkers

We can use a parity tree to generate parity which is then appended to the data

Example: Three-bit EVEN parity generator

3-Bit Parity Generator

X

Y

Z

P

We can use a 4-bit parity tree to check the codeword for correct parity. Here C=0 if the parity is correct as generated above, and C=1 if an error has occurred.

Example: Three-bit EVEN parity checker


Integrated Circuits

SSI -- Small Scale Integration -- gates, simple logic functions, and basic storage elements. (~10 gates)

MSI -- Medium Scale Integration -- tend to be simple functions that can be packaged in the 14 to 24 pin packages. (~10 to 100 gates)

LSI -- Large Scale Integration -- regular, programmable structures such as PAL, PROM, and PLD Devices, or custom devices. (~100 to a few 1000 gates)

VLSI -- Very Large Scale Integration -- tend to be custom microprocessors and regular memory components. (Many gates)


Digital Logic Families

Logic elements are constructed from various circuit components.

Based on physical characteristics, they are organized into families. Here are a few families:

RTL Resistor-Transistor Logic (old)

DTL Diode-Transistor Logic (old)

TTL Transistor-Transistor Logic

ECL Emitter Coupled Logic

MOS Metal Oxide Semiconductor

CMOS Complementary Metal-Oxide Semiconductor

Bi-CMOS

Bipolar Complementary Metal-Oxide Semiconductor


Compatibility

Logic device families have characteristics which are defined by some of the following parameters:

Fan-in -- the number of inputs available on a gate.

Fan-out -- the number of inputs the output of one gate can drive.

Logic Levels -- The signal values defining "1" and "0".

Propagation Delay -- The time for an input signal change to propagate to the output.

Noise Margin -- the amount of noise a logic signal will tolerate without error.

Power Supply -- the voltages required to allow the circuit to operate.

Power Dissipation -- the amount of power a circuit consumes.


Propagation Delay

Propagation delay is the time for a change in the input of a gate to propagate to the output.

Delay is usually measured from the 50% of logic level voltage reference points.

High-to-low (tPHL) and low-to-high (tPLH) output signal changes may have different propagation delays.

High-to-low (tPHL) and low-to-high (tPLH) propagation delays are measured on output transitions.

A "0" to "1" input transition causes a "1" to "0" output transition if the gate inverts, and a "0" to "1" output transition if the gate does not invert.


Propagation Delay Example

In A

B

TPLH

TPLH

TPHL

TPHL A

B

In

What is the delay for: a string of inverters?

a string of buffers?


Positive and Negative Logic

The same physical gate can have different logical meanings depending on how we interpret the signal levels.

Positive Logic Logic 1 is set to high (more positive) signal levels Logic 0 is set to low (less positive) signal levels

Negative Logic Logic 1 is set to low (more negative) signal levels Logic 0 is set to high (less negative) signal levels

A gate which implements a Positive Logic AND function will implement a Negative Logic OR function.


Positive and Negative Logic

Given this signal level table: InputX Y

Output

L L LL H HH L HH H H

What logic function is implemented?

Positive Logic

(H = 1) (L = 0)

Negative Logic

(H = 0) (L = 1)

0 0 0 1 1 1 0 1 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 0


Positive and Negative Logic (Cont.)

Rearranging the negative logic terms to be in proper function table order we get:

Positive Logic

(H = 1) (L = 0)

Negative Logic

(H = 0) (L = 1)

0 0 0 0 0 0

0 1 1 0 1 0

1 0 1 1 0 0

1 1 1 1 1 1

Positive logic "OR", Negative Logic "AND"


Logic Conventions

Symbols:

X

YZ

CKT

Positive LogicNegative Logic

X

YZ

X

YZ

Logic Circuit

X

LLHH

Y

LHLH

Z

LHHH

SYEN 3330 Digital Systems

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