Switching Energy in CMOS Logic: How far are we from ... Reliability of CMOS Inverter Operation V min

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Transcript of Switching Energy in CMOS Logic: How far are we from ... Reliability of CMOS Inverter Operation V min

  • Switching Energy in CMOS Logic: How far are we from physical limit?

    Saibal Mukhopadhyay Arijit Raychowdhury

    Professor: Kaushik Roy Dept. of Electrical & Computer Engineering

    Purdue University

    Network for Computational Nanotechnology

    NRLNRL NANOELECTRONICSNANOELECTRONICS RESEARCH LABRESEARCH LAB

  • 2

    Outline • Switching energy in charge transfer based

    Digital Logic – Basics and Physical Limits

    • Practical consideration for switching energy in CMOS Logic – Static requirements – Dynamic requirements – System considerations

    • What can we do to reduce switching energy ? • Summary

  • 3

    Charge Based Digital Logic

    Key principles in the charge based digital logic 1. Representation of digital states

    Logic “0”: No Charge in the capacitor Logic “1”: Charge stored in the capacitor

    2. Change of digital state Charge/dis-charge capacitor through a resistor

    =out QV C

    + – C

    Ron Vmin

    “0”

    “1”

    Vmin

    Time

    V o

    lt ag

    e

  • 4

    Switching Energy

    + – C

    Ron Vmin

    = = =

    = = =

    ∴ → = − =

    ∫ ∫

    ∫ ∫

    2 min min 0 min0 0

    2 0 0 0 min0 0

    2 min

    ( )

    1 ( ) ( )

    2 1

    (0 1) 2

    DD

    DD

    V Total DD

    V Cap C

    diss Total Cap

    E i t V dt CV dv CV

    E i t v t dt Cv dv CV

    E E E CV

    ( )DDi t

    =( ) oC dv

    i t C dt

    “0”

    “1”

    Vmin

    Time

    V o

    lt ag

    e Switching energy can be minimized by

    reducing Q and/or Vmin

    = =

    2 min

    min dissE CV

    QV

  • 5

    Physical Medium for Computation: Barrier Model

    Eb

    V=Vmin=Ebmin

    V=0

    Tox

    SOURCE DRAIN

    Leff

    GATE

    Vg

    Vd

  • 6

    Minimum Barrier Height: Zhirnov’s Model

    Lch Eb

    ( ) 10

    ~ exp 1 ch

    err b B b B err

    For L nm

    P E k T E k Tln P

    >

    − => =   

    _ _

    _ _ err err cl err QM

    err cl err QM

    P P P

    P P

    = +

    Minimum barrier height = Ebmin ~ kBTln(2)

    Channel Length (Lch) [nm]

    M in

    b ar

    ri er

    h ei

    g h

    t (E

    b )

    in k

    B T

    Lch=32nm Lgate = 45nm

  • 7

    Minimum Operating Voltage and Switching Energy

    Eb

    V=Vmin=Ebmin

    V=0

    • Minimum operating voltage Vmin ~ kBTln(2)

    • Minimum switching energy Ediss= QminVmin=qkBTln(2) ~ 0.7kBT

    Switching energy for an minimum sized inverter designed using in 45nm gate length devices ~

    35000kBT

    Why are we so far from the limit?

  • 1. Can we operate with Vmin ~ KBTln2 ?

    2. Can we operate with Qmin = q ?

  • 9

    Outline • Switching energy in charge transfer based

    Digital Logic – Basics and Physical Limits

    • Practical consideration for switching energy in CMOS Logic – Static requirements – Dynamic requirements – Circuit/System considerations

    • What can we do to reduce switching energy ? • Summary

  • 10

    Reliability of Circuit Operation In

    p u

    ts

    O u

    tp u

    ts

    # of devices = Ndev Prob. of error of a single gate = Perr Prob. of error of the circuit = Pcirc = 1 – (1-Perr)Ndev

    Reliable operation of the circuit imposes stronger constraint on the reliability of the gate operation

    Circuit failure prob [%]

    G at

    e fa

    ilu re

    p ro

    b ab

    ili ty

    Perr ~5x10-12

    Ndev~100million

    Ndev~300million

    Ndev~500million

  • 11

    Reliable Operation for a Device

    • Reliable operation requires a higher barrier – Perr = 0.5

    => Eb= 0.7kBT – Perr = 5x10-12

    => Eb= 25kBT

    • 0.1% failure rate for a circuit of 300 million devices => Vmin~25kBT

    Eb=25kBT

    Perr ~ 5x10-12 B

    ar ri

    er H

    ei g

    h t

    in k

    B T

    Device error probability (Perr)

    kBTln(2) 25kBTReliability

    Lgate=45nm Lch=32nm

  • 12

    CMOS Logic: Physical Model

    CMOS logic operates based on presence or absence of charge and not on localization of charge

    VDD

    Vin Vo

    “0” ≡ 0V“1” ≡ VDD

    “1” ≡ VDD“0” ≡ 0V

    VoutVin

  • 13

    Operation of MOS Device

    V=VDD=EbOFF – EbON

    EbON

    EbOFF

    V=0

    onB DD

    off

    pk T V ln

    q p η

      =   

     

    Operation with a larger pon/poff requires a higher supply voltage

    Vg

    Csemi

    Cox

    1 semi oxC Cη = +

  • 14

    Operation of CMOS Logic

    ( )( ) ( )

    0

    0

    1 0.5 0.5

    1 DD BonB B

    in off B

    exp q V V k Tpk T k T V ln ln

    q p q exp qV k T η η

       − − −  = × + ×    − −   

    VDD

    Vin Vo

    VIL VIH VOL

    VOH NML = VIL-VOL NMH = VOH-VIH

    Av= Max gain

    V in =V

    o

  • 15

    Operation of CMOS Logic

    Higher pon/poff improves maximum gain and noise margin

    100on off

    p p

    =

    10on off

    p p

    =

    4on off

    p p

    =

    2on off

    p p

    =

  • 16

    Operation of CMOS Logic

    “1” Vol

    “0” Voh

    ?

    2n+1 stages

    DD

    DD v

    2n+1 2n+1 DD v

    O DD

    O

    Vin = V 2-

    Vo(1) = Vin(2) = V 2 + A

    Vo(2n+1) = V 2- (-1)

    1, , V V 2

    1, , V v

    v OH

    A

    if A as n

    if A as n V

    < → ∞ →

    > → ∞ →

    M

    Vin

    V o

    u t

  • 17

    Operation of CMOS Logic

    distinguishability => Gain (AV) > 1

    for CMOS inverter Minimum pon/poff

    is “4” and

    not “2”

    AV=1

    pon/poff=4

    ( )

    ( ) ( )

    2 1

    2 2

    B DD v

    min B

    k T V ln A

    q

    V k T q ln

    η= +

    => =

    Vmin= kBTln(2) Vmin= 2kBTln(2)Device to Inverter

  • 18

    Operation of CMOS Logic

    To prevent spontaneous change of state noise margin needs to be at least higher than kBT

    => VDD > 3kBT

    supply voltage in kBT (VDD/kBT)

    N o

    is e

    m ar

    g in

    in k

    B T

    (N M

    /k B T

    )

  • 19

    Reliability of Circuit Operation In

    p u

    ts

    O u

    tp u

    ts

    # of gates = Ngate Prob. of error of a single gate = Perr Prob. of error of the circuit = Pcirc = 1 – (1-Perr)Ndev

    Reliable operation of the circuit imposes stronger constraint on the reliability of the gate operation

    Circuit failure prob [%]

    G at

    e fa

    ilu re

    p ro

    b ab

    ili ty

    Perr ~5x10-12

    Ngate~100million

    Ngate~300million

    Ngate~500million

  • 20

    Std. dev of noise voltage [mV]

    N o

    is e

    M ar

    g in

    in k

    B T

    Perr~5x10-12

    Perr~5x10-10

    Perr~5x10-8

    Reliability of CMOS Inverter Operation

    NMNM

    σN

    Vnoise

    Higher noise requires a larger noise margin for reliable operation

  • 21

    supply voltage in kBT (VDD/kBT)

    N o

    is e

    m ar

    g in

    in k

    B T

    (N M

    /k B T

    )

    ~10kBT

    ~13kBT

    Reliability of CMOS Inverter Operation

    Vmin= 2kBTln(2) Vmin= 10kBTReliability

  • Operations of CMOS Logic

    1. It is a “single well - double barrier” system.

    2. Presence or absence of charge at the “well” determines the logic state

    3. At both logic states, the well is strongly coupled to VDD or GND through a “on” device

    The “driven” nature of CMOS logic makes it reliable even at very low voltage operation

  • 23

    Limit of poff : Leakage Power

    EbOFF ~ 11kBT helps to meet a leakage requirement of 1nA/µm

    Lch EbOFF

    0 0exp bOFF

    leak off B

    E I I I p

    k T  

    = − =   

    1mA/µm 0.1mA/µm

    1nA/µm

    Vgs

    Vt VDD

    Ids

    ( ) 5

    5

    ~ 1 / ~ 10

    10 ~ 11

    leak off

    bOFF B B

    I nA m p

    E k T ln k T

    µ −⇒

    ⇒ = ×

  • 24

    Outline • Switching energy in charge transfer based

    Digital Logic – Basics and Physical Limits

    • Practical consideration for switching energy in CMOS Logic – Static requirements – Dynamic requirements – Circuit/System considerations

    • What can we do to reduce switching ene