Outline Packet switching paradigms Bridges and extended LANs Cell switching Switching hardware.
Switching activity
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06/18/2022 1 Now we have understood, For any signal to be considered as logic ‘0’ and logic ‘1’, it should be in the NM L and NM H ranges, respectively
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https://www.udemy.com/vlsi-academy http://vlsisystemdesign.com/switchAct.php A CMOS, is basically an inverter logic (NOT gate), that consists of a PMOS at the top, and NMOS at the bottom (as shown in figure below), whose 'gate' and 'drain' terminal are tied together. The 'gate' terminals of both the MOS transistors is the input side of an inverter, whereas, the 'drain' terminals form the output side.
Transcript of Switching activity
04/11/2023 1
Now we have understood, For any signal to be considered as logic ‘0’ and logic ‘1’, it should be in the NML and NMH ranges, respectively
04/11/2023 2
Now we have understood, For any signal to be considered as logic ‘0’ and logic ‘1’, it should be in the NML and NMH ranges, respectively
Now, let us understand the factors affecting the voltage levels to vary from this range
Switching Activity of a Device is one of the factors which affects the voltage levels of Input/Output signals
Ideal Switching
Activity
ActualSwitching
Activity
In Out
Vdd
Vss
PMOS – P Diff
NMOS – N Diff
Poly Gate
Lets understand the internal process while Switching Activity happens in a Device
In Out
Vdd
Vss
PMOS – P Diff
NMOS – N Diff
Poly Gate
PMOS NMOSConsider the MOS device, to understand the actual scenario
PMOS NMOS
Let’s revise MOS device characteristics
MOS device characteristics
MOS device characteristics
MOS device characteristics
MOS device characteristics
MOS device characteristics
MOS device characteristics
MOS device characteristics
MOS device characteristics
MOS device characteristics
MOS device characteristics
NMOSS D
G
Vgs
MOS device characteristics
Vgs is the Voltage between gate and source
NMOSS D
G
Vgs
MOS device characteristics
NMOSS D
G
Vgs
Vgs < VT (Threshold Voltage)
S D
MOS device characteristics
If Vgs is less then VT , the NMOS will act as Open Switch
NMOSS D
G
Vgs
Vgs > VT (Threshold Voltage)
S D
MOS device characteristics
If Vgs is greater then VT , the NMOS will act as Closed Switch
NMOSS D
G
Vgs
S D
Vgs > VT
MOS device characteristics
NMOSS D
G
Vgs
S D
Vgs > VT
When MOSFET is ‘ON’, it can be modeled as a ‘Resistor’ with switch closed
MOS device characteristics
NMOSS D
G
Vgs
S D
Vgs > VT
When MOSFET is ‘ON’, it can be modeled as a ‘Resistor’ with switch closed
When MOSFET is ‘OFF’, it can be modeled as an ‘open switch’
MOS device characteristics
When MOSFET is ‘ON’, it can be modeled as a ‘Resistor’ with closed switch
When MOSFET is ‘ON’, it can be modeled as a ‘Resistor’ with switch closed
PMOS acts as Logic ‘0’ NMOS acts as Logic ‘1’
When MOSFET is ‘ON’, it can be modeled as a ‘Resistor’ with switch closed
When MOSFET is ‘OFF’, it can be modeled as an ‘open switch’
PMOS acts as Logic ‘0’ NMOS acts as Logic ‘1’
When MOSFET is ‘ON’, it can be modeled as a ‘Resistor’ with switch closed
When MOSFET is ‘OFF’, it can be modeled as an ‘open switch’
PMOS NMOS
PMOS acts as Logic ‘0’ NMOS acts as Logic ‘1’
PMOS acts as Logic ‘1’ NMOS acts as Logic ‘0’
In Out
Vdd
Vss
Input Switching from logic ‘1’ to logic ‘0’
In Out
Vdd
Vss
Input Switching from logic ‘1’ to logic ‘0’
NMOS is turning ‘OFF’
In Out
Vdd
Vss
Input Switching from logic ‘1’ to logic ‘0’
NMOS is turning ‘OFF’
PMOS is turning ‘ON’
Input Switching from logic ‘1’ to logic ‘0’
Input Switching from logic ‘1’ to logic ‘0’
NMOS is turning ‘OFF’
Input Switching from logic ‘1’ to logic ‘0’
NMOS is turning ‘OFF’
PMOS is turning ‘ON’
Input Switching from logic ‘1’ to logic ‘0’
NMOS is turning ‘OFF’
PMOS is turning ‘ON’
In Out
Vdd
Vss
Input Switching from logic ‘1’ to logic ‘0’
NMOS is turning ‘OFF’
PMOS is turning ‘ON’
In Out
Vdd
Vss
Out
Vdd
Vss
R
Replace PMOS as resistor and NMOS by open switch.
Input Switching from logic ‘1’ to logic ‘0’
NMOS is turning ‘OFF’
PMOS is turning ‘ON’
Out
Vdd
Vss
R
Out
Vdd
Vss
R
CL
Connect Capacitor on output end.
Input Switching from logic ‘1’ to logic ‘0’
NMOS is turning ‘OFF’
PMOS is turning ‘ON’
Out
Vdd
Vss
R
CL
Consider Capacitor is charged when Vdd is applied.
Input Switching from logic ‘1’ to logic ‘0’
NMOS is turning ‘OFF’
PMOS is turning ‘ON’
Out
Vdd
Vss
R
CL
Consider Capacitor is charged up to Vdd
Input Switching from logic ‘1’ to logic ‘0’
NMOS is turning ‘OFF’
PMOS is turning ‘ON’
Out
Vdd
Vss
R
CL
Summary
Out
Vdd
Vss
R
CL
In Out
Vdd
Vss
Summary
Out
Vdd
Vss
R
CL
Lets convert the area within dotted lines into closed loop circuit.
Summary
Out
Vdd
Vss
R
CL
CL
R
Vdd
Lets convert into closed loop circuit.
Summary
Out
Vdd
Vss
R
CL
CL
R
Vdd
Lets convert into closed loop circuit.
Summary
Capacitor Models
CL
R
Vdd
Summary
Capacitor Models
Uncharged Cap
Charged Cap
Fully Charged Cap
+-
+-
+-
0V
VO
Open circuit
short
+-
VO
CL
R
Vdd
Summary
CL
R
Vdd
Waveforms
Summary
CL
R
Vdd
Vdd
Waveforms
Summary
CL
R
Vdd
Waveforms
Vdd
VCL
Summary
CL
R
Vdd
Waveforms
Vdd
VCL
VR
Summary
CL
R
Vdd
Waveforms
Vdd
VCL
VR
I = V/R
Summary
CL
R
Vdd
Vdd
VCL
VR
I = V/R
IR
Waveforms
Summary
CL
R
Vdd
Vdd
VCL
VR
I = V/R
IR
Ipeak
Waveforms
So what can we conclude!!!
So what can we conclude!!!
A capacitor needs at least Ipeak amount of current
So what can we conclude!!!
A capacitor needs at least Ipeak amount of current
IR
Ipeak
So what can we conclude!!!
A capacitor needs at least Ipeak amount of current
IR
Ipeak
To get charged upto Vdd voltage
So what can we conclude!!!
A capacitor needs at least Ipeak amount of current
IR
Ipeak
To get charged upto Vdd voltage
VCL
So what can we conclude!!!
A capacitor needs at least Ipeak amount of current
IR
Ipeak
To get charged upto Vdd voltage
VCL
And, the output of inverter, is recognized as logic ‘1’
So what can we conclude!!!
A capacitor needs at least Ipeak amount of current
IR
Ipeak
To get charged upto Vdd voltage
VCL
And, the output of inverter, is recognized as logic ‘1’
And, the output of inverter, is recognized as logic ‘1’
And, the output of inverter, is recognised as logic ‘1’
What does this mean????
And, the output of inverter, is recognised as logic ‘1’
What does this mean????
It means that the voltage across capacitor
VCL
Vpeak
And, the output of inverter, is recognised as logic ‘1’
What does this mean????
It means that the voltage across capacitor
VCL
Vpeak
Lies in NMH level of noise margin graph
Vdd
0
VOH
VIH
VOL
VIL
NMHNoise Margin High
NMLNoise Margin High
NMH = VOH - VIH
NML = VIL - VOL
Why to do?
04/11/2023 65
