Sw module user files OrCad 9.2 in Sulautetut. Start Cadence PSD 14.0 Capture Schematics, logical...

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sw module user files Cad 9.2 in Sulautetut

Transcript of Sw module user files OrCad 9.2 in Sulautetut. Start Cadence PSD 14.0 Capture Schematics, logical...

sw module

user

files

OrCad 9.2 in Sulautetut

Start Cadence PSD 14.0 Capture

Schematics, logical connections

File Open Project h8s_eval.opj Open

Example H8S_evalBoard.zip can be downloaded from :http://www.ee.oulu.fi/~terva/Embedded2003/bulletin.php

Link to HW manual of the MCU is at:http://www.ee.oulu.fi/~hannu/Embedded2003/mcus.php

File Save As name.opj Save As

change the name of the project.

Capture

Microcontroller H8S2128

Offpage connector

Design pages

Overview

VCC (+5v)

GND (0v)

Library of symbols

Place a part

Place Part in the Libraries field, select Sulautetut2 ,in the Part List field, select DB9S ,then Click OK .

To rotate a part :Select a part (left click on the part) ,CTRL-R .

Place a wire

Place Wire ,Use the mouse to draw the wire.

Place an offpage connector

to connect 2 pins that are on different design pages,

! Give the same name on each of the pages, for one connection.

e.g a DB9 connector (for serial communication)

Toolbar for wires, parts,

GND, VCC,

offpage connectors ...

Design Rule check : unconnected nets, off-page connectors

Tools Design Rule Check

Nota: menu Tools is visible only when a design page is selected.

Create a netlist (.MNL)

Tools Create Netlist Check the report messages in the Session Log window.

Automaticupdate CaptureLayout

Layout

Pad :

Copper(kupari)

Copper

Insulation(eristys)

Hole(reikä)

if copper on the interior of this cylinder : pad is also via

Top layer

Bottom layer

Bottom/Top layer view

Footprint : padstack(s) + obstacle(s)

Padstack : list ofthose dimensions forone pad.

(the current flows between layers).

Start Cadence PSD 14.0 Layout

• File New Default.tch / Metric.tch (inches/mm).

• then automatically, Layout asks the netlist file (.MNL) ,

• next the name of the main output file (.MAX)

• next the footprints of the components. .../...

Use the library EVALBOARD.LLB for the main components;some footprints are missing, like the crystal resonator (Takee.g., a capa footprint. The crystal is not needed when usingthe emulator).

EVALBOARDlibrary

Link footprints

System settings : units

Options System Settings

Spacing between items: used as routing rules.

Options Global Spacing

Layers : 3 layers of interest

Tools Layers Select from Spreadsheet

Nets selections/settings :

Tools Nets Select from Spreadsheet

allows modifying the properties.

Select one or several net names ,and a pop-up menu (right click)

Create the board outline (ToolObstacleSelect Tool)

Place components (footprints)

Route those nets (e.g. autoroute)

NoteOnline DRC OFF

NoteOnline DRC ON

Check out statistics of unrouted nets

Enable a modular group of nets (e.g LCD_Connec)

Cleanup design/Design Rule Check

Run Post Processorname.bot, name.top, thruhole.tap

For all modules

Create Reports

Check statistics of unrouted nets :

• Auto Design Rule Check Select All, and Check Detail Obstacle.

Cleanup design/Design Rule Check :• Auto Cleanup Design

Select All, and Check Detail Obstacle.

• Auto Refresh Calculate StatisticsCheck out the unrouted nets section.

Create Reports :

• Auto Create reportsCheck the ”Conns Unrouted” box.

in order to see the location of unrouted nets.

Autorouting/Manual Route : • Auto AutoRoute Board : autorouting

• Tool Track Select Tool , then use the mouse and right button (select Finish in the pop-up to terminate a track).

• More detailed description of the previous steps :http://www.ee.oulu.fi/~terva/Embedded2003/bulletin.phpon ”Intro to Orcad” link.

• Re-use the proposed example, the pad-to-pad spacing, and other properties/settings have been tested.

• The design is quite simple : two layers TOP and BOT.

THRUHOLE.TAP contains drilling properties/settings.

• Even better description in the tutorial/help provided in the software.

Obstacle

Via

Texton toplayer