Supporting Systolic and Memory Communication in iWarp

CS258 Paper SummaryComputer ScienceJaein Jeong

Systolic array architectureReplacing a processing element (PE) with an array of PE’s without increasing I/O bandwidth

Memory

PE

Memory

PE

PE

PE

PE

PE

Conventional

Systolic

Two communication styles

CPU

Local

Mem

CPU

Local

Mem

CPU

Local

Mem

CPU

Local

Mem

CPU

Local

Mem

CPU

Local

Mem

Systolic Communication:A CPU directly communicates through queues

Memory Communication:Communication goes through local memory

Memory communication

Pros

Cons

Application doesn’t need to know memory access detail.

Data can be accessed randomly.

Communication takes memory bandwidth

Long communication latency

Systolic Communication

Advantages

Disadvantages

Fine grain communication due to reduced latency.

Reduced local memory access Reduced size for local memory Increased instruction-level parallelism

Hard to use – messages are accessed sequentially

Messages can’t be retransmitted

iWarp communication

Program access to communication Supports Systolic communication Speeds up memory communication

(Messages are transferred between user spaces) A processor can alter a route and forward data

to another processor without buffering.

Logical channels Higher degree of connectivity by mapping

multiple alogical channels over physical channels.

Guarantees communication bandwidth by time multiplexing logical channels.

Logical Channels

Logical channels are mapped over physical buses using queues.Once logical channelsare allocated, data is transmitted over the channels.To prevent sending data to full queue, a sender counts free slots of receiver queue.

CommunicationAgent

ComputationAgent Me-

moryAgent

Two types of logical channels

Reservation pool (implememted by pathway) For transporting data for a long period of time. A pathway is built and dismantled using special

messages (pathway begin marker, end marker) Each cell routes a message either by forwarding it

to its neighbor or receiving it.

Open pool For message passing of short period, No pathway

Data and Control interface within a iWarp processor

Data interface b/w comp and comm Reads/writes to gates access queues which are

bound to corresponding logical channels.

Data interface to memory FIFO like spooling gates are mapped between

mem and comm or comp. Memory can be used for extension of msg

queue.

Control interface b/w comp and comm Comp => comm : stores info in comm’s CAM. Comm => comp : sets status register