Superconducting Microelectronics for Next-Generation Computing · 2020. 1. 25. · Contrast to 90nm...

Superconducting Microelectronics forNext-Generation Computing

Leonard M. Johnson

2018 MIT Research and Development Conference

14 November 2018

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This research was funded by the Office of the Director of National Intelligence (ODNI), Intelligence Advanced Research Projects Activity (IARPA) under Air Force Contract No. FA8721-05-C-0002. The views and conclusions contained herein are those of the authors and should not be interpreted as necessarily representing the official policies or endorsements, either expressed or implied, of ODNI, IARPA, or the US Government.

© 2018 Massachusetts Institute of Technology.

Delivered to the U.S. Government with Unlimited Rights, as defined in DFARS Part 252.227-7013 or 7014 (Feb 2014). Notwithstanding any copyright notice, U.S. Government rights in this work are defined by DFARS 252.227-7013 or DFARS 252.227-7014 as detailed above. Use of this work other than as specifically authorized by the U.S. Government may violate any copyrights that exist in this work.

Superconducting Elec - 2L. M. Johnson 11/14/2018

Computing Development Timeline

ENIAC First fully transistor-based computer: TX-0

Transistor invented

4.5M transistors: Pentium

30k transistors: i8088

19.2B transistors: 32-core Epyc GPU

Triode vacuumtube invented

Vacuum tubes

*RSFQ: Rapid Single Flux Quantum**AQFP: Adiabatic Quantum Flux Parametron

1907 1946 20171971

Discrete transistors

Bipolar transistorintegrated circuits

CMOSintegrated circuits


Computing Development Timeline

ENIAC First fully transistor-based computer: TX-0

Transistor invented

4.5M transistors: Pentium

30k transistors: i8088

19.2B transistors: 32-core Epyc CPU

Triode vacuumtube invented

Vacuum tubes

Cryotron AQFP** CircuitsIBM Latching Logic RSFQ* Circuits AC-Clocking

*RSFQ: Rapid Single Flux Quantum**AQFP: Adiabatic Quantum Flux Parametron

1907 1946 20171971


Computing Application Space

Titan Supercomputer at ORNL

Centralized ComputingWearables / Implants

Facebook Data Center

Low Power, Limited Processing High Power, Massive Processing

Personal Computing


High Performance Computing (HPC)Energy Consumption Limitations

• Exascale computer projected to consume ~100 MW with existing approaches– ~1 B kW-h / year– ~$50M / year for electricity

• DOE and IARPA charged with realizing aggressive exascale computing power consumption goals

HPC Energy Consumption Trends

1 10 100 10001

10

100

1000

10 best supercomputers (without cooling)

Pow

er c

onsu

mpt

ion

(MW

)

Supercomputer performance (Peta FLOPS)

2 GFLOPS/W

att

DOE TargetTianhe-2

Titan/Sequoia

Mirra

K-Computer

IARPA Target

14GFLOPS/W

att

SunwayTiahu Light

Summit


• Introduction to Superconducting Electronics• Technology Development for Digital Computing• Additional Applications

Outline


• Superconductivity

– Zero dc electric resistance at T < Tc

• Cryotron

– Developed at MIT Lincoln Laboratory by Dudley Allen

Buck in 1950s

– Information encoded in the superconducting and

normal states of a wire

– Tantalum wire with wound copper heater

– Achieved 5-ms switching

– Spawned research efforts at IBM, RCA, and GE

– Speed and power never outperformed transistors

and efforts were abandoned

Vacuum

tube

Cryotron

Transistor

First Superconducting Device - Cryotron

S→N

I

V

Ic

‘1’

‘0’

T >Tc

I-V Curve for Superconducting Wire


• Josephson tunneling and Josephson junction – Superconductor-Insulator-Superconductor

• Josephson Tunneling Logic– Information encoded in the normal and

superconducting states of the JJ– Ultrafast, ~ 1 ps S → N switching by current I > Ic– Slow, ~ 1 ns N → S switching back– ~100 person effort at IBM from 1970 to 1982– No path identified to outperform transistors

I

JJ - a “weak link” between two superconductors

S1

S2

~ 1-nm-thickinsulator

Josephson Junction (JJ)

Computing with Superconductivity - Josephson Tunneling Logic

S→N

I

V

Ic

‘1’

‘0’

~2.5 mV

I-V Characteristics of Josephson junction


• Flux in a superconducting loop is quantized– Φ = nΦ0, Φ0 - magnetic flux quantum

• Addition of Josephson junction (JJ) in superconducting loop allows switching– Generates a quantized Single Flux Quantum (SFQ)

voltage pulse

• Ultrafast switch is made from shunted JJ – Voltage waveform at I > Ic: periodic ~ 1-ps pulses

• Ultralow switching energy of ~10-19 J

• Single Flux Quantum (SFQ) logic/memory– Proposed in 1985; thousands of circuits demonstrated – DC bias (early versions), synchronous / asynchronous

clocking– Recent SFQ logic families nearly eliminate DC bias

power

S

JJ

B

IsΦe

Persistent current Φ

Φ = nΦ0

Computing with SuperconductivitySingle Flux Quantum, 1985 - Present

RshN

I

V

IcS

time

Ib

JJ

Resistively Shunted Josephson Junction (JJ)

Josephson Junction in Superconducting Loop


0.1 1 10 100 100010-23

10-22

10-21

10-20

10-19

10-18

10-17

10-16

10-15

ERSFQ RQL

STT/DW

NML

STTtriadSTM G

SpinFE TGpnJ

gnrTFET

HJTFETIIIvTFE T

CMOS LP0.3V InAs

Sw

itchi

ng e

ner

gy, D

E (J

)

Delay, t (ps)

CMOS HP

AQFP

kBT ln2 @ 4.2 K

nSQUID

Quantum 'limit', DEt = h

STOlogic

SWD

Spin-basedTFETs

Landauer’s thermodynamic limit, !"#$%&

AdiabaticSuperconducting

SwitchingSuperconducting

STT/DW

SWD

SpinFET

CMOSHigh Power

Ultralow Logic Energy and High Speed

SCE as Candidate for a Beyond CMOS TechnologySw

itchi

ng E

nerg

y(J

) CMOSLow Power0.3V InAs

~ 1 ps

Speed of light

• Superconductive transmission lines provide lossless on-chip data transmission– Preserves ~1 ps SFQ pulses (no

dispersion)

• Solution to high energy overhead of data movement in conventional processors

Lossless Data Transmission


The Fastest Digital Technology

SUNY Stony Brook 0.3-µm, 140 kA/cm2, CMP Nb Josephson fabrication process

• Clock speed of SFQ circuits increases as (Jc/Cs)1/2

• Early SFQ development emphasized high-speed

demonstration of small-scale circuits

• 770 GHz maximum frequency of operation of SFQ

static frequency dividers (T Flip-Flop) was

demonstrated at Stony Brook University ~ 20 years

ago

1 10 100

200

400

600

800

1000AB limit

Pair breaking in Nb wiring f

2D

Max

imum

TFF

Div

ider

Fre

quen

cy (G

Hz)

Josephson Junction Critical Current Density (kA/cm2)

HYPRES HYPRES+SUNY SB NGST SUNY SB plasma frequency f

p

MIT LL



Outline


1990 1995 2000 2005 2010 2015 2020102

103

104

105

106

107

HYPRES NEC-ISTEC ISTEC-AIST D-Wave Systems

Num

ber J

Js in

ope

ratio

nal S

CE c

ircui

ts

Year

doubling every 4.5 ye

ars

Superconducting Electronic (SCE) Circuit Trends(pre 2011)

SFQ Circuit Level of Integration pre 2011Issues Contributing to 20,000 JJ limit

• Primary focus on high-clock-speed circuit demonstrations, not larger-scale circuits

• RSFQ circuit design limitations – Parallel current biasing: Ib ∝ number of JJs– Required dc bias current of over 2 A into

small chips– Relatively large bias currents cause spurious

magnetic fields that interfere with the SFQ pulse propagation

• Unsophisticated circuit design tools• Outdated fabrication equipment

Doubling every 4.5 years


SFQ Logic Families

(1)I+

(2)Q

I(3)

(4)

Adiabatic Quantum Flux Parametron(AQFP)

Energy-Efficient RSFQ(ERSFQ)

• Developed by Hypres, Inc.• Eliminates resistor-based bias network

Reciprocal Quantum Logic(RQL)

• Developed by Northrop Grumman• Based on AC biasing


Nominal Energy per Operation for Beyond-CMOS Technologies

Device Type Nominal Device Energy (aJ)

Interconnect Factor

Cooling Factor

Computation Energy per

Operation (aJ)

HP CMOS 18 100x 1.5x 2700

LP CMOS0.3-V InAs 3.3 100x 1.5x 500

Tunneling FETs 1.5 100x 1.5x 220

Switching SFQ@ 4 K 0.1 1x 500x 50

AQFP @ 4 K 0.01 1x 500x 5

Nearly reversible@ 4 K 0.001 1x 500x 0.5

Superconducting electronics offers orders of magnitude reduction in energy consumption, even with requirement to cool to 4 K temperature

Advanced Semiconductor Technologies

Superconducting Technologies

Commercial State-of-the-Art

~10x improvement

~500x improvement

Today


State-of-the-Art Superconducting Circuit Fabrication

Wafer sizeNumber of Nb layersPlanarizationMin wiring feature sizeMin JJ sizeIntegration scale

HYPRES 4-Layer Process (USA) AIST 10-Nb-Layer (Japan)

75 mm9 and 10

Partial planarization~ 1 μm

~ 1.2 μm80k JJs

*AIST: National Institute of Advanced Industrial Science and Technology, Japan

MIT LL 8-Nb-Layer Process

200 mm8 and 9

Full planarization350 nm700 nm

810k JJs

1 μm

150 mm4

No planarization~ 1 μm

~ 1.5 μm11k JJs

D-Wave Systems 6-Nb-Layer

200 mm6

Full planarization250 nm600 nm

128k JJs


Contrast to 90nm FDSOI CMOS Fabrication Process

90-nm FDSOI CMOS Cross Section

PassiveWiring Layers

Interconnect, vias,inductors

Active LayersTransistors,capacitors, resistors

SFQ circuit performance is much more dependent on process control than CMOS circuits

Superconducting Electronics Cross Section


interconnect, vias, inductors

Active Layers JJs, resistors

• CMOS is tolerant of process variability: >10%

• Planarization of metal layers is primarily done for patterning (DOF)

• Thickness between metals can vary up to 10% across wafer with minimal electrical impact (R, C)

• SFQ allowed variability is much less – Active devices: < 1%– Inductors (wires): < 5%– Dielectric thickness: < 10%

• Critical parameters: device area, tunnel barrier uniformity


Contrast to 90nm FDSOI CMOS Fabrication Process

90-nm FDSOI CMOS Cross Section


Interconnect, vias,inductors

Active LayersTransistors,capacitors, resistors

Both SFQ and CMOS active devices rely on well-controlled, sub-nm-scale oxide layers

Superconducting Electronics Cross Section


interconnect, vias, inductors

Active Layers JJs, resistors

Gate length = 90 nmGate oxide thickness = 1.8 nm

FDSOI transistor

Josephson Junction

JJ diameter = 500 nmJJ oxide

thickness = 1 nm

• Substrate: 200mm Si wafer• Wire layers: AlCu, TiN, Ti, W• Inter-metal dielectric: PECVD SiO2 at 400°C• Device active layers: HfO2, Si3N4, SiOxNy, polysilicon,

CoSi2

• Substrate: 200mm Si wafer• Wire layers: Nb, MoNx, NbTiNx• Inter-metal dielectric: PECVD SiO2 at 150°C• Device active layers: Nb/AlOx/Al/Nb• Resistors: Ti/Mo, Ti/MoNx


9-chip Multi-Chip Module32 mm x 32 mm

Northrop Grumman and Hypres Circuit DesignsFabricated in MIT LL Process (IARPA C3 Program)

ERSFQ 32-bit slice of Register with Decoder

• Access time: 100 ps

ERSFQ 8-bit ALU • JJ count: 7200• Clock: 10 GHz

RQL 8-bit CPU• Gates: ~5600• JJ count: ~ 25,000

RQL Register• Gates: 222• JJ count: ~ 2,500• Tested @: 4.7 GHzERSFQ 4-to-16 bit

Decoder• Delay: ~ 30 ps• Energy: ~40 aJ /clock• Clock: 13 GHz

Hypres DesignsNorthrop Grumman Designs


VLSI Integration Demonstrated at MIT-LLWorld Record in JJ Count

• AC-biased shift register: 202,000 bits • JJ count: 810,000+ (World Record)• Integration scale: ≈ Intel’s Pentium, 0.8-μm

process, 3.1M transistors on 294 mm2 chip• 100x increase in integration scale during

four years

1-bit cell

20 μm

• Cell size:20 μm x 15 μm

• JJ density:1.33∙106 JJ/cm2


Superconducting Electronics Scaling Trends

Superconducting electronics can now be fabricated at the very large scale integration (VLSI), and the next challenge is demonstrating application-relevant impact

~ 1M gates



Outline


Superconducting Electronics Application Domains

• Digital circuits have been pursued since the early 1950s

• Increasing interest in both high-performance computing and control circuit applications

• Poised for significant progress in the next 5 – 10 years

Digital Electronics RF Electronics

Quantum Computing Detectors and Sensors

• Extremely small RF electrical resistance enables very high quality factor components

• Used in particle accelerators and free electron lasers

• Maturation of fabrication processes can be leveraged to expand use in RF applications

• Superconducting quantum bits (qubits) are a leading candidate for quantum computation (QC)

• Dominant QC approach pursued by commercial companies

• Superconducting electronics are also being pursued for qubit control and readout

• Used in scientific, astronomy and metrology applications

• Voltage standard and high-sensitivity magnetometers

• Broadband optical detectors and unique energy resolution in the single photon domainImage: NISTImage: Google

Image: HYPRES

-120

-100

-80

-60

-40

-20

0

-60

-50

-40

-30

-20

-10

0

1935 1940 1945 1950 1955 1960 1965

|S2

1| [d

B]

|S1

1| [d

B]

Frequency [MHz]

Image: IEEE Trans MTT (2000): 2519


Control Electronics for Superconducting Devices

I/O plane

Superconductingqubit plane

CLr

Cr

Cc

I0, CJ

inpu

t

. . .

ampl

ified

outp

ut

C.

2 mm50 µm

MIT LL & UC BerkeleyTraveling-Wave

Parametric Amplifier (TWPA)

MIT Lincoln Laboratory3D Integrated Superconducting

Qubit Platform

MIT LL multi-layer superconducting electronics is

critical to achieving the required I/O density for quantum

annealing systems

MIT LL superconducting electronics fabrication

process enables multi-GHz bandwidth, near-quantum-

limited amplification

Advances in superconductor electronics at MIT Lincoln Laboratory are enabling unique quantum systems

IARPA Quantum Enhanced Optimization (QEO) and Logical Qubit (LogiQ) Programs

NASA Goddard & NISTExisting 8x8 pixel

Transition Edge Sensor (TES) array

MIT Lincoln LaboratoryExisting 4x4 element array of Superconducting Nanowire Single Photon Detectors (SNSPDs)

MIT LL superconducting electronics fabrication paired with existing circuit design could enable

multi-kilopixel detector arrays

Superconducting Detector Arrays


Technologies for 3D Integration of Superconducting Qubits

Interposer

RoutingLayer

Qubitchip

Through-substrate

vias (TSVs)

D. Rosenberg et al., npj Quantum Information (2017).

3D integration approaches are being developed to support required connectivity to qubits while maintaining high coherence

3D Superconducting Chip Stack Diagram

3D Superconducting Chip Stack Image

Qubit chip

Routing Layer

Interposer

CLr

Cr

Cc

I0, CJ

inpu

t

. . .

ampl

ified

outp

ut

C.

2 mm50 µm

Traveling Wave Parametric Amplifiers

(TWPAs)

Superconducting bumps


Traveling-wave Parametric Amplifier (TWPA)

TWPA devices fabricated at MIT Lincoln Laboratory are supporting R&D at many universities, companies and Government laboratories

CLr

Cr

Cc

I0, CJ

inpu

t

. . .

ampl

ified

outp

ut

C.

2 mm50 µm

CLr

Cr

Cc

I0, CJ

inpu

t

. . .

ampl

ified

outp

ut

C.

2 mm50 µm10 µm

Vias Josephson junctions à LJ

C C C CLJ

DispersionEngineeringResonator

LrCr

C. Macklin et al., Science 350, 307 (2015)

• Narrow-band Josephson parametric amplifiers first demonstrated in late 1980s

• Traveling-wave parametric amplifiers offer broadband, quantum-limited noise performance– >4 GHz bandwidth– 400 mK noise temperature

• Leverages unique multi-layer superconducting Nbfabrication process at MIT Lincoln Laboratory


• Significant increase in interest in superconducting electronics over the past decade– Classical computation– Control electronics for cryogenic devices, particularly detectors and sensors– Quantum computing

• Rapid advances in Nb trilayer fabrication processes• Future development of superconducting electronic systems will rely on advances in

many technologies beyond just superconducting integrated circuits– Cryogenic systems– Cryogenic packaging and interconnects– Superconducting design and simulation tools– New architectures, algorithms and software

Summary

Superconducting Microelectronics for Next-Generation Computing · 2020. 1. 25. · Contrast to 90nm...

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