Superconducting computing: present status and perspectives · Phys. Rev. Appl. 4, 034007 (2015)....

Superconducting computing

present status and perspectives

Nobuyuki Yoshikawa

1) Graduate School of Engineering

2) Institute of Advance Science

Yokohama National University Japan

ISEC 2019

July 28 ndash August 1 2018 Riverside CA

IEEE CSC amp ESAS SUPERCONDUCTIVITY NEWS FORUM (global edition) September 2019 Plenary presentation 2-KN given at ISEC 28 July-1 August 2019 Riverside USA

1


2


3


4


5

Thomas Ortlepp Distinguished professor YNU

CiS Managing Director Germany

Nobuyuki Yoshikawa PI IAS Professor

Yuki Yamanashi IAS Associate Professor

Naoki Takeuchi IAS Associate Professor

Christopher Ayala IAS Associate Professor

Hideo Suzuki IAS Researcher

Olivia Chan IAS Assistant Professor

Yuxing He IAS Assistant Professor

Members in the research unit on ldquoExtremely Energy-Efficient Processorsrdquo

Members in Overseas

Institute of Advanced Sciences YNU

6


6

Outlines of This Talk

Background and motivation

Past and present status of superconducting digital

electronics

Operation principles of AQFP circuits

AQFP as a logic circuit

Recent research activities on AQFP circuits

Future directions

JosephsonCMOS hybrid memories

Reversible logic circuits

Summary

7


7

Background

httpwwwtop500org

1st-ranked computers in recent TOP500

Low-Power Logic Devices is highly demanded

Estimated power consumption to

realize an exa-scale computer

gt 100 MW

~ $million100 MW per year

K computer (Japan)

Peak performance 105 PFLOPS

Power consumption 126 MW

1 EFLOPS

8


8

AI is Power Hungry

httpjamieshottonorgworkresearchhtml

Example of Semantic Segmentation

httpswwwnvidiaco

men-ustitantitan-xp input size 513 x 513

Flops 346 GFLOPS

httpsgithubcomalbanieconvnet-burden

9


9

Energy Efficiency of CMOS Chips

Energy efficiency of CMOS chips for different CMOS nodes

and die sizes

fchip = 1 GHz

A Fuchs and D Wentzlaff ldquoThe Accelerator Wall Limits of Chip-

Specializationrdquo the 25th IEEE International Symposium on High-

Performance Computer Architecture (HPCA rsquo19) 2019

10

Normalized to 25 mm2 chip fabricated with 45 nm CMOS


10

Single-Flux-Quantum (SFQ) Circuits

Q = CLVDD

CMOS circuits

E = QVDD ~ 10-16 J

SFQ circuits

Ic

E = F0 Ic ~ 10-19 J

Φ0 = h(2e)

Superconducting loop

with Josephson junctions

Switching energy Switching energy

11


11

Comparison of Energy-Delay Product

Energy-efficient SFQ

12


12

IRDS (International Roadmap for Device and Systems)

Available at httpsirdsieeeorgeditions2018

Energy and delay of gates with 100 mm

interconnection length

13


13

Rapid Single-Flux-Quantum (RSFQ) Circuits

bull Pulse height ~ 400 mV

bull Pulse width ~ 3 ps

bull Power ~ nWgate

T Flip-flop operating at up to 770 GHz

W Chen et al IEEE Trans Appl Supercond 9 3212ndash

3215 (1999)

256-b shift register operating at 12 GHz O Mukhanov et al IEEE Trans Appl Supercond 3

2578-2581 (1993) K K Likharev V K Semenov IEEE Trans Appl

Supercond 1 3ndash28 (1991)

Josephson junction

400 mV

3 ps

14


14

Power Consumption in RSFQ Logic

Reduction of static

power is required

Dynamic power dissipation

PD = F0Icf

Static power dissipation

PS = RbIc2

PD ~ PS20

15


15

DC Powered

RQL (Northrop Grumman)

PS ~ PD ~ IcF0f

LV-SFQ (Nagoya Univ)

PS ~ 0 PD ~ IcF0f

PS ~ 0 PD lt IcF0f

dt

dφ

2π

Ф0V

RB

J1

RS

IB

VB

Q P Herr et al J Appl Phys

109 103903 (2011)

O A Mukhanov IEEE Trans

Appl Supercond 21 760 (2011)

ERSFQ (Hypres)

AC Powered

PS ~ 5PD PD ~ IcF0f

M Tanaka et al JJAP 5

1053102 (2012)

AQFP (Yokohama National Univ)

N Takeuchi et al SUST

26 035010 (2013)

Energy-Efficient SFQ Circuits 16


16


Energy-efficient RSFQ

17


17

Two Options in SC Digital Electronics

SFQ Logic

Extremely high throughput

50 GHz ~ 100 GHz frequency

RSFQ ERSFQ LVSFQ RQL

Adiabatic QFP Logic

Extremely high energy

efficiency

1~10 zJoperation

Combination of these two logic circuits brings about high-

performance digital systems

18


18

56-GHz Demonstration of Gate-Level-Pipelined Bit-Parallel ALU

1 mm

M9

M8

M7

M6M5M4M3M2

M1

Si Substrate

SiO2

Junction

Resistor

Completely Planarized Layer

Active layerincluding JJsand resistors

Main groundplane

Upper PTLs

Lower PTLs

DC power

SEM image by courtesy of AIST

S Nagasawa et al IEICE Trans Electron E97-C (2014) 132ndash140

clk

Op_and

Inv_x

Inv_y

C_out

Clk_outS0

S1S2

S3S4

S5S6

S7

Inpu

tO

utp

ut

Op_xor

Op_arith

Result

Input to SR_IN

AD

DA

DD

SU

B

SU

B

High Frequency clock1 0

0 0

0 0

0 0

01 0

00 1

00

01

1 1

11

1 1

11 0

1 0

1 0

0 0

0 1

1

1111 1111 ndash 1111 1111 = 1 0000 0000

1010 1010 ndash 1001 1001 = 1 0001 0001

1111 1111 + 1111 1111 = 1 1111 1110

1010 1010 + 1001 1001 = 1 0100 0011

56 GHz

M Tanaka et al ISLPED 2017 Design Contest Honorable Mention Award Taipei

7348 junctions 393times207 mm2

19


19




electronics




Future directions



Summary

20


20

Energy Potential of RSFQ Circuits

Energy

Phase State 1 State 2

E1

E2

Input energy E1

Output energy E2

Energy dissipation E2

Requirement for the reduction of

switching errors

E1 gt 100 kBT

F0

Ib

21


21


Energy


E1

E2

Nonadiabatic

transition

Adiabatic operation of the system is required for

energy-efficient computing

F0

Ib

~ IbF0

22


22

Quantum Flux Parametron (QFP)

M Hosoya et al IEEE Trans Appl Supercond 1 77ndash89 (1991)

E Goto Proc 1st RIKEN Symp Josephson Electronics pp 48-51 (1984)

23


23

Operation Principle of


E Goto Pros 1st RIKEN Symp Josephson Electronics 1984

Iout

E

Iout

E

Iout

E

t

Exciting

current

24


24

Potential Energy of QFP

coscos2

2

)()( 22

qL

S

L

Ejqfp EU

2

2

22

22

22

212100

0

0

0

01

00

1

F

F

F

F

F

IEE

ILIL

ILIM

Jj

q

qL

Sq

SE

E

M Hosoya et al IEEE Trans Appl Supercond vol 1 1991 pp 77 ndash 89

Normalized exciting

current

Normalized input

current

Normalized loop

inductance

Normalized output

inductance

E

S

q

L

E = 15 E = 27 E = 22

(L q) = (10 30)

25


25

QFP in Nonadiabatic and Adiabatic Modes

(L q) = (10 30)

(L q) = (08 04)

Non-adiabatic-mode QFP

Adiabatic-mode QFP

26

N Takeuchi et al SUST 26 035010 (2013)


26

Evolution of Junction Phase

The phase of junctions

in AQFP change

adiabatically Ph

ase

diffe

ren

ce

s

Excitation flux

27

Takeuchi et al Phys Rev Appl 4 034007 (2015)


27

When rise time is 1000 ps Ebit = 0023 IcF0 (~ 20kBT)

11000 of RSFQ

E

S

q

L

fEnergy dissipation

Bit Energy vs Clock Period of AQFP 28

(L L)



28

Robust AQFP Design

(02 16)

Linn = Lqn kq = 03 Iin1 = 01Ic and

the rise time is 100 ps

(02 16)



Bit Energy Bias Margin

N Takeuchi et al IEEE TAS 23 (2013) 1700304

29


29

Energy Consumption of AQFP

2 0rf

swcbit IE

F

Bit Energy

bull rf Risingfalling time of clock

Intrinsic switching time

cccsw

I

C

RI

00 2 F

F

rf

bull c McCumber parameter

Damping

resistance

c ~ 1 critical damping

c gt 1 under damping

30

N Takeuchi et al APL 103 052602 (2013)


30


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf

rf is 1000 ps Ic = 50 mA

c Dependence of Bit-Energy of AQFP

31



31

Bit-Error-Rate (BER) of the AQFP at

Finite Temperatures

bull Iteration number is 104

(L q) = (02 16) Ic = 50 mA

Linn = Lqn kq = 03 Iin1 = 01Ic

and rise time is 200 ps

T [K] IcF0KBT Bias Margin for BER lt 10-23

42 110 plusmn194

12 386 plusmn138

20 232 plusmn88

N Takeuchi et al IEEE TAS 23 1700304 (2013)

32


32




electronics




Future directions



Summary

33


33

Important Metrics as a Logic Circuit

Gainsignal reproducibility

Functionality

Speed

Energy consumption

Driving ability

Connectability

Robustness

Density

34


34

Signal Propagation in AQFP Array

Excitation

Outputs

x2 = 05

(L q) = (02 16)

Ic = 50 mA

Iin1 = 5 mA

Lin = Lq kq = 03

35



35

Gain

Current gain of AQFP is considerably large

If we assume

dIin ~ 1 mA and Ic = 50 mA

the current gain is given by

Ic dIin ~ 50

cf In RSFQ circuits with

Iin ~ 20 mA Ic = 100 mA

the current gain is ~ 5


Current gain vs input current at T = 0K

dIin input thermal noise

36


36

Functionality

NOT gate is cost free

Majority gate is a basic logic gate

-

NOT gate is made by using a

transformer with negative coupling

Buffer NOT

Majority gate is made by connecting

three buffer in parallel

Majority a b c

x

x = MAJ(a b c) = ab + bc + ac

K Inoue et al IEEE Trans Appl Supercond 23 1301105 (2013)

37


37

Speed

AQFP is driven by multi-phase clocks (4-phase is typically used)

Target clock frequency is 5 GHz

Double excitation method can increases the clock frequency [1]

Latency is improved by increasing the number of phase

Clocking of AQFP gates

119871119886119905119890119899119888119910 =119888119897119900119888119896 119901119890119903119894119900119889

119899119906119898119887119890119903 119900119891 119901ℎ119886119904119890

[1] K Fang et al J Appl Phys 121 143901 (2017)

38


38

Energy Consumption

The static energy consumption is zero the dynamic energy consumption

is proportional to the clock frequency

The energy consumption is reduced by using high-Jc and high-c junctions

c is 1000 ps Ic = 50 mA


2 0rf

swcbit IE

F

ccc

swj

c

RI

00 2 F

F

Bit energy


39



39

Driving Ability

Fan-out of AQFP gate is relatively large (~ 4)

cf optimal fan-out of CMOS is 3 ~ 4

Fan-out 14 splitter

AIST Nb Josephson standard process

(STP2) was used

40

N


40

Connectability

The output current of AQFP gate decreases with increase

of interconnect inductance which limits the wire length

Lmax ~ 1 mm

Iout vs Lwire

N Takeuchi et al J Appl Phys 117 173912 (2015)

Testing of maximum wiring length

41


41

Robustness

Wide operation margins were

observed in experiments

42



42

Demonstrated 84k-Junction AQFP buffer array 43

AIST 10 kAcm2 high-speed standard

process (HSTP) was used

Area 668times623 mm2

Bias Current 360 mA

JJ number 83736

AQFP is robust because

The operation is based on

differential pairs of junctions

and inductances

The critical current of all

junctions is the same


43

Density

Multi-layer processes improve the circuit density

13times25 mm2

(-675 area reduction)

25times40 mm2

Excitation line

(upper layers)

Transformer

(lower layers)

4-metal layer process

(Junction size ~ 1 mm)

Si Substrate

SiO 2

Nb JJ

Mo Resistor

AlOx

BAS (M2) ＧＣ

RC RC

JC

BC

COU (M3)

BAS (M2)

COU (M3)

CC CC

COU

CTL (M4) CTL (M4)

SiO 2

JP Nb Pd - NW1 (40 nm + 40 nm)

I1+I2+I3 +I4 (700 nm)

I5 (500 nm)

CC

CTL (M4)

CC

IN1 (100 nm)

Nb Pd - NW2 (40 nm + 40 nm) IN2 (100 nm)

Nb Ground Plane (M1)



~ 03M gatecm2

44


44

AQFP Cell Library for the MIT LL

8-Metal Layer Process

bull AQFP and an output

transformer can be

overlapped by using the

MIT LL multilayer process

Schematic of an

AQFP buffer

15 mm x 20 mm

Supported by IARPA SuperTools project

AIST HSTP process

MIT LL process

(SFQ5ee)

Layouts of an AQFP buffer

20 mm x 40 mm

45


45

Design Methodology

Logic cells can be designed by placing four building blocks

Buffer NOT Constant Branch

46

(

accbba

cbax

　　

MAJ (

ab

ba

bax

　　

　　

1MAJ azyx

Majority NAND Splitter

Buffer 13-branch

NOT

1-constant


46


46

Layout of Basic Cells

47

Building block cells Majority cell

Symmetric design prevents the parasitic coupling between

the excitation and output inductance


47


47

AQFP Logic Design

Logic cells are placed together

like Lego blocks

Logic gates grouped by phase

amp data flow

Inputs Phase 1

Phase 2

Phase 3

Phase 1

Phase 2

Phase 3

Phase 1

Outputs

Data

flo

w

AQFP design flow

48


48

HDL-Modeling of AQFP Logic

49

An AQFP majority gate is modeled by a

combinational logic with a larch

HDL-modeling of AQFP Majority gate Waveform of AQFP majority gate

Analog simulation results

Digital simulation results

49

Q Xu et al IEEE TAS 26 1ndash5 (2016)

Q Xu et al IEEE TAS 27 1301905 (2017)


49

EDA Tools for Top-Down Design

VerilogVHDL Schematic Digital Sim Layout Chip

50


50

AQFP Circuits Fabricated by Top-Down

Design Flow

Fabricated by AIST HSTP

4-bit shifter 8-bit shifter 16-bit carry look-

ahead adder

12-bit instruction

decoder

Correct

operation

confirmed

1090 JJ

7100 JJ

4976 JJ 2664 JJ Partial operation confirmed Partial operation confirmed

C Ayala et al ISEC 2019 Riverside

T Tanaka et al ISEC 2019 Riverside

Y Murai et al IEEE TAS 27 1ndash9 (2017)

T Tanaka et al IEEE TAS 291-6 (2019)

51


51

Measurement of Energy Consumption of

AQFP Circuits at 5 GHz

8-bit AQFP Cary Look-ahead Adder

The total junction count 1638

Output waveform of carry 1 GHz

Power consumption measurements

Energy consumption 15 aJoperation

~ 24 kBTjunction

5 GHz

52

Takeuchi et al APL 114 (2019) 042602



52

Delay-line Clocking for Short Latency

Takeuchi et al APL to be published

Phase-to-phase clock delay

shorten by delay line

5-GHz 4-phse

clock latency

~ 50 ps

4-GHz test result of AQFP buffer

array with latency of 10 ps


Delay-line

clock latency

~ 5 ps

53


53

Directly Coupled AQFP Logic

Takeuchi et al submitted to Phys Rev Appl

Directly coupled AQFP inverter

Transformer was removed to decrease the cell size

Good for scaling down the device size in the future Fabricated by AIST HSTP

Conventional AQFP inverter

54


54

Development of 3D AQFP ICs

Double Gate Process (DGP) Comparison of XOR Gate

DGP HSTP

The circuit area was reduced by 44

T Ando et al SUST 30 (2017) 075003

55

Fabricated by AIST DGP


55




electronics




Future directions



Summary

56


56

Future Directions

Memories

Josephson-CMOS hybrid memories

Magnetic memories

More energy efficient logic

Reversible QFP (RQFP) circuits

Other applications

Control and readout circuits for Quantum computers

Read out circuits for superconducting sensor arrays

57


57

JosephsonCMOS Hybrid Memory

[1] Ghoshal et al IEEE TAS 3 2316 1993

64-kb Cryo-CMOS RAM

[2] G Konno et al IEEE TAS 27 1300607 2017

180 nm CMOS and 25 kAcm2 JJ processes

Concept of hybrid

Josephson-CMOS RAM

Successful demonstration of SFQ processor with

a cryo-CMOS memory

Y Hironaka et al ISEC 2019 Riverside

58


58

AQFP-CMOS Hybrid FPGA

Concept 8T CMOS memory cell with

AQFP read-out

Reduction of output current of a

memory cell with reduced VDD

CMOS memory is used as a rewritable ROM

Power consumption of CMOS is reduced by

decreasing VDD

Y Okuma et al submitted to IEEE TAS

AQFP two-by-two logic cells

59


59

Issues in JosephsonCMOS Hybrid systems

CMOS devices consume a lot of power

105 times larger than AQFP

Connection between Josephson and CMOS devices

Use of low VTH

process

Use of adiabatic

decoder

Use of new amplifier

(nTron)

Use of flip chip bonding ~100 pads1 mm2

Use of monolithic JosephsonCMOS fabrication process

60


60

Flip-chip Bonding Monolithic Process

Hybrid integration of AQFP and

nTron chips

Curtesy of Prof Ortlepp and Prof Berggren

T Ortlepp et al ISEC2019 Riverside

Monolithic integration of AQFP

and CMOS circuits

CMOS circuits on a large wafer

Trimming of small

wafers

Josephson circuit

fabrication

61


61

Landauerrsquos Principle

Equivalence between thermodynamic entropy and

information entropy

For computation reducing the information entropy the

minimum bit energy Ebit = kBTln2 is consumed

For computation conserving the information entropy

there is no minimum limit of bit energy in computation

R Landauer IBM Journal of Research and Development 5 183 (1961)

C H Bennett IBM Journal of Research and Development 17 525 (1973)

Thermodynamic entropy ＝ Information entropy

101100010100110

62


62

Reversible Computing

bull The entropy is conserved

during computation

bull Logical reversibility is

required Input Output

c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate

Physical reversibility bi-

directionality is also required

E Fredkin and T Toffoli Int J Theor Phys 21

219-253 (1982)

data input data output

63


63

Reversible AQFP (RQFP)

Reversible majority QFP gate

A logically and physically reversible

gate can be achieved by using

AQFP gates

N Takeuchi et al Scientific Reports 4 6354 (2014)


64


64

Reversible AQFP Adder

T Yamae et al SUST 32 035005 (2019)


Schematic of 1b full adder Energy dissipation of 1b full adder

Bit energy smaller than kBTln2 is

possible in RQFP circuits

kBT ln2

RQFP register file see Yamae et al ISEC 2019 Riverside

65


65

Summary

Two outstanding features of superconducting

logic circuits

High-speed SFQ logic circuits

Energy-efficient AQFP logic circuits

Memories are key devices for digital

applications

Hybrid Josephson-MOS memory has its potential

More energy-efficient logic circuit is possible

by using RQFP

66


66


2


3


4


5











Members in Overseas


6


6




electronics




Future directions



Summary

7


7

Background

httpwwwtop500org





gt 100 MW


K computer (Japan)



1 EFLOPS

8


8

AI is Power Hungry



httpswwwnvidiaco


Flops 346 GFLOPS


9


9



and die sizes

fchip = 1 GHz




10



10


Q = CLVDD

CMOS circuits

E = QVDD ~ 10-16 J

SFQ circuits

Ic

E = F0 Ic ~ 10-19 J

Φ0 = h(2e)




11


11



12


12





13


13




bull Power ~ nWgate



3215 (1999)




Josephson junction

400 mV

3 ps

14


14


Reduction of static

power is required


PD = F0Icf


PS = RbIc2

PD ~ PS20

15


15

DC Powered


PS ~ PD ~ IcF0f


PS ~ 0 PD ~ IcF0f

PS ~ 0 PD lt IcF0f

dt

dφ

2π

Ф0V

RB

J1

RS

IB

VB


109 103903 (2011)



ERSFQ (Hypres)

AC Powered

PS ~ 5PD PD ~ IcF0f


1053102 (2012)



26 035010 (2013)



16



17


17


SFQ Logic




Adiabatic QFP Logic


efficiency

1~10 zJoperation



18


18


1 mm

M9

M8

M7

M6M5M4M3M2

M1

Si Substrate

SiO2

Junction

Resistor



Main groundplane

Upper PTLs

Lower PTLs

DC power



clk

Op_and

Inv_x

Inv_y

C_out

Clk_outS0

S1S2

S3S4

S5S6

S7

Inpu

tO

utp

ut

Op_xor

Op_arith

Result

Input to SR_IN

AD

DA

DD

SU

B

SU

B


0 0

0 0

0 0

01 0

00 1

00

01

1 1

11

1 1

11 0

1 0

1 0

0 0

0 1

1

1111 1111 ndash 1111 1111 = 1 0000 0000

1010 1010 ndash 1001 1001 = 1 0001 0001

1111 1111 + 1111 1111 = 1 1111 1110

1010 1010 + 1001 1001 = 1 0100 0011

56 GHz



19


19




electronics




Future directions



Summary

20


20


Energy


E1

E2

Input energy E1

Output energy E2



switching errors

E1 gt 100 kBT

F0

Ib

21


21


Energy


E1

E2

Nonadiabatic

transition



F0

Ib

~ IbF0

22


22




23


23




Iout

E

Iout

E

Iout

E

t

Exciting

current

24


24


coscos2

2

)()( 22

qL

S

L

Ejqfp EU

2

2

22

22

22

212100

0

0

0

01

00

1

F

F

F

F

F

IEE

ILIL

ILIM

Jj

q

qL

Sq

SE

E


Normalized exciting

current

Normalized input

current

Normalized loop

inductance

Normalized output

inductance

E

S

q

L

E = 15 E = 27 E = 22

(L q) = (10 30)

25


25


(L q) = (10 30)

(L q) = (08 04)


Adiabatic-mode QFP

26



26



in AQFP change

adiabatically Ph

ase

diffe

ren

ce

s

Excitation flux

27



27


11000 of RSFQ

E

S

q

L

fEnergy dissipation


(L L)



28

Robust AQFP Design

(02 16)



(02 16)





29


29


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf


Damping

resistance



30



30


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf



31



31


Finite Temperatures


(L q) = (02 16) Ic = 50 mA




42 110 plusmn194

12 386 plusmn138

20 232 plusmn88


32


32




electronics




Future directions



Summary

33


33



Functionality

Speed

Energy consumption

Driving ability

Connectability

Robustness

Density

34


34


Excitation

Outputs

x2 = 05

(L q) = (02 16)

Ic = 50 mA

Iin1 = 5 mA

Lin = Lq kq = 03

35



35

Gain


If we assume



Ic dIin ~ 50


Iin ~ 20 mA Ic = 100 mA





36


36

Functionality



-



Buffer NOT



Majority a b c

x



37


37

Speed






119871119886119905119890119899119888119910 =119888119897119900119888119896 119901119890119903119894119900119889

119899119906119898119887119890119903 119900119891 119901ℎ119886119904119890


38


38

Energy Consumption




c is 1000 ps Ic = 50 mA


2 0rf

swcbit IE

F

ccc

swj

c

RI

00 2 F

F

Bit energy


39



39

Driving Ability



Fan-out 14 splitter


(STP2) was used

40

N


40

Connectability



Lmax ~ 1 mm

Iout vs Lwire



41


41

Robustness



42



42





Bias Current 360 mA

JJ number 83736




and inductances




43

Density


13times25 mm2


25times40 mm2

Excitation line

(upper layers)

Transformer

(lower layers)



Si Substrate

SiO 2

Nb JJ

Mo Resistor

AlOx

BAS (M2) ＧＣ

RC RC

JC

BC

COU (M3)

BAS (M2)

COU (M3)

CC CC

COU

CTL (M4) CTL (M4)

SiO 2


I1+I2+I3 +I4 (700 nm)

I5 (500 nm)

CC

CTL (M4)

CC

IN1 (100 nm)

Nb Pd - NW2 (40 nm + 40 nm) IN2 (100 nm)




~ 03M gatecm2

44


44




transformer can be



Schematic of an

AQFP buffer

15 mm x 20 mm


AIST HSTP process

MIT LL process

(SFQ5ee)


20 mm x 40 mm

45


45

Design Methodology



46

(

accbba

cbax

　　

MAJ (

ab

ba

bax

　　

　　

1MAJ azyx


Buffer 13-branch

NOT

1-constant


46


46


47





47


47

AQFP Logic Design


like Lego blocks


amp data flow

Inputs Phase 1

Phase 2

Phase 3

Phase 1

Phase 2

Phase 3

Phase 1

Outputs

Data

flo

w

AQFP design flow

48


48


49






49


Q Xu et al IEEE TAS 27 1301905 (2017)


49



50


50


Design Flow



ahead adder

12-bit instruction

decoder

Correct

operation

confirmed

1090 JJ

7100 JJ






51


51








~ 24 kBTjunction

5 GHz

52




52





5-GHz 4-phse

clock latency

~ 50 ps




Delay-line

clock latency

~ 5 ps

53


53







54


54



DGP HSTP


T Ando et al SUST 30 (2017) 075003

55



55




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66


3


4


5











Members in Overseas


6


6




electronics




Future directions



Summary

7


7

Background

httpwwwtop500org





gt 100 MW


K computer (Japan)



1 EFLOPS

8


8

AI is Power Hungry



httpswwwnvidiaco


Flops 346 GFLOPS


9


9



and die sizes

fchip = 1 GHz




10



10


Q = CLVDD

CMOS circuits

E = QVDD ~ 10-16 J

SFQ circuits

Ic

E = F0 Ic ~ 10-19 J

Φ0 = h(2e)




11


11



12


12





13


13




bull Power ~ nWgate



3215 (1999)




Josephson junction

400 mV

3 ps

14


14


Reduction of static

power is required


PD = F0Icf


PS = RbIc2

PD ~ PS20

15


15

DC Powered


PS ~ PD ~ IcF0f


PS ~ 0 PD ~ IcF0f

PS ~ 0 PD lt IcF0f

dt

dφ

2π

Ф0V

RB

J1

RS

IB

VB


109 103903 (2011)



ERSFQ (Hypres)

AC Powered

PS ~ 5PD PD ~ IcF0f


1053102 (2012)



26 035010 (2013)



16



17


17


SFQ Logic




Adiabatic QFP Logic


efficiency

1~10 zJoperation



18


18


1 mm

M9

M8

M7

M6M5M4M3M2

M1

Si Substrate

SiO2

Junction

Resistor



Main groundplane

Upper PTLs

Lower PTLs

DC power



clk

Op_and

Inv_x

Inv_y

C_out

Clk_outS0

S1S2

S3S4

S5S6

S7

Inpu

tO

utp

ut

Op_xor

Op_arith

Result

Input to SR_IN

AD

DA

DD

SU

B

SU

B


0 0

0 0

0 0

01 0

00 1

00

01

1 1

11

1 1

11 0

1 0

1 0

0 0

0 1

1

1111 1111 ndash 1111 1111 = 1 0000 0000

1010 1010 ndash 1001 1001 = 1 0001 0001

1111 1111 + 1111 1111 = 1 1111 1110

1010 1010 + 1001 1001 = 1 0100 0011

56 GHz



19


19




electronics




Future directions



Summary

20


20


Energy


E1

E2

Input energy E1

Output energy E2



switching errors

E1 gt 100 kBT

F0

Ib

21


21


Energy


E1

E2

Nonadiabatic

transition



F0

Ib

~ IbF0

22


22




23


23




Iout

E

Iout

E

Iout

E

t

Exciting

current

24


24


coscos2

2

)()( 22

qL

S

L

Ejqfp EU

2

2

22

22

22

212100

0

0

0

01

00

1

F

F

F

F

F

IEE

ILIL

ILIM

Jj

q

qL

Sq

SE

E


Normalized exciting

current

Normalized input

current

Normalized loop

inductance

Normalized output

inductance

E

S

q

L

E = 15 E = 27 E = 22

(L q) = (10 30)

25


25


(L q) = (10 30)

(L q) = (08 04)


Adiabatic-mode QFP

26



26



in AQFP change

adiabatically Ph

ase

diffe

ren

ce

s

Excitation flux

27



27


11000 of RSFQ

E

S

q

L

fEnergy dissipation


(L L)



28

Robust AQFP Design

(02 16)



(02 16)





29


29


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf


Damping

resistance



30



30


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf



31



31


Finite Temperatures


(L q) = (02 16) Ic = 50 mA




42 110 plusmn194

12 386 plusmn138

20 232 plusmn88


32


32




electronics




Future directions



Summary

33


33



Functionality

Speed

Energy consumption

Driving ability

Connectability

Robustness

Density

34


34


Excitation

Outputs

x2 = 05

(L q) = (02 16)

Ic = 50 mA

Iin1 = 5 mA

Lin = Lq kq = 03

35



35

Gain


If we assume



Ic dIin ~ 50


Iin ~ 20 mA Ic = 100 mA





36


36

Functionality



-



Buffer NOT



Majority a b c

x



37


37

Speed






119871119886119905119890119899119888119910 =119888119897119900119888119896 119901119890119903119894119900119889

119899119906119898119887119890119903 119900119891 119901ℎ119886119904119890


38


38

Energy Consumption




c is 1000 ps Ic = 50 mA


2 0rf

swcbit IE

F

ccc

swj

c

RI

00 2 F

F

Bit energy


39



39

Driving Ability



Fan-out 14 splitter


(STP2) was used

40

N


40

Connectability



Lmax ~ 1 mm

Iout vs Lwire



41


41

Robustness



42



42





Bias Current 360 mA

JJ number 83736




and inductances




43

Density


13times25 mm2


25times40 mm2

Excitation line

(upper layers)

Transformer

(lower layers)



Si Substrate

SiO 2

Nb JJ

Mo Resistor

AlOx

BAS (M2) ＧＣ

RC RC

JC

BC

COU (M3)

BAS (M2)

COU (M3)

CC CC

COU

CTL (M4) CTL (M4)

SiO 2


I1+I2+I3 +I4 (700 nm)

I5 (500 nm)

CC

CTL (M4)

CC

IN1 (100 nm)

Nb Pd - NW2 (40 nm + 40 nm) IN2 (100 nm)




~ 03M gatecm2

44


44




transformer can be



Schematic of an

AQFP buffer

15 mm x 20 mm


AIST HSTP process

MIT LL process

(SFQ5ee)


20 mm x 40 mm

45


45

Design Methodology



46

(

accbba

cbax

　　

MAJ (

ab

ba

bax

　　

　　

1MAJ azyx


Buffer 13-branch

NOT

1-constant


46


46


47





47


47

AQFP Logic Design


like Lego blocks


amp data flow

Inputs Phase 1

Phase 2

Phase 3

Phase 1

Phase 2

Phase 3

Phase 1

Outputs

Data

flo

w

AQFP design flow

48


48


49






49


Q Xu et al IEEE TAS 27 1301905 (2017)


49



50


50


Design Flow



ahead adder

12-bit instruction

decoder

Correct

operation

confirmed

1090 JJ

7100 JJ






51


51








~ 24 kBTjunction

5 GHz

52




52





5-GHz 4-phse

clock latency

~ 50 ps




Delay-line

clock latency

~ 5 ps

53


53







54


54



DGP HSTP


T Ando et al SUST 30 (2017) 075003

55



55




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66


4


5











Members in Overseas


6


6




electronics




Future directions



Summary

7


7

Background

httpwwwtop500org





gt 100 MW


K computer (Japan)



1 EFLOPS

8


8

AI is Power Hungry



httpswwwnvidiaco


Flops 346 GFLOPS


9


9



and die sizes

fchip = 1 GHz




10



10


Q = CLVDD

CMOS circuits

E = QVDD ~ 10-16 J

SFQ circuits

Ic

E = F0 Ic ~ 10-19 J

Φ0 = h(2e)




11


11



12


12





13


13




bull Power ~ nWgate



3215 (1999)




Josephson junction

400 mV

3 ps

14


14


Reduction of static

power is required


PD = F0Icf


PS = RbIc2

PD ~ PS20

15


15

DC Powered


PS ~ PD ~ IcF0f


PS ~ 0 PD ~ IcF0f

PS ~ 0 PD lt IcF0f

dt

dφ

2π

Ф0V

RB

J1

RS

IB

VB


109 103903 (2011)



ERSFQ (Hypres)

AC Powered

PS ~ 5PD PD ~ IcF0f


1053102 (2012)



26 035010 (2013)



16



17


17


SFQ Logic




Adiabatic QFP Logic


efficiency

1~10 zJoperation



18


18


1 mm

M9

M8

M7

M6M5M4M3M2

M1

Si Substrate

SiO2

Junction

Resistor



Main groundplane

Upper PTLs

Lower PTLs

DC power



clk

Op_and

Inv_x

Inv_y

C_out

Clk_outS0

S1S2

S3S4

S5S6

S7

Inpu

tO

utp

ut

Op_xor

Op_arith

Result

Input to SR_IN

AD

DA

DD

SU

B

SU

B


0 0

0 0

0 0

01 0

00 1

00

01

1 1

11

1 1

11 0

1 0

1 0

0 0

0 1

1

1111 1111 ndash 1111 1111 = 1 0000 0000

1010 1010 ndash 1001 1001 = 1 0001 0001

1111 1111 + 1111 1111 = 1 1111 1110

1010 1010 + 1001 1001 = 1 0100 0011

56 GHz



19


19




electronics




Future directions



Summary

20


20


Energy


E1

E2

Input energy E1

Output energy E2



switching errors

E1 gt 100 kBT

F0

Ib

21


21


Energy


E1

E2

Nonadiabatic

transition



F0

Ib

~ IbF0

22


22




23


23




Iout

E

Iout

E

Iout

E

t

Exciting

current

24


24


coscos2

2

)()( 22

qL

S

L

Ejqfp EU

2

2

22

22

22

212100

0

0

0

01

00

1

F

F

F

F

F

IEE

ILIL

ILIM

Jj

q

qL

Sq

SE

E


Normalized exciting

current

Normalized input

current

Normalized loop

inductance

Normalized output

inductance

E

S

q

L

E = 15 E = 27 E = 22

(L q) = (10 30)

25


25


(L q) = (10 30)

(L q) = (08 04)


Adiabatic-mode QFP

26



26



in AQFP change

adiabatically Ph

ase

diffe

ren

ce

s

Excitation flux

27



27


11000 of RSFQ

E

S

q

L

fEnergy dissipation


(L L)



28

Robust AQFP Design

(02 16)



(02 16)





29


29


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf


Damping

resistance



30



30


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf



31



31


Finite Temperatures


(L q) = (02 16) Ic = 50 mA




42 110 plusmn194

12 386 plusmn138

20 232 plusmn88


32


32




electronics




Future directions



Summary

33


33



Functionality

Speed

Energy consumption

Driving ability

Connectability

Robustness

Density

34


34


Excitation

Outputs

x2 = 05

(L q) = (02 16)

Ic = 50 mA

Iin1 = 5 mA

Lin = Lq kq = 03

35



35

Gain


If we assume



Ic dIin ~ 50


Iin ~ 20 mA Ic = 100 mA





36


36

Functionality



-



Buffer NOT



Majority a b c

x



37


37

Speed






119871119886119905119890119899119888119910 =119888119897119900119888119896 119901119890119903119894119900119889

119899119906119898119887119890119903 119900119891 119901ℎ119886119904119890


38


38

Energy Consumption




c is 1000 ps Ic = 50 mA


2 0rf

swcbit IE

F

ccc

swj

c

RI

00 2 F

F

Bit energy


39



39

Driving Ability



Fan-out 14 splitter


(STP2) was used

40

N


40

Connectability



Lmax ~ 1 mm

Iout vs Lwire



41


41

Robustness



42



42





Bias Current 360 mA

JJ number 83736




and inductances




43

Density


13times25 mm2


25times40 mm2

Excitation line

(upper layers)

Transformer

(lower layers)



Si Substrate

SiO 2

Nb JJ

Mo Resistor

AlOx

BAS (M2) ＧＣ

RC RC

JC

BC

COU (M3)

BAS (M2)

COU (M3)

CC CC

COU

CTL (M4) CTL (M4)

SiO 2


I1+I2+I3 +I4 (700 nm)

I5 (500 nm)

CC

CTL (M4)

CC

IN1 (100 nm)

Nb Pd - NW2 (40 nm + 40 nm) IN2 (100 nm)




~ 03M gatecm2

44


44




transformer can be



Schematic of an

AQFP buffer

15 mm x 20 mm


AIST HSTP process

MIT LL process

(SFQ5ee)


20 mm x 40 mm

45


45

Design Methodology



46

(

accbba

cbax

　　

MAJ (

ab

ba

bax

　　

　　

1MAJ azyx


Buffer 13-branch

NOT

1-constant


46


46


47





47


47

AQFP Logic Design


like Lego blocks


amp data flow

Inputs Phase 1

Phase 2

Phase 3

Phase 1

Phase 2

Phase 3

Phase 1

Outputs

Data

flo

w

AQFP design flow

48


48


49






49


Q Xu et al IEEE TAS 27 1301905 (2017)


49



50


50


Design Flow



ahead adder

12-bit instruction

decoder

Correct

operation

confirmed

1090 JJ

7100 JJ






51


51








~ 24 kBTjunction

5 GHz

52




52





5-GHz 4-phse

clock latency

~ 50 ps




Delay-line

clock latency

~ 5 ps

53


53







54


54



DGP HSTP


T Ando et al SUST 30 (2017) 075003

55



55




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66


5











Members in Overseas


6


6




electronics




Future directions



Summary

7


7

Background

httpwwwtop500org





gt 100 MW


K computer (Japan)



1 EFLOPS

8


8

AI is Power Hungry



httpswwwnvidiaco


Flops 346 GFLOPS


9


9



and die sizes

fchip = 1 GHz




10



10


Q = CLVDD

CMOS circuits

E = QVDD ~ 10-16 J

SFQ circuits

Ic

E = F0 Ic ~ 10-19 J

Φ0 = h(2e)




11


11



12


12





13


13




bull Power ~ nWgate



3215 (1999)




Josephson junction

400 mV

3 ps

14


14


Reduction of static

power is required


PD = F0Icf


PS = RbIc2

PD ~ PS20

15


15

DC Powered


PS ~ PD ~ IcF0f


PS ~ 0 PD ~ IcF0f

PS ~ 0 PD lt IcF0f

dt

dφ

2π

Ф0V

RB

J1

RS

IB

VB


109 103903 (2011)



ERSFQ (Hypres)

AC Powered

PS ~ 5PD PD ~ IcF0f


1053102 (2012)



26 035010 (2013)



16



17


17


SFQ Logic




Adiabatic QFP Logic


efficiency

1~10 zJoperation



18


18


1 mm

M9

M8

M7

M6M5M4M3M2

M1

Si Substrate

SiO2

Junction

Resistor



Main groundplane

Upper PTLs

Lower PTLs

DC power



clk

Op_and

Inv_x

Inv_y

C_out

Clk_outS0

S1S2

S3S4

S5S6

S7

Inpu

tO

utp

ut

Op_xor

Op_arith

Result

Input to SR_IN

AD

DA

DD

SU

B

SU

B


0 0

0 0

0 0

01 0

00 1

00

01

1 1

11

1 1

11 0

1 0

1 0

0 0

0 1

1

1111 1111 ndash 1111 1111 = 1 0000 0000

1010 1010 ndash 1001 1001 = 1 0001 0001

1111 1111 + 1111 1111 = 1 1111 1110

1010 1010 + 1001 1001 = 1 0100 0011

56 GHz



19


19




electronics




Future directions



Summary

20


20


Energy


E1

E2

Input energy E1

Output energy E2



switching errors

E1 gt 100 kBT

F0

Ib

21


21


Energy


E1

E2

Nonadiabatic

transition



F0

Ib

~ IbF0

22


22




23


23




Iout

E

Iout

E

Iout

E

t

Exciting

current

24


24


coscos2

2

)()( 22

qL

S

L

Ejqfp EU

2

2

22

22

22

212100

0

0

0

01

00

1

F

F

F

F

F

IEE

ILIL

ILIM

Jj

q

qL

Sq

SE

E


Normalized exciting

current

Normalized input

current

Normalized loop

inductance

Normalized output

inductance

E

S

q

L

E = 15 E = 27 E = 22

(L q) = (10 30)

25


25


(L q) = (10 30)

(L q) = (08 04)


Adiabatic-mode QFP

26



26



in AQFP change

adiabatically Ph

ase

diffe

ren

ce

s

Excitation flux

27



27


11000 of RSFQ

E

S

q

L

fEnergy dissipation


(L L)



28

Robust AQFP Design

(02 16)



(02 16)





29


29


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf


Damping

resistance



30



30


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf



31



31


Finite Temperatures


(L q) = (02 16) Ic = 50 mA




42 110 plusmn194

12 386 plusmn138

20 232 plusmn88


32


32




electronics




Future directions



Summary

33


33



Functionality

Speed

Energy consumption

Driving ability

Connectability

Robustness

Density

34


34


Excitation

Outputs

x2 = 05

(L q) = (02 16)

Ic = 50 mA

Iin1 = 5 mA

Lin = Lq kq = 03

35



35

Gain


If we assume



Ic dIin ~ 50


Iin ~ 20 mA Ic = 100 mA





36


36

Functionality



-



Buffer NOT



Majority a b c

x



37


37

Speed






119871119886119905119890119899119888119910 =119888119897119900119888119896 119901119890119903119894119900119889

119899119906119898119887119890119903 119900119891 119901ℎ119886119904119890


38


38

Energy Consumption




c is 1000 ps Ic = 50 mA


2 0rf

swcbit IE

F

ccc

swj

c

RI

00 2 F

F

Bit energy


39



39

Driving Ability



Fan-out 14 splitter


(STP2) was used

40

N


40

Connectability



Lmax ~ 1 mm

Iout vs Lwire



41


41

Robustness



42



42





Bias Current 360 mA

JJ number 83736




and inductances




43

Density


13times25 mm2


25times40 mm2

Excitation line

(upper layers)

Transformer

(lower layers)



Si Substrate

SiO 2

Nb JJ

Mo Resistor

AlOx

BAS (M2) ＧＣ

RC RC

JC

BC

COU (M3)

BAS (M2)

COU (M3)

CC CC

COU

CTL (M4) CTL (M4)

SiO 2


I1+I2+I3 +I4 (700 nm)

I5 (500 nm)

CC

CTL (M4)

CC

IN1 (100 nm)

Nb Pd - NW2 (40 nm + 40 nm) IN2 (100 nm)




~ 03M gatecm2

44


44




transformer can be



Schematic of an

AQFP buffer

15 mm x 20 mm


AIST HSTP process

MIT LL process

(SFQ5ee)


20 mm x 40 mm

45


45

Design Methodology



46

(

accbba

cbax

　　

MAJ (

ab

ba

bax

　　

　　

1MAJ azyx


Buffer 13-branch

NOT

1-constant


46


46


47





47


47

AQFP Logic Design


like Lego blocks


amp data flow

Inputs Phase 1

Phase 2

Phase 3

Phase 1

Phase 2

Phase 3

Phase 1

Outputs

Data

flo

w

AQFP design flow

48


48


49






49


Q Xu et al IEEE TAS 27 1301905 (2017)


49



50


50


Design Flow



ahead adder

12-bit instruction

decoder

Correct

operation

confirmed

1090 JJ

7100 JJ






51


51








~ 24 kBTjunction

5 GHz

52




52





5-GHz 4-phse

clock latency

~ 50 ps




Delay-line

clock latency

~ 5 ps

53


53







54


54



DGP HSTP


T Ando et al SUST 30 (2017) 075003

55



55




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66











Members in Overseas


6


6




electronics




Future directions



Summary

7


7

Background

httpwwwtop500org





gt 100 MW


K computer (Japan)



1 EFLOPS

8


8

AI is Power Hungry



httpswwwnvidiaco


Flops 346 GFLOPS


9


9



and die sizes

fchip = 1 GHz




10



10


Q = CLVDD

CMOS circuits

E = QVDD ~ 10-16 J

SFQ circuits

Ic

E = F0 Ic ~ 10-19 J

Φ0 = h(2e)




11


11



12


12





13


13




bull Power ~ nWgate



3215 (1999)




Josephson junction

400 mV

3 ps

14


14


Reduction of static

power is required


PD = F0Icf


PS = RbIc2

PD ~ PS20

15


15

DC Powered


PS ~ PD ~ IcF0f


PS ~ 0 PD ~ IcF0f

PS ~ 0 PD lt IcF0f

dt

dφ

2π

Ф0V

RB

J1

RS

IB

VB


109 103903 (2011)



ERSFQ (Hypres)

AC Powered

PS ~ 5PD PD ~ IcF0f


1053102 (2012)



26 035010 (2013)



16



17


17


SFQ Logic




Adiabatic QFP Logic


efficiency

1~10 zJoperation



18


18


1 mm

M9

M8

M7

M6M5M4M3M2

M1

Si Substrate

SiO2

Junction

Resistor



Main groundplane

Upper PTLs

Lower PTLs

DC power



clk

Op_and

Inv_x

Inv_y

C_out

Clk_outS0

S1S2

S3S4

S5S6

S7

Inpu

tO

utp

ut

Op_xor

Op_arith

Result

Input to SR_IN

AD

DA

DD

SU

B

SU

B


0 0

0 0

0 0

01 0

00 1

00

01

1 1

11

1 1

11 0

1 0

1 0

0 0

0 1

1

1111 1111 ndash 1111 1111 = 1 0000 0000

1010 1010 ndash 1001 1001 = 1 0001 0001

1111 1111 + 1111 1111 = 1 1111 1110

1010 1010 + 1001 1001 = 1 0100 0011

56 GHz



19


19




electronics




Future directions



Summary

20


20


Energy


E1

E2

Input energy E1

Output energy E2



switching errors

E1 gt 100 kBT

F0

Ib

21


21


Energy


E1

E2

Nonadiabatic

transition



F0

Ib

~ IbF0

22


22




23


23




Iout

E

Iout

E

Iout

E

t

Exciting

current

24


24


coscos2

2

)()( 22

qL

S

L

Ejqfp EU

2

2

22

22

22

212100

0

0

0

01

00

1

F

F

F

F

F

IEE

ILIL

ILIM

Jj

q

qL

Sq

SE

E


Normalized exciting

current

Normalized input

current

Normalized loop

inductance

Normalized output

inductance

E

S

q

L

E = 15 E = 27 E = 22

(L q) = (10 30)

25


25


(L q) = (10 30)

(L q) = (08 04)


Adiabatic-mode QFP

26



26



in AQFP change

adiabatically Ph

ase

diffe

ren

ce

s

Excitation flux

27



27


11000 of RSFQ

E

S

q

L

fEnergy dissipation


(L L)



28

Robust AQFP Design

(02 16)



(02 16)





29


29


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf


Damping

resistance



30



30


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf



31



31


Finite Temperatures


(L q) = (02 16) Ic = 50 mA




42 110 plusmn194

12 386 plusmn138

20 232 plusmn88


32


32




electronics




Future directions



Summary

33


33



Functionality

Speed

Energy consumption

Driving ability

Connectability

Robustness

Density

34


34


Excitation

Outputs

x2 = 05

(L q) = (02 16)

Ic = 50 mA

Iin1 = 5 mA

Lin = Lq kq = 03

35



35

Gain


If we assume



Ic dIin ~ 50


Iin ~ 20 mA Ic = 100 mA





36


36

Functionality



-



Buffer NOT



Majority a b c

x



37


37

Speed






119871119886119905119890119899119888119910 =119888119897119900119888119896 119901119890119903119894119900119889

119899119906119898119887119890119903 119900119891 119901ℎ119886119904119890


38


38

Energy Consumption




c is 1000 ps Ic = 50 mA


2 0rf

swcbit IE

F

ccc

swj

c

RI

00 2 F

F

Bit energy


39



39

Driving Ability



Fan-out 14 splitter


(STP2) was used

40

N


40

Connectability



Lmax ~ 1 mm

Iout vs Lwire



41


41

Robustness



42



42





Bias Current 360 mA

JJ number 83736




and inductances




43

Density


13times25 mm2


25times40 mm2

Excitation line

(upper layers)

Transformer

(lower layers)



Si Substrate

SiO 2

Nb JJ

Mo Resistor

AlOx

BAS (M2) ＧＣ

RC RC

JC

BC

COU (M3)

BAS (M2)

COU (M3)

CC CC

COU

CTL (M4) CTL (M4)

SiO 2


I1+I2+I3 +I4 (700 nm)

I5 (500 nm)

CC

CTL (M4)

CC

IN1 (100 nm)

Nb Pd - NW2 (40 nm + 40 nm) IN2 (100 nm)




~ 03M gatecm2

44


44




transformer can be



Schematic of an

AQFP buffer

15 mm x 20 mm


AIST HSTP process

MIT LL process

(SFQ5ee)


20 mm x 40 mm

45


45

Design Methodology



46

(

accbba

cbax

　　

MAJ (

ab

ba

bax

　　

　　

1MAJ azyx


Buffer 13-branch

NOT

1-constant


46


46


47





47


47

AQFP Logic Design


like Lego blocks


amp data flow

Inputs Phase 1

Phase 2

Phase 3

Phase 1

Phase 2

Phase 3

Phase 1

Outputs

Data

flo

w

AQFP design flow

48


48


49






49


Q Xu et al IEEE TAS 27 1301905 (2017)


49



50


50


Design Flow



ahead adder

12-bit instruction

decoder

Correct

operation

confirmed

1090 JJ

7100 JJ






51


51








~ 24 kBTjunction

5 GHz

52




52





5-GHz 4-phse

clock latency

~ 50 ps




Delay-line

clock latency

~ 5 ps

53


53







54


54



DGP HSTP


T Ando et al SUST 30 (2017) 075003

55



55




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66




electronics




Future directions



Summary

7


7

Background

httpwwwtop500org





gt 100 MW


K computer (Japan)



1 EFLOPS

8


8

AI is Power Hungry



httpswwwnvidiaco


Flops 346 GFLOPS


9


9



and die sizes

fchip = 1 GHz




10



10


Q = CLVDD

CMOS circuits

E = QVDD ~ 10-16 J

SFQ circuits

Ic

E = F0 Ic ~ 10-19 J

Φ0 = h(2e)




11


11



12


12





13


13




bull Power ~ nWgate



3215 (1999)




Josephson junction

400 mV

3 ps

14


14


Reduction of static

power is required


PD = F0Icf


PS = RbIc2

PD ~ PS20

15


15

DC Powered


PS ~ PD ~ IcF0f


PS ~ 0 PD ~ IcF0f

PS ~ 0 PD lt IcF0f

dt

dφ

2π

Ф0V

RB

J1

RS

IB

VB


109 103903 (2011)



ERSFQ (Hypres)

AC Powered

PS ~ 5PD PD ~ IcF0f


1053102 (2012)



26 035010 (2013)



16



17


17


SFQ Logic




Adiabatic QFP Logic


efficiency

1~10 zJoperation



18


18


1 mm

M9

M8

M7

M6M5M4M3M2

M1

Si Substrate

SiO2

Junction

Resistor



Main groundplane

Upper PTLs

Lower PTLs

DC power



clk

Op_and

Inv_x

Inv_y

C_out

Clk_outS0

S1S2

S3S4

S5S6

S7

Inpu

tO

utp

ut

Op_xor

Op_arith

Result

Input to SR_IN

AD

DA

DD

SU

B

SU

B


0 0

0 0

0 0

01 0

00 1

00

01

1 1

11

1 1

11 0

1 0

1 0

0 0

0 1

1

1111 1111 ndash 1111 1111 = 1 0000 0000

1010 1010 ndash 1001 1001 = 1 0001 0001

1111 1111 + 1111 1111 = 1 1111 1110

1010 1010 + 1001 1001 = 1 0100 0011

56 GHz



19


19




electronics




Future directions



Summary

20


20


Energy


E1

E2

Input energy E1

Output energy E2



switching errors

E1 gt 100 kBT

F0

Ib

21


21


Energy


E1

E2

Nonadiabatic

transition



F0

Ib

~ IbF0

22


22




23


23




Iout

E

Iout

E

Iout

E

t

Exciting

current

24


24


coscos2

2

)()( 22

qL

S

L

Ejqfp EU

2

2

22

22

22

212100

0

0

0

01

00

1

F

F

F

F

F

IEE

ILIL

ILIM

Jj

q

qL

Sq

SE

E


Normalized exciting

current

Normalized input

current

Normalized loop

inductance

Normalized output

inductance

E

S

q

L

E = 15 E = 27 E = 22

(L q) = (10 30)

25


25


(L q) = (10 30)

(L q) = (08 04)


Adiabatic-mode QFP

26



26



in AQFP change

adiabatically Ph

ase

diffe

ren

ce

s

Excitation flux

27



27


11000 of RSFQ

E

S

q

L

fEnergy dissipation


(L L)



28

Robust AQFP Design

(02 16)



(02 16)





29


29


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf


Damping

resistance



30



30


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf



31



31


Finite Temperatures


(L q) = (02 16) Ic = 50 mA




42 110 plusmn194

12 386 plusmn138

20 232 plusmn88


32


32




electronics




Future directions



Summary

33


33



Functionality

Speed

Energy consumption

Driving ability

Connectability

Robustness

Density

34


34


Excitation

Outputs

x2 = 05

(L q) = (02 16)

Ic = 50 mA

Iin1 = 5 mA

Lin = Lq kq = 03

35



35

Gain


If we assume



Ic dIin ~ 50


Iin ~ 20 mA Ic = 100 mA





36


36

Functionality



-



Buffer NOT



Majority a b c

x



37


37

Speed






119871119886119905119890119899119888119910 =119888119897119900119888119896 119901119890119903119894119900119889

119899119906119898119887119890119903 119900119891 119901ℎ119886119904119890


38


38

Energy Consumption




c is 1000 ps Ic = 50 mA


2 0rf

swcbit IE

F

ccc

swj

c

RI

00 2 F

F

Bit energy


39



39

Driving Ability



Fan-out 14 splitter


(STP2) was used

40

N


40

Connectability



Lmax ~ 1 mm

Iout vs Lwire



41


41

Robustness



42



42





Bias Current 360 mA

JJ number 83736




and inductances




43

Density


13times25 mm2


25times40 mm2

Excitation line

(upper layers)

Transformer

(lower layers)



Si Substrate

SiO 2

Nb JJ

Mo Resistor

AlOx

BAS (M2) ＧＣ

RC RC

JC

BC

COU (M3)

BAS (M2)

COU (M3)

CC CC

COU

CTL (M4) CTL (M4)

SiO 2


I1+I2+I3 +I4 (700 nm)

I5 (500 nm)

CC

CTL (M4)

CC

IN1 (100 nm)

Nb Pd - NW2 (40 nm + 40 nm) IN2 (100 nm)




~ 03M gatecm2

44


44




transformer can be



Schematic of an

AQFP buffer

15 mm x 20 mm


AIST HSTP process

MIT LL process

(SFQ5ee)


20 mm x 40 mm

45


45

Design Methodology



46

(

accbba

cbax

　　

MAJ (

ab

ba

bax

　　

　　

1MAJ azyx


Buffer 13-branch

NOT

1-constant


46


46


47





47


47

AQFP Logic Design


like Lego blocks


amp data flow

Inputs Phase 1

Phase 2

Phase 3

Phase 1

Phase 2

Phase 3

Phase 1

Outputs

Data

flo

w

AQFP design flow

48


48


49






49


Q Xu et al IEEE TAS 27 1301905 (2017)


49



50


50


Design Flow



ahead adder

12-bit instruction

decoder

Correct

operation

confirmed

1090 JJ

7100 JJ






51


51








~ 24 kBTjunction

5 GHz

52




52





5-GHz 4-phse

clock latency

~ 50 ps




Delay-line

clock latency

~ 5 ps

53


53







54


54



DGP HSTP


T Ando et al SUST 30 (2017) 075003

55



55




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66

Background

httpwwwtop500org





gt 100 MW


K computer (Japan)



1 EFLOPS

8


8

AI is Power Hungry



httpswwwnvidiaco


Flops 346 GFLOPS


9


9



and die sizes

fchip = 1 GHz




10



10


Q = CLVDD

CMOS circuits

E = QVDD ~ 10-16 J

SFQ circuits

Ic

E = F0 Ic ~ 10-19 J

Φ0 = h(2e)




11


11



12


12





13


13




bull Power ~ nWgate



3215 (1999)




Josephson junction

400 mV

3 ps

14


14


Reduction of static

power is required


PD = F0Icf


PS = RbIc2

PD ~ PS20

15


15

DC Powered


PS ~ PD ~ IcF0f


PS ~ 0 PD ~ IcF0f

PS ~ 0 PD lt IcF0f

dt

dφ

2π

Ф0V

RB

J1

RS

IB

VB


109 103903 (2011)



ERSFQ (Hypres)

AC Powered

PS ~ 5PD PD ~ IcF0f


1053102 (2012)



26 035010 (2013)



16



17


17


SFQ Logic




Adiabatic QFP Logic


efficiency

1~10 zJoperation



18


18


1 mm

M9

M8

M7

M6M5M4M3M2

M1

Si Substrate

SiO2

Junction

Resistor



Main groundplane

Upper PTLs

Lower PTLs

DC power



clk

Op_and

Inv_x

Inv_y

C_out

Clk_outS0

S1S2

S3S4

S5S6

S7

Inpu

tO

utp

ut

Op_xor

Op_arith

Result

Input to SR_IN

AD

DA

DD

SU

B

SU

B


0 0

0 0

0 0

01 0

00 1

00

01

1 1

11

1 1

11 0

1 0

1 0

0 0

0 1

1

1111 1111 ndash 1111 1111 = 1 0000 0000

1010 1010 ndash 1001 1001 = 1 0001 0001

1111 1111 + 1111 1111 = 1 1111 1110

1010 1010 + 1001 1001 = 1 0100 0011

56 GHz



19


19




electronics




Future directions



Summary

20


20


Energy


E1

E2

Input energy E1

Output energy E2



switching errors

E1 gt 100 kBT

F0

Ib

21


21


Energy


E1

E2

Nonadiabatic

transition



F0

Ib

~ IbF0

22


22




23


23




Iout

E

Iout

E

Iout

E

t

Exciting

current

24


24


coscos2

2

)()( 22

qL

S

L

Ejqfp EU

2

2

22

22

22

212100

0

0

0

01

00

1

F

F

F

F

F

IEE

ILIL

ILIM

Jj

q

qL

Sq

SE

E


Normalized exciting

current

Normalized input

current

Normalized loop

inductance

Normalized output

inductance

E

S

q

L

E = 15 E = 27 E = 22

(L q) = (10 30)

25


25


(L q) = (10 30)

(L q) = (08 04)


Adiabatic-mode QFP

26



26



in AQFP change

adiabatically Ph

ase

diffe

ren

ce

s

Excitation flux

27



27


11000 of RSFQ

E

S

q

L

fEnergy dissipation


(L L)



28

Robust AQFP Design

(02 16)



(02 16)





29


29


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf


Damping

resistance



30



30


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf



31



31


Finite Temperatures


(L q) = (02 16) Ic = 50 mA




42 110 plusmn194

12 386 plusmn138

20 232 plusmn88


32


32




electronics




Future directions



Summary

33


33



Functionality

Speed

Energy consumption

Driving ability

Connectability

Robustness

Density

34


34


Excitation

Outputs

x2 = 05

(L q) = (02 16)

Ic = 50 mA

Iin1 = 5 mA

Lin = Lq kq = 03

35



35

Gain


If we assume



Ic dIin ~ 50


Iin ~ 20 mA Ic = 100 mA





36


36

Functionality



-



Buffer NOT



Majority a b c

x



37


37

Speed






119871119886119905119890119899119888119910 =119888119897119900119888119896 119901119890119903119894119900119889

119899119906119898119887119890119903 119900119891 119901ℎ119886119904119890


38


38

Energy Consumption




c is 1000 ps Ic = 50 mA


2 0rf

swcbit IE

F

ccc

swj

c

RI

00 2 F

F

Bit energy


39



39

Driving Ability



Fan-out 14 splitter


(STP2) was used

40

N


40

Connectability



Lmax ~ 1 mm

Iout vs Lwire



41


41

Robustness



42



42





Bias Current 360 mA

JJ number 83736




and inductances




43

Density


13times25 mm2


25times40 mm2

Excitation line

(upper layers)

Transformer

(lower layers)



Si Substrate

SiO 2

Nb JJ

Mo Resistor

AlOx

BAS (M2) ＧＣ

RC RC

JC

BC

COU (M3)

BAS (M2)

COU (M3)

CC CC

COU

CTL (M4) CTL (M4)

SiO 2


I1+I2+I3 +I4 (700 nm)

I5 (500 nm)

CC

CTL (M4)

CC

IN1 (100 nm)

Nb Pd - NW2 (40 nm + 40 nm) IN2 (100 nm)




~ 03M gatecm2

44


44




transformer can be



Schematic of an

AQFP buffer

15 mm x 20 mm


AIST HSTP process

MIT LL process

(SFQ5ee)


20 mm x 40 mm

45


45

Design Methodology



46

(

accbba

cbax

　　

MAJ (

ab

ba

bax

　　

　　

1MAJ azyx


Buffer 13-branch

NOT

1-constant


46


46


47





47


47

AQFP Logic Design


like Lego blocks


amp data flow

Inputs Phase 1

Phase 2

Phase 3

Phase 1

Phase 2

Phase 3

Phase 1

Outputs

Data

flo

w

AQFP design flow

48


48


49






49


Q Xu et al IEEE TAS 27 1301905 (2017)


49



50


50


Design Flow



ahead adder

12-bit instruction

decoder

Correct

operation

confirmed

1090 JJ

7100 JJ






51


51








~ 24 kBTjunction

5 GHz

52




52





5-GHz 4-phse

clock latency

~ 50 ps




Delay-line

clock latency

~ 5 ps

53


53







54


54



DGP HSTP


T Ando et al SUST 30 (2017) 075003

55



55




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66

AI is Power Hungry



httpswwwnvidiaco


Flops 346 GFLOPS


9


9



and die sizes

fchip = 1 GHz




10



10


Q = CLVDD

CMOS circuits

E = QVDD ~ 10-16 J

SFQ circuits

Ic

E = F0 Ic ~ 10-19 J

Φ0 = h(2e)




11


11



12


12





13


13




bull Power ~ nWgate



3215 (1999)




Josephson junction

400 mV

3 ps

14


14


Reduction of static

power is required


PD = F0Icf


PS = RbIc2

PD ~ PS20

15


15

DC Powered


PS ~ PD ~ IcF0f


PS ~ 0 PD ~ IcF0f

PS ~ 0 PD lt IcF0f

dt

dφ

2π

Ф0V

RB

J1

RS

IB

VB


109 103903 (2011)



ERSFQ (Hypres)

AC Powered

PS ~ 5PD PD ~ IcF0f


1053102 (2012)



26 035010 (2013)



16



17


17


SFQ Logic




Adiabatic QFP Logic


efficiency

1~10 zJoperation



18


18


1 mm

M9

M8

M7

M6M5M4M3M2

M1

Si Substrate

SiO2

Junction

Resistor



Main groundplane

Upper PTLs

Lower PTLs

DC power



clk

Op_and

Inv_x

Inv_y

C_out

Clk_outS0

S1S2

S3S4

S5S6

S7

Inpu

tO

utp

ut

Op_xor

Op_arith

Result

Input to SR_IN

AD

DA

DD

SU

B

SU

B


0 0

0 0

0 0

01 0

00 1

00

01

1 1

11

1 1

11 0

1 0

1 0

0 0

0 1

1

1111 1111 ndash 1111 1111 = 1 0000 0000

1010 1010 ndash 1001 1001 = 1 0001 0001

1111 1111 + 1111 1111 = 1 1111 1110

1010 1010 + 1001 1001 = 1 0100 0011

56 GHz



19


19




electronics




Future directions



Summary

20


20


Energy


E1

E2

Input energy E1

Output energy E2



switching errors

E1 gt 100 kBT

F0

Ib

21


21


Energy


E1

E2

Nonadiabatic

transition



F0

Ib

~ IbF0

22


22




23


23




Iout

E

Iout

E

Iout

E

t

Exciting

current

24


24


coscos2

2

)()( 22

qL

S

L

Ejqfp EU

2

2

22

22

22

212100

0

0

0

01

00

1

F

F

F

F

F

IEE

ILIL

ILIM

Jj

q

qL

Sq

SE

E


Normalized exciting

current

Normalized input

current

Normalized loop

inductance

Normalized output

inductance

E

S

q

L

E = 15 E = 27 E = 22

(L q) = (10 30)

25


25


(L q) = (10 30)

(L q) = (08 04)


Adiabatic-mode QFP

26



26



in AQFP change

adiabatically Ph

ase

diffe

ren

ce

s

Excitation flux

27



27


11000 of RSFQ

E

S

q

L

fEnergy dissipation


(L L)



28

Robust AQFP Design

(02 16)



(02 16)





29


29


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf


Damping

resistance



30



30


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf



31



31


Finite Temperatures


(L q) = (02 16) Ic = 50 mA




42 110 plusmn194

12 386 plusmn138

20 232 plusmn88


32


32




electronics




Future directions



Summary

33


33



Functionality

Speed

Energy consumption

Driving ability

Connectability

Robustness

Density

34


34


Excitation

Outputs

x2 = 05

(L q) = (02 16)

Ic = 50 mA

Iin1 = 5 mA

Lin = Lq kq = 03

35



35

Gain


If we assume



Ic dIin ~ 50


Iin ~ 20 mA Ic = 100 mA





36


36

Functionality



-



Buffer NOT



Majority a b c

x



37


37

Speed






119871119886119905119890119899119888119910 =119888119897119900119888119896 119901119890119903119894119900119889

119899119906119898119887119890119903 119900119891 119901ℎ119886119904119890


38


38

Energy Consumption




c is 1000 ps Ic = 50 mA


2 0rf

swcbit IE

F

ccc

swj

c

RI

00 2 F

F

Bit energy


39



39

Driving Ability



Fan-out 14 splitter


(STP2) was used

40

N


40

Connectability



Lmax ~ 1 mm

Iout vs Lwire



41


41

Robustness



42



42





Bias Current 360 mA

JJ number 83736




and inductances




43

Density


13times25 mm2


25times40 mm2

Excitation line

(upper layers)

Transformer

(lower layers)



Si Substrate

SiO 2

Nb JJ

Mo Resistor

AlOx

BAS (M2) ＧＣ

RC RC

JC

BC

COU (M3)

BAS (M2)

COU (M3)

CC CC

COU

CTL (M4) CTL (M4)

SiO 2


I1+I2+I3 +I4 (700 nm)

I5 (500 nm)

CC

CTL (M4)

CC

IN1 (100 nm)

Nb Pd - NW2 (40 nm + 40 nm) IN2 (100 nm)




~ 03M gatecm2

44


44




transformer can be



Schematic of an

AQFP buffer

15 mm x 20 mm


AIST HSTP process

MIT LL process

(SFQ5ee)


20 mm x 40 mm

45


45

Design Methodology



46

(

accbba

cbax

　　

MAJ (

ab

ba

bax

　　

　　

1MAJ azyx


Buffer 13-branch

NOT

1-constant


46


46


47





47


47

AQFP Logic Design


like Lego blocks


amp data flow

Inputs Phase 1

Phase 2

Phase 3

Phase 1

Phase 2

Phase 3

Phase 1

Outputs

Data

flo

w

AQFP design flow

48


48


49






49


Q Xu et al IEEE TAS 27 1301905 (2017)


49



50


50


Design Flow



ahead adder

12-bit instruction

decoder

Correct

operation

confirmed

1090 JJ

7100 JJ






51


51








~ 24 kBTjunction

5 GHz

52




52





5-GHz 4-phse

clock latency

~ 50 ps




Delay-line

clock latency

~ 5 ps

53


53







54


54



DGP HSTP


T Ando et al SUST 30 (2017) 075003

55



55




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66



and die sizes

fchip = 1 GHz




10



10


Q = CLVDD

CMOS circuits

E = QVDD ~ 10-16 J

SFQ circuits

Ic

E = F0 Ic ~ 10-19 J

Φ0 = h(2e)




11


11



12


12





13


13




bull Power ~ nWgate



3215 (1999)




Josephson junction

400 mV

3 ps

14


14


Reduction of static

power is required


PD = F0Icf


PS = RbIc2

PD ~ PS20

15


15

DC Powered


PS ~ PD ~ IcF0f


PS ~ 0 PD ~ IcF0f

PS ~ 0 PD lt IcF0f

dt

dφ

2π

Ф0V

RB

J1

RS

IB

VB


109 103903 (2011)



ERSFQ (Hypres)

AC Powered

PS ~ 5PD PD ~ IcF0f


1053102 (2012)



26 035010 (2013)



16



17


17


SFQ Logic




Adiabatic QFP Logic


efficiency

1~10 zJoperation



18


18


1 mm

M9

M8

M7

M6M5M4M3M2

M1

Si Substrate

SiO2

Junction

Resistor



Main groundplane

Upper PTLs

Lower PTLs

DC power



clk

Op_and

Inv_x

Inv_y

C_out

Clk_outS0

S1S2

S3S4

S5S6

S7

Inpu

tO

utp

ut

Op_xor

Op_arith

Result

Input to SR_IN

AD

DA

DD

SU

B

SU

B


0 0

0 0

0 0

01 0

00 1

00

01

1 1

11

1 1

11 0

1 0

1 0

0 0

0 1

1

1111 1111 ndash 1111 1111 = 1 0000 0000

1010 1010 ndash 1001 1001 = 1 0001 0001

1111 1111 + 1111 1111 = 1 1111 1110

1010 1010 + 1001 1001 = 1 0100 0011

56 GHz



19


19




electronics




Future directions



Summary

20


20


Energy


E1

E2

Input energy E1

Output energy E2



switching errors

E1 gt 100 kBT

F0

Ib

21


21


Energy


E1

E2

Nonadiabatic

transition



F0

Ib

~ IbF0

22


22




23


23




Iout

E

Iout

E

Iout

E

t

Exciting

current

24


24


coscos2

2

)()( 22

qL

S

L

Ejqfp EU

2

2

22

22

22

212100

0

0

0

01

00

1

F

F

F

F

F

IEE

ILIL

ILIM

Jj

q

qL

Sq

SE

E


Normalized exciting

current

Normalized input

current

Normalized loop

inductance

Normalized output

inductance

E

S

q

L

E = 15 E = 27 E = 22

(L q) = (10 30)

25


25


(L q) = (10 30)

(L q) = (08 04)


Adiabatic-mode QFP

26



26



in AQFP change

adiabatically Ph

ase

diffe

ren

ce

s

Excitation flux

27



27


11000 of RSFQ

E

S

q

L

fEnergy dissipation


(L L)



28

Robust AQFP Design

(02 16)



(02 16)





29


29


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf


Damping

resistance



30



30


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf



31



31


Finite Temperatures


(L q) = (02 16) Ic = 50 mA




42 110 plusmn194

12 386 plusmn138

20 232 plusmn88


32


32




electronics




Future directions



Summary

33


33



Functionality

Speed

Energy consumption

Driving ability

Connectability

Robustness

Density

34


34


Excitation

Outputs

x2 = 05

(L q) = (02 16)

Ic = 50 mA

Iin1 = 5 mA

Lin = Lq kq = 03

35



35

Gain


If we assume



Ic dIin ~ 50


Iin ~ 20 mA Ic = 100 mA





36


36

Functionality



-



Buffer NOT



Majority a b c

x



37


37

Speed






119871119886119905119890119899119888119910 =119888119897119900119888119896 119901119890119903119894119900119889

119899119906119898119887119890119903 119900119891 119901ℎ119886119904119890


38


38

Energy Consumption




c is 1000 ps Ic = 50 mA


2 0rf

swcbit IE

F

ccc

swj

c

RI

00 2 F

F

Bit energy


39



39

Driving Ability



Fan-out 14 splitter


(STP2) was used

40

N


40

Connectability



Lmax ~ 1 mm

Iout vs Lwire



41


41

Robustness



42



42





Bias Current 360 mA

JJ number 83736




and inductances




43

Density


13times25 mm2


25times40 mm2

Excitation line

(upper layers)

Transformer

(lower layers)



Si Substrate

SiO 2

Nb JJ

Mo Resistor

AlOx

BAS (M2) ＧＣ

RC RC

JC

BC

COU (M3)

BAS (M2)

COU (M3)

CC CC

COU

CTL (M4) CTL (M4)

SiO 2


I1+I2+I3 +I4 (700 nm)

I5 (500 nm)

CC

CTL (M4)

CC

IN1 (100 nm)

Nb Pd - NW2 (40 nm + 40 nm) IN2 (100 nm)




~ 03M gatecm2

44


44




transformer can be



Schematic of an

AQFP buffer

15 mm x 20 mm


AIST HSTP process

MIT LL process

(SFQ5ee)


20 mm x 40 mm

45


45

Design Methodology



46

(

accbba

cbax

　　

MAJ (

ab

ba

bax

　　

　　

1MAJ azyx


Buffer 13-branch

NOT

1-constant


46


46


47





47


47

AQFP Logic Design


like Lego blocks


amp data flow

Inputs Phase 1

Phase 2

Phase 3

Phase 1

Phase 2

Phase 3

Phase 1

Outputs

Data

flo

w

AQFP design flow

48


48


49






49


Q Xu et al IEEE TAS 27 1301905 (2017)


49



50


50


Design Flow



ahead adder

12-bit instruction

decoder

Correct

operation

confirmed

1090 JJ

7100 JJ






51


51








~ 24 kBTjunction

5 GHz

52




52





5-GHz 4-phse

clock latency

~ 50 ps




Delay-line

clock latency

~ 5 ps

53


53







54


54



DGP HSTP


T Ando et al SUST 30 (2017) 075003

55



55




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66


Q = CLVDD

CMOS circuits

E = QVDD ~ 10-16 J

SFQ circuits

Ic

E = F0 Ic ~ 10-19 J

Φ0 = h(2e)




11


11



12


12





13


13




bull Power ~ nWgate



3215 (1999)




Josephson junction

400 mV

3 ps

14


14


Reduction of static

power is required


PD = F0Icf


PS = RbIc2

PD ~ PS20

15


15

DC Powered


PS ~ PD ~ IcF0f


PS ~ 0 PD ~ IcF0f

PS ~ 0 PD lt IcF0f

dt

dφ

2π

Ф0V

RB

J1

RS

IB

VB


109 103903 (2011)



ERSFQ (Hypres)

AC Powered

PS ~ 5PD PD ~ IcF0f


1053102 (2012)



26 035010 (2013)



16



17


17


SFQ Logic




Adiabatic QFP Logic


efficiency

1~10 zJoperation



18


18


1 mm

M9

M8

M7

M6M5M4M3M2

M1

Si Substrate

SiO2

Junction

Resistor



Main groundplane

Upper PTLs

Lower PTLs

DC power



clk

Op_and

Inv_x

Inv_y

C_out

Clk_outS0

S1S2

S3S4

S5S6

S7

Inpu

tO

utp

ut

Op_xor

Op_arith

Result

Input to SR_IN

AD

DA

DD

SU

B

SU

B


0 0

0 0

0 0

01 0

00 1

00

01

1 1

11

1 1

11 0

1 0

1 0

0 0

0 1

1

1111 1111 ndash 1111 1111 = 1 0000 0000

1010 1010 ndash 1001 1001 = 1 0001 0001

1111 1111 + 1111 1111 = 1 1111 1110

1010 1010 + 1001 1001 = 1 0100 0011

56 GHz



19


19




electronics




Future directions



Summary

20


20


Energy


E1

E2

Input energy E1

Output energy E2



switching errors

E1 gt 100 kBT

F0

Ib

21


21


Energy


E1

E2

Nonadiabatic

transition



F0

Ib

~ IbF0

22


22




23


23




Iout

E

Iout

E

Iout

E

t

Exciting

current

24


24


coscos2

2

)()( 22

qL

S

L

Ejqfp EU

2

2

22

22

22

212100

0

0

0

01

00

1

F

F

F

F

F

IEE

ILIL

ILIM

Jj

q

qL

Sq

SE

E


Normalized exciting

current

Normalized input

current

Normalized loop

inductance

Normalized output

inductance

E

S

q

L

E = 15 E = 27 E = 22

(L q) = (10 30)

25


25


(L q) = (10 30)

(L q) = (08 04)


Adiabatic-mode QFP

26



26



in AQFP change

adiabatically Ph

ase

diffe

ren

ce

s

Excitation flux

27



27


11000 of RSFQ

E

S

q

L

fEnergy dissipation


(L L)



28

Robust AQFP Design

(02 16)



(02 16)





29


29


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf


Damping

resistance



30



30


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf



31



31


Finite Temperatures


(L q) = (02 16) Ic = 50 mA




42 110 plusmn194

12 386 plusmn138

20 232 plusmn88


32


32




electronics




Future directions



Summary

33


33



Functionality

Speed

Energy consumption

Driving ability

Connectability

Robustness

Density

34


34


Excitation

Outputs

x2 = 05

(L q) = (02 16)

Ic = 50 mA

Iin1 = 5 mA

Lin = Lq kq = 03

35



35

Gain


If we assume



Ic dIin ~ 50


Iin ~ 20 mA Ic = 100 mA





36


36

Functionality



-



Buffer NOT



Majority a b c

x



37


37

Speed






119871119886119905119890119899119888119910 =119888119897119900119888119896 119901119890119903119894119900119889

119899119906119898119887119890119903 119900119891 119901ℎ119886119904119890


38


38

Energy Consumption




c is 1000 ps Ic = 50 mA


2 0rf

swcbit IE

F

ccc

swj

c

RI

00 2 F

F

Bit energy


39



39

Driving Ability



Fan-out 14 splitter


(STP2) was used

40

N


40

Connectability



Lmax ~ 1 mm

Iout vs Lwire



41


41

Robustness



42



42





Bias Current 360 mA

JJ number 83736




and inductances




43

Density


13times25 mm2


25times40 mm2

Excitation line

(upper layers)

Transformer

(lower layers)



Si Substrate

SiO 2

Nb JJ

Mo Resistor

AlOx

BAS (M2) ＧＣ

RC RC

JC

BC

COU (M3)

BAS (M2)

COU (M3)

CC CC

COU

CTL (M4) CTL (M4)

SiO 2


I1+I2+I3 +I4 (700 nm)

I5 (500 nm)

CC

CTL (M4)

CC

IN1 (100 nm)

Nb Pd - NW2 (40 nm + 40 nm) IN2 (100 nm)




~ 03M gatecm2

44


44




transformer can be



Schematic of an

AQFP buffer

15 mm x 20 mm


AIST HSTP process

MIT LL process

(SFQ5ee)


20 mm x 40 mm

45


45

Design Methodology



46

(

accbba

cbax

　　

MAJ (

ab

ba

bax

　　

　　

1MAJ azyx


Buffer 13-branch

NOT

1-constant


46


46


47





47


47

AQFP Logic Design


like Lego blocks


amp data flow

Inputs Phase 1

Phase 2

Phase 3

Phase 1

Phase 2

Phase 3

Phase 1

Outputs

Data

flo

w

AQFP design flow

48


48


49






49


Q Xu et al IEEE TAS 27 1301905 (2017)


49



50


50


Design Flow



ahead adder

12-bit instruction

decoder

Correct

operation

confirmed

1090 JJ

7100 JJ






51


51








~ 24 kBTjunction

5 GHz

52




52





5-GHz 4-phse

clock latency

~ 50 ps




Delay-line

clock latency

~ 5 ps

53


53







54


54



DGP HSTP


T Ando et al SUST 30 (2017) 075003

55



55




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66



12


12





13


13




bull Power ~ nWgate



3215 (1999)




Josephson junction

400 mV

3 ps

14


14


Reduction of static

power is required


PD = F0Icf


PS = RbIc2

PD ~ PS20

15


15

DC Powered


PS ~ PD ~ IcF0f


PS ~ 0 PD ~ IcF0f

PS ~ 0 PD lt IcF0f

dt

dφ

2π

Ф0V

RB

J1

RS

IB

VB


109 103903 (2011)



ERSFQ (Hypres)

AC Powered

PS ~ 5PD PD ~ IcF0f


1053102 (2012)



26 035010 (2013)



16



17


17


SFQ Logic




Adiabatic QFP Logic


efficiency

1~10 zJoperation



18


18


1 mm

M9

M8

M7

M6M5M4M3M2

M1

Si Substrate

SiO2

Junction

Resistor



Main groundplane

Upper PTLs

Lower PTLs

DC power



clk

Op_and

Inv_x

Inv_y

C_out

Clk_outS0

S1S2

S3S4

S5S6

S7

Inpu

tO

utp

ut

Op_xor

Op_arith

Result

Input to SR_IN

AD

DA

DD

SU

B

SU

B


0 0

0 0

0 0

01 0

00 1

00

01

1 1

11

1 1

11 0

1 0

1 0

0 0

0 1

1

1111 1111 ndash 1111 1111 = 1 0000 0000

1010 1010 ndash 1001 1001 = 1 0001 0001

1111 1111 + 1111 1111 = 1 1111 1110

1010 1010 + 1001 1001 = 1 0100 0011

56 GHz



19


19




electronics




Future directions



Summary

20


20


Energy


E1

E2

Input energy E1

Output energy E2



switching errors

E1 gt 100 kBT

F0

Ib

21


21


Energy


E1

E2

Nonadiabatic

transition



F0

Ib

~ IbF0

22


22




23


23




Iout

E

Iout

E

Iout

E

t

Exciting

current

24


24


coscos2

2

)()( 22

qL

S

L

Ejqfp EU

2

2

22

22

22

212100

0

0

0

01

00

1

F

F

F

F

F

IEE

ILIL

ILIM

Jj

q

qL

Sq

SE

E


Normalized exciting

current

Normalized input

current

Normalized loop

inductance

Normalized output

inductance

E

S

q

L

E = 15 E = 27 E = 22

(L q) = (10 30)

25


25


(L q) = (10 30)

(L q) = (08 04)


Adiabatic-mode QFP

26



26



in AQFP change

adiabatically Ph

ase

diffe

ren

ce

s

Excitation flux

27



27


11000 of RSFQ

E

S

q

L

fEnergy dissipation


(L L)



28

Robust AQFP Design

(02 16)



(02 16)





29


29


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf


Damping

resistance



30



30


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf



31



31


Finite Temperatures


(L q) = (02 16) Ic = 50 mA




42 110 plusmn194

12 386 plusmn138

20 232 plusmn88


32


32




electronics




Future directions



Summary

33


33



Functionality

Speed

Energy consumption

Driving ability

Connectability

Robustness

Density

34


34


Excitation

Outputs

x2 = 05

(L q) = (02 16)

Ic = 50 mA

Iin1 = 5 mA

Lin = Lq kq = 03

35



35

Gain


If we assume



Ic dIin ~ 50


Iin ~ 20 mA Ic = 100 mA





36


36

Functionality



-



Buffer NOT



Majority a b c

x



37


37

Speed






119871119886119905119890119899119888119910 =119888119897119900119888119896 119901119890119903119894119900119889

119899119906119898119887119890119903 119900119891 119901ℎ119886119904119890


38


38

Energy Consumption




c is 1000 ps Ic = 50 mA


2 0rf

swcbit IE

F

ccc

swj

c

RI

00 2 F

F

Bit energy


39



39

Driving Ability



Fan-out 14 splitter


(STP2) was used

40

N


40

Connectability



Lmax ~ 1 mm

Iout vs Lwire



41


41

Robustness



42



42





Bias Current 360 mA

JJ number 83736




and inductances




43

Density


13times25 mm2


25times40 mm2

Excitation line

(upper layers)

Transformer

(lower layers)



Si Substrate

SiO 2

Nb JJ

Mo Resistor

AlOx

BAS (M2) ＧＣ

RC RC

JC

BC

COU (M3)

BAS (M2)

COU (M3)

CC CC

COU

CTL (M4) CTL (M4)

SiO 2


I1+I2+I3 +I4 (700 nm)

I5 (500 nm)

CC

CTL (M4)

CC

IN1 (100 nm)

Nb Pd - NW2 (40 nm + 40 nm) IN2 (100 nm)




~ 03M gatecm2

44


44




transformer can be



Schematic of an

AQFP buffer

15 mm x 20 mm


AIST HSTP process

MIT LL process

(SFQ5ee)


20 mm x 40 mm

45


45

Design Methodology



46

(

accbba

cbax

　　

MAJ (

ab

ba

bax

　　

　　

1MAJ azyx


Buffer 13-branch

NOT

1-constant


46


46


47





47


47

AQFP Logic Design


like Lego blocks


amp data flow

Inputs Phase 1

Phase 2

Phase 3

Phase 1

Phase 2

Phase 3

Phase 1

Outputs

Data

flo

w

AQFP design flow

48


48


49






49


Q Xu et al IEEE TAS 27 1301905 (2017)


49



50


50


Design Flow



ahead adder

12-bit instruction

decoder

Correct

operation

confirmed

1090 JJ

7100 JJ






51


51








~ 24 kBTjunction

5 GHz

52




52





5-GHz 4-phse

clock latency

~ 50 ps




Delay-line

clock latency

~ 5 ps

53


53







54


54



DGP HSTP


T Ando et al SUST 30 (2017) 075003

55



55




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66





13


13




bull Power ~ nWgate



3215 (1999)




Josephson junction

400 mV

3 ps

14


14


Reduction of static

power is required


PD = F0Icf


PS = RbIc2

PD ~ PS20

15


15

DC Powered


PS ~ PD ~ IcF0f


PS ~ 0 PD ~ IcF0f

PS ~ 0 PD lt IcF0f

dt

dφ

2π

Ф0V

RB

J1

RS

IB

VB


109 103903 (2011)



ERSFQ (Hypres)

AC Powered

PS ~ 5PD PD ~ IcF0f


1053102 (2012)



26 035010 (2013)



16



17


17


SFQ Logic




Adiabatic QFP Logic


efficiency

1~10 zJoperation



18


18


1 mm

M9

M8

M7

M6M5M4M3M2

M1

Si Substrate

SiO2

Junction

Resistor



Main groundplane

Upper PTLs

Lower PTLs

DC power



clk

Op_and

Inv_x

Inv_y

C_out

Clk_outS0

S1S2

S3S4

S5S6

S7

Inpu

tO

utp

ut

Op_xor

Op_arith

Result

Input to SR_IN

AD

DA

DD

SU

B

SU

B


0 0

0 0

0 0

01 0

00 1

00

01

1 1

11

1 1

11 0

1 0

1 0

0 0

0 1

1

1111 1111 ndash 1111 1111 = 1 0000 0000

1010 1010 ndash 1001 1001 = 1 0001 0001

1111 1111 + 1111 1111 = 1 1111 1110

1010 1010 + 1001 1001 = 1 0100 0011

56 GHz



19


19




electronics




Future directions



Summary

20


20


Energy


E1

E2

Input energy E1

Output energy E2



switching errors

E1 gt 100 kBT

F0

Ib

21


21


Energy


E1

E2

Nonadiabatic

transition



F0

Ib

~ IbF0

22


22




23


23




Iout

E

Iout

E

Iout

E

t

Exciting

current

24


24


coscos2

2

)()( 22

qL

S

L

Ejqfp EU

2

2

22

22

22

212100

0

0

0

01

00

1

F

F

F

F

F

IEE

ILIL

ILIM

Jj

q

qL

Sq

SE

E


Normalized exciting

current

Normalized input

current

Normalized loop

inductance

Normalized output

inductance

E

S

q

L

E = 15 E = 27 E = 22

(L q) = (10 30)

25


25


(L q) = (10 30)

(L q) = (08 04)


Adiabatic-mode QFP

26



26



in AQFP change

adiabatically Ph

ase

diffe

ren

ce

s

Excitation flux

27



27


11000 of RSFQ

E

S

q

L

fEnergy dissipation


(L L)



28

Robust AQFP Design

(02 16)



(02 16)





29


29


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf


Damping

resistance



30



30


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf



31



31


Finite Temperatures


(L q) = (02 16) Ic = 50 mA




42 110 plusmn194

12 386 plusmn138

20 232 plusmn88


32


32




electronics




Future directions



Summary

33


33



Functionality

Speed

Energy consumption

Driving ability

Connectability

Robustness

Density

34


34


Excitation

Outputs

x2 = 05

(L q) = (02 16)

Ic = 50 mA

Iin1 = 5 mA

Lin = Lq kq = 03

35



35

Gain


If we assume



Ic dIin ~ 50


Iin ~ 20 mA Ic = 100 mA





36


36

Functionality



-



Buffer NOT



Majority a b c

x



37


37

Speed






119871119886119905119890119899119888119910 =119888119897119900119888119896 119901119890119903119894119900119889

119899119906119898119887119890119903 119900119891 119901ℎ119886119904119890


38


38

Energy Consumption




c is 1000 ps Ic = 50 mA


2 0rf

swcbit IE

F

ccc

swj

c

RI

00 2 F

F

Bit energy


39



39

Driving Ability



Fan-out 14 splitter


(STP2) was used

40

N


40

Connectability



Lmax ~ 1 mm

Iout vs Lwire



41


41

Robustness



42



42





Bias Current 360 mA

JJ number 83736




and inductances




43

Density


13times25 mm2


25times40 mm2

Excitation line

(upper layers)

Transformer

(lower layers)



Si Substrate

SiO 2

Nb JJ

Mo Resistor

AlOx

BAS (M2) ＧＣ

RC RC

JC

BC

COU (M3)

BAS (M2)

COU (M3)

CC CC

COU

CTL (M4) CTL (M4)

SiO 2


I1+I2+I3 +I4 (700 nm)

I5 (500 nm)

CC

CTL (M4)

CC

IN1 (100 nm)

Nb Pd - NW2 (40 nm + 40 nm) IN2 (100 nm)




~ 03M gatecm2

44


44




transformer can be



Schematic of an

AQFP buffer

15 mm x 20 mm


AIST HSTP process

MIT LL process

(SFQ5ee)


20 mm x 40 mm

45


45

Design Methodology



46

(

accbba

cbax

　　

MAJ (

ab

ba

bax

　　

　　

1MAJ azyx


Buffer 13-branch

NOT

1-constant


46


46


47





47


47

AQFP Logic Design


like Lego blocks


amp data flow

Inputs Phase 1

Phase 2

Phase 3

Phase 1

Phase 2

Phase 3

Phase 1

Outputs

Data

flo

w

AQFP design flow

48


48


49






49


Q Xu et al IEEE TAS 27 1301905 (2017)


49



50


50


Design Flow



ahead adder

12-bit instruction

decoder

Correct

operation

confirmed

1090 JJ

7100 JJ






51


51








~ 24 kBTjunction

5 GHz

52




52





5-GHz 4-phse

clock latency

~ 50 ps




Delay-line

clock latency

~ 5 ps

53


53







54


54



DGP HSTP


T Ando et al SUST 30 (2017) 075003

55



55




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66




bull Power ~ nWgate



3215 (1999)




Josephson junction

400 mV

3 ps

14


14


Reduction of static

power is required


PD = F0Icf


PS = RbIc2

PD ~ PS20

15


15

DC Powered


PS ~ PD ~ IcF0f


PS ~ 0 PD ~ IcF0f

PS ~ 0 PD lt IcF0f

dt

dφ

2π

Ф0V

RB

J1

RS

IB

VB


109 103903 (2011)



ERSFQ (Hypres)

AC Powered

PS ~ 5PD PD ~ IcF0f


1053102 (2012)



26 035010 (2013)



16



17


17


SFQ Logic




Adiabatic QFP Logic


efficiency

1~10 zJoperation



18


18


1 mm

M9

M8

M7

M6M5M4M3M2

M1

Si Substrate

SiO2

Junction

Resistor



Main groundplane

Upper PTLs

Lower PTLs

DC power



clk

Op_and

Inv_x

Inv_y

C_out

Clk_outS0

S1S2

S3S4

S5S6

S7

Inpu

tO

utp

ut

Op_xor

Op_arith

Result

Input to SR_IN

AD

DA

DD

SU

B

SU

B


0 0

0 0

0 0

01 0

00 1

00

01

1 1

11

1 1

11 0

1 0

1 0

0 0

0 1

1

1111 1111 ndash 1111 1111 = 1 0000 0000

1010 1010 ndash 1001 1001 = 1 0001 0001

1111 1111 + 1111 1111 = 1 1111 1110

1010 1010 + 1001 1001 = 1 0100 0011

56 GHz



19


19




electronics




Future directions



Summary

20


20


Energy


E1

E2

Input energy E1

Output energy E2



switching errors

E1 gt 100 kBT

F0

Ib

21


21


Energy


E1

E2

Nonadiabatic

transition



F0

Ib

~ IbF0

22


22




23


23




Iout

E

Iout

E

Iout

E

t

Exciting

current

24


24


coscos2

2

)()( 22

qL

S

L

Ejqfp EU

2

2

22

22

22

212100

0

0

0

01

00

1

F

F

F

F

F

IEE

ILIL

ILIM

Jj

q

qL

Sq

SE

E


Normalized exciting

current

Normalized input

current

Normalized loop

inductance

Normalized output

inductance

E

S

q

L

E = 15 E = 27 E = 22

(L q) = (10 30)

25


25


(L q) = (10 30)

(L q) = (08 04)


Adiabatic-mode QFP

26



26



in AQFP change

adiabatically Ph

ase

diffe

ren

ce

s

Excitation flux

27



27


11000 of RSFQ

E

S

q

L

fEnergy dissipation


(L L)



28

Robust AQFP Design

(02 16)



(02 16)





29


29


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf


Damping

resistance



30



30


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf



31



31


Finite Temperatures


(L q) = (02 16) Ic = 50 mA




42 110 plusmn194

12 386 plusmn138

20 232 plusmn88


32


32




electronics




Future directions



Summary

33


33



Functionality

Speed

Energy consumption

Driving ability

Connectability

Robustness

Density

34


34


Excitation

Outputs

x2 = 05

(L q) = (02 16)

Ic = 50 mA

Iin1 = 5 mA

Lin = Lq kq = 03

35



35

Gain


If we assume



Ic dIin ~ 50


Iin ~ 20 mA Ic = 100 mA





36


36

Functionality



-



Buffer NOT



Majority a b c

x



37


37

Speed






119871119886119905119890119899119888119910 =119888119897119900119888119896 119901119890119903119894119900119889

119899119906119898119887119890119903 119900119891 119901ℎ119886119904119890


38


38

Energy Consumption




c is 1000 ps Ic = 50 mA


2 0rf

swcbit IE

F

ccc

swj

c

RI

00 2 F

F

Bit energy


39



39

Driving Ability



Fan-out 14 splitter


(STP2) was used

40

N


40

Connectability



Lmax ~ 1 mm

Iout vs Lwire



41


41

Robustness



42



42





Bias Current 360 mA

JJ number 83736




and inductances




43

Density


13times25 mm2


25times40 mm2

Excitation line

(upper layers)

Transformer

(lower layers)



Si Substrate

SiO 2

Nb JJ

Mo Resistor

AlOx

BAS (M2) ＧＣ

RC RC

JC

BC

COU (M3)

BAS (M2)

COU (M3)

CC CC

COU

CTL (M4) CTL (M4)

SiO 2


I1+I2+I3 +I4 (700 nm)

I5 (500 nm)

CC

CTL (M4)

CC

IN1 (100 nm)

Nb Pd - NW2 (40 nm + 40 nm) IN2 (100 nm)




~ 03M gatecm2

44


44




transformer can be



Schematic of an

AQFP buffer

15 mm x 20 mm


AIST HSTP process

MIT LL process

(SFQ5ee)


20 mm x 40 mm

45


45

Design Methodology



46

(

accbba

cbax

　　

MAJ (

ab

ba

bax

　　

　　

1MAJ azyx


Buffer 13-branch

NOT

1-constant


46


46


47





47


47

AQFP Logic Design


like Lego blocks


amp data flow

Inputs Phase 1

Phase 2

Phase 3

Phase 1

Phase 2

Phase 3

Phase 1

Outputs

Data

flo

w

AQFP design flow

48


48


49






49


Q Xu et al IEEE TAS 27 1301905 (2017)


49



50


50


Design Flow



ahead adder

12-bit instruction

decoder

Correct

operation

confirmed

1090 JJ

7100 JJ






51


51








~ 24 kBTjunction

5 GHz

52




52





5-GHz 4-phse

clock latency

~ 50 ps




Delay-line

clock latency

~ 5 ps

53


53







54


54



DGP HSTP


T Ando et al SUST 30 (2017) 075003

55



55




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66


Reduction of static

power is required


PD = F0Icf


PS = RbIc2

PD ~ PS20

15


15

DC Powered


PS ~ PD ~ IcF0f


PS ~ 0 PD ~ IcF0f

PS ~ 0 PD lt IcF0f

dt

dφ

2π

Ф0V

RB

J1

RS

IB

VB


109 103903 (2011)



ERSFQ (Hypres)

AC Powered

PS ~ 5PD PD ~ IcF0f


1053102 (2012)



26 035010 (2013)



16



17


17


SFQ Logic




Adiabatic QFP Logic


efficiency

1~10 zJoperation



18


18


1 mm

M9

M8

M7

M6M5M4M3M2

M1

Si Substrate

SiO2

Junction

Resistor



Main groundplane

Upper PTLs

Lower PTLs

DC power



clk

Op_and

Inv_x

Inv_y

C_out

Clk_outS0

S1S2

S3S4

S5S6

S7

Inpu

tO

utp

ut

Op_xor

Op_arith

Result

Input to SR_IN

AD

DA

DD

SU

B

SU

B


0 0

0 0

0 0

01 0

00 1

00

01

1 1

11

1 1

11 0

1 0

1 0

0 0

0 1

1

1111 1111 ndash 1111 1111 = 1 0000 0000

1010 1010 ndash 1001 1001 = 1 0001 0001

1111 1111 + 1111 1111 = 1 1111 1110

1010 1010 + 1001 1001 = 1 0100 0011

56 GHz



19


19




electronics




Future directions



Summary

20


20


Energy


E1

E2

Input energy E1

Output energy E2



switching errors

E1 gt 100 kBT

F0

Ib

21


21


Energy


E1

E2

Nonadiabatic

transition



F0

Ib

~ IbF0

22


22




23


23




Iout

E

Iout

E

Iout

E

t

Exciting

current

24


24


coscos2

2

)()( 22

qL

S

L

Ejqfp EU

2

2

22

22

22

212100

0

0

0

01

00

1

F

F

F

F

F

IEE

ILIL

ILIM

Jj

q

qL

Sq

SE

E


Normalized exciting

current

Normalized input

current

Normalized loop

inductance

Normalized output

inductance

E

S

q

L

E = 15 E = 27 E = 22

(L q) = (10 30)

25


25


(L q) = (10 30)

(L q) = (08 04)


Adiabatic-mode QFP

26



26



in AQFP change

adiabatically Ph

ase

diffe

ren

ce

s

Excitation flux

27



27


11000 of RSFQ

E

S

q

L

fEnergy dissipation


(L L)



28

Robust AQFP Design

(02 16)



(02 16)





29


29


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf


Damping

resistance



30



30


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf



31



31


Finite Temperatures


(L q) = (02 16) Ic = 50 mA




42 110 plusmn194

12 386 plusmn138

20 232 plusmn88


32


32




electronics




Future directions



Summary

33


33



Functionality

Speed

Energy consumption

Driving ability

Connectability

Robustness

Density

34


34


Excitation

Outputs

x2 = 05

(L q) = (02 16)

Ic = 50 mA

Iin1 = 5 mA

Lin = Lq kq = 03

35



35

Gain


If we assume



Ic dIin ~ 50


Iin ~ 20 mA Ic = 100 mA





36


36

Functionality



-



Buffer NOT



Majority a b c

x



37


37

Speed






119871119886119905119890119899119888119910 =119888119897119900119888119896 119901119890119903119894119900119889

119899119906119898119887119890119903 119900119891 119901ℎ119886119904119890


38


38

Energy Consumption




c is 1000 ps Ic = 50 mA


2 0rf

swcbit IE

F

ccc

swj

c

RI

00 2 F

F

Bit energy


39



39

Driving Ability



Fan-out 14 splitter


(STP2) was used

40

N


40

Connectability



Lmax ~ 1 mm

Iout vs Lwire



41


41

Robustness



42



42





Bias Current 360 mA

JJ number 83736




and inductances




43

Density


13times25 mm2


25times40 mm2

Excitation line

(upper layers)

Transformer

(lower layers)



Si Substrate

SiO 2

Nb JJ

Mo Resistor

AlOx

BAS (M2) ＧＣ

RC RC

JC

BC

COU (M3)

BAS (M2)

COU (M3)

CC CC

COU

CTL (M4) CTL (M4)

SiO 2


I1+I2+I3 +I4 (700 nm)

I5 (500 nm)

CC

CTL (M4)

CC

IN1 (100 nm)

Nb Pd - NW2 (40 nm + 40 nm) IN2 (100 nm)




~ 03M gatecm2

44


44




transformer can be



Schematic of an

AQFP buffer

15 mm x 20 mm


AIST HSTP process

MIT LL process

(SFQ5ee)


20 mm x 40 mm

45


45

Design Methodology



46

(

accbba

cbax

　　

MAJ (

ab

ba

bax

　　

　　

1MAJ azyx


Buffer 13-branch

NOT

1-constant


46


46


47





47


47

AQFP Logic Design


like Lego blocks


amp data flow

Inputs Phase 1

Phase 2

Phase 3

Phase 1

Phase 2

Phase 3

Phase 1

Outputs

Data

flo

w

AQFP design flow

48


48


49






49


Q Xu et al IEEE TAS 27 1301905 (2017)


49



50


50


Design Flow



ahead adder

12-bit instruction

decoder

Correct

operation

confirmed

1090 JJ

7100 JJ






51


51








~ 24 kBTjunction

5 GHz

52




52





5-GHz 4-phse

clock latency

~ 50 ps




Delay-line

clock latency

~ 5 ps

53


53







54


54



DGP HSTP


T Ando et al SUST 30 (2017) 075003

55



55




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66

DC Powered


PS ~ PD ~ IcF0f


PS ~ 0 PD ~ IcF0f

PS ~ 0 PD lt IcF0f

dt

dφ

2π

Ф0V

RB

J1

RS

IB

VB


109 103903 (2011)



ERSFQ (Hypres)

AC Powered

PS ~ 5PD PD ~ IcF0f


1053102 (2012)



26 035010 (2013)



16



17


17


SFQ Logic




Adiabatic QFP Logic


efficiency

1~10 zJoperation



18


18


1 mm

M9

M8

M7

M6M5M4M3M2

M1

Si Substrate

SiO2

Junction

Resistor



Main groundplane

Upper PTLs

Lower PTLs

DC power



clk

Op_and

Inv_x

Inv_y

C_out

Clk_outS0

S1S2

S3S4

S5S6

S7

Inpu

tO

utp

ut

Op_xor

Op_arith

Result

Input to SR_IN

AD

DA

DD

SU

B

SU

B


0 0

0 0

0 0

01 0

00 1

00

01

1 1

11

1 1

11 0

1 0

1 0

0 0

0 1

1

1111 1111 ndash 1111 1111 = 1 0000 0000

1010 1010 ndash 1001 1001 = 1 0001 0001

1111 1111 + 1111 1111 = 1 1111 1110

1010 1010 + 1001 1001 = 1 0100 0011

56 GHz



19


19




electronics




Future directions



Summary

20


20


Energy


E1

E2

Input energy E1

Output energy E2



switching errors

E1 gt 100 kBT

F0

Ib

21


21


Energy


E1

E2

Nonadiabatic

transition



F0

Ib

~ IbF0

22


22




23


23




Iout

E

Iout

E

Iout

E

t

Exciting

current

24


24


coscos2

2

)()( 22

qL

S

L

Ejqfp EU

2

2

22

22

22

212100

0

0

0

01

00

1

F

F

F

F

F

IEE

ILIL

ILIM

Jj

q

qL

Sq

SE

E


Normalized exciting

current

Normalized input

current

Normalized loop

inductance

Normalized output

inductance

E

S

q

L

E = 15 E = 27 E = 22

(L q) = (10 30)

25


25


(L q) = (10 30)

(L q) = (08 04)


Adiabatic-mode QFP

26



26



in AQFP change

adiabatically Ph

ase

diffe

ren

ce

s

Excitation flux

27



27


11000 of RSFQ

E

S

q

L

fEnergy dissipation


(L L)



28

Robust AQFP Design

(02 16)



(02 16)





29


29


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf


Damping

resistance



30



30


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf



31



31


Finite Temperatures


(L q) = (02 16) Ic = 50 mA




42 110 plusmn194

12 386 plusmn138

20 232 plusmn88


32


32




electronics




Future directions



Summary

33


33



Functionality

Speed

Energy consumption

Driving ability

Connectability

Robustness

Density

34


34


Excitation

Outputs

x2 = 05

(L q) = (02 16)

Ic = 50 mA

Iin1 = 5 mA

Lin = Lq kq = 03

35



35

Gain


If we assume



Ic dIin ~ 50


Iin ~ 20 mA Ic = 100 mA





36


36

Functionality



-



Buffer NOT



Majority a b c

x



37


37

Speed






119871119886119905119890119899119888119910 =119888119897119900119888119896 119901119890119903119894119900119889

119899119906119898119887119890119903 119900119891 119901ℎ119886119904119890


38


38

Energy Consumption




c is 1000 ps Ic = 50 mA


2 0rf

swcbit IE

F

ccc

swj

c

RI

00 2 F

F

Bit energy


39



39

Driving Ability



Fan-out 14 splitter


(STP2) was used

40

N


40

Connectability



Lmax ~ 1 mm

Iout vs Lwire



41


41

Robustness



42



42





Bias Current 360 mA

JJ number 83736




and inductances




43

Density


13times25 mm2


25times40 mm2

Excitation line

(upper layers)

Transformer

(lower layers)



Si Substrate

SiO 2

Nb JJ

Mo Resistor

AlOx

BAS (M2) ＧＣ

RC RC

JC

BC

COU (M3)

BAS (M2)

COU (M3)

CC CC

COU

CTL (M4) CTL (M4)

SiO 2


I1+I2+I3 +I4 (700 nm)

I5 (500 nm)

CC

CTL (M4)

CC

IN1 (100 nm)

Nb Pd - NW2 (40 nm + 40 nm) IN2 (100 nm)




~ 03M gatecm2

44


44




transformer can be



Schematic of an

AQFP buffer

15 mm x 20 mm


AIST HSTP process

MIT LL process

(SFQ5ee)


20 mm x 40 mm

45


45

Design Methodology



46

(

accbba

cbax

　　

MAJ (

ab

ba

bax

　　

　　

1MAJ azyx


Buffer 13-branch

NOT

1-constant


46


46


47





47


47

AQFP Logic Design


like Lego blocks


amp data flow

Inputs Phase 1

Phase 2

Phase 3

Phase 1

Phase 2

Phase 3

Phase 1

Outputs

Data

flo

w

AQFP design flow

48


48


49






49


Q Xu et al IEEE TAS 27 1301905 (2017)


49



50


50


Design Flow



ahead adder

12-bit instruction

decoder

Correct

operation

confirmed

1090 JJ

7100 JJ






51


51








~ 24 kBTjunction

5 GHz

52




52





5-GHz 4-phse

clock latency

~ 50 ps




Delay-line

clock latency

~ 5 ps

53


53







54


54



DGP HSTP


T Ando et al SUST 30 (2017) 075003

55



55




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66



17


17


SFQ Logic




Adiabatic QFP Logic


efficiency

1~10 zJoperation



18


18


1 mm

M9

M8

M7

M6M5M4M3M2

M1

Si Substrate

SiO2

Junction

Resistor



Main groundplane

Upper PTLs

Lower PTLs

DC power



clk

Op_and

Inv_x

Inv_y

C_out

Clk_outS0

S1S2

S3S4

S5S6

S7

Inpu

tO

utp

ut

Op_xor

Op_arith

Result

Input to SR_IN

AD

DA

DD

SU

B

SU

B


0 0

0 0

0 0

01 0

00 1

00

01

1 1

11

1 1

11 0

1 0

1 0

0 0

0 1

1

1111 1111 ndash 1111 1111 = 1 0000 0000

1010 1010 ndash 1001 1001 = 1 0001 0001

1111 1111 + 1111 1111 = 1 1111 1110

1010 1010 + 1001 1001 = 1 0100 0011

56 GHz



19


19




electronics




Future directions



Summary

20


20


Energy


E1

E2

Input energy E1

Output energy E2



switching errors

E1 gt 100 kBT

F0

Ib

21


21


Energy


E1

E2

Nonadiabatic

transition



F0

Ib

~ IbF0

22


22




23


23




Iout

E

Iout

E

Iout

E

t

Exciting

current

24


24


coscos2

2

)()( 22

qL

S

L

Ejqfp EU

2

2

22

22

22

212100

0

0

0

01

00

1

F

F

F

F

F

IEE

ILIL

ILIM

Jj

q

qL

Sq

SE

E


Normalized exciting

current

Normalized input

current

Normalized loop

inductance

Normalized output

inductance

E

S

q

L

E = 15 E = 27 E = 22

(L q) = (10 30)

25


25


(L q) = (10 30)

(L q) = (08 04)


Adiabatic-mode QFP

26



26



in AQFP change

adiabatically Ph

ase

diffe

ren

ce

s

Excitation flux

27



27


11000 of RSFQ

E

S

q

L

fEnergy dissipation


(L L)



28

Robust AQFP Design

(02 16)



(02 16)





29


29


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf


Damping

resistance



30



30


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf



31



31


Finite Temperatures


(L q) = (02 16) Ic = 50 mA




42 110 plusmn194

12 386 plusmn138

20 232 plusmn88


32


32




electronics




Future directions



Summary

33


33



Functionality

Speed

Energy consumption

Driving ability

Connectability

Robustness

Density

34


34


Excitation

Outputs

x2 = 05

(L q) = (02 16)

Ic = 50 mA

Iin1 = 5 mA

Lin = Lq kq = 03

35



35

Gain


If we assume



Ic dIin ~ 50


Iin ~ 20 mA Ic = 100 mA





36


36

Functionality



-



Buffer NOT



Majority a b c

x



37


37

Speed






119871119886119905119890119899119888119910 =119888119897119900119888119896 119901119890119903119894119900119889

119899119906119898119887119890119903 119900119891 119901ℎ119886119904119890


38


38

Energy Consumption




c is 1000 ps Ic = 50 mA


2 0rf

swcbit IE

F

ccc

swj

c

RI

00 2 F

F

Bit energy


39



39

Driving Ability



Fan-out 14 splitter


(STP2) was used

40

N


40

Connectability



Lmax ~ 1 mm

Iout vs Lwire



41


41

Robustness



42



42





Bias Current 360 mA

JJ number 83736




and inductances




43

Density


13times25 mm2


25times40 mm2

Excitation line

(upper layers)

Transformer

(lower layers)



Si Substrate

SiO 2

Nb JJ

Mo Resistor

AlOx

BAS (M2) ＧＣ

RC RC

JC

BC

COU (M3)

BAS (M2)

COU (M3)

CC CC

COU

CTL (M4) CTL (M4)

SiO 2


I1+I2+I3 +I4 (700 nm)

I5 (500 nm)

CC

CTL (M4)

CC

IN1 (100 nm)

Nb Pd - NW2 (40 nm + 40 nm) IN2 (100 nm)




~ 03M gatecm2

44


44




transformer can be



Schematic of an

AQFP buffer

15 mm x 20 mm


AIST HSTP process

MIT LL process

(SFQ5ee)


20 mm x 40 mm

45


45

Design Methodology



46

(

accbba

cbax

　　

MAJ (

ab

ba

bax

　　

　　

1MAJ azyx


Buffer 13-branch

NOT

1-constant


46


46


47





47


47

AQFP Logic Design


like Lego blocks


amp data flow

Inputs Phase 1

Phase 2

Phase 3

Phase 1

Phase 2

Phase 3

Phase 1

Outputs

Data

flo

w

AQFP design flow

48


48


49






49


Q Xu et al IEEE TAS 27 1301905 (2017)


49



50


50


Design Flow



ahead adder

12-bit instruction

decoder

Correct

operation

confirmed

1090 JJ

7100 JJ






51


51








~ 24 kBTjunction

5 GHz

52




52





5-GHz 4-phse

clock latency

~ 50 ps




Delay-line

clock latency

~ 5 ps

53


53







54


54



DGP HSTP


T Ando et al SUST 30 (2017) 075003

55



55




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66


SFQ Logic




Adiabatic QFP Logic


efficiency

1~10 zJoperation



18


18


1 mm

M9

M8

M7

M6M5M4M3M2

M1

Si Substrate

SiO2

Junction

Resistor



Main groundplane

Upper PTLs

Lower PTLs

DC power



clk

Op_and

Inv_x

Inv_y

C_out

Clk_outS0

S1S2

S3S4

S5S6

S7

Inpu

tO

utp

ut

Op_xor

Op_arith

Result

Input to SR_IN

AD

DA

DD

SU

B

SU

B


0 0

0 0

0 0

01 0

00 1

00

01

1 1

11

1 1

11 0

1 0

1 0

0 0

0 1

1

1111 1111 ndash 1111 1111 = 1 0000 0000

1010 1010 ndash 1001 1001 = 1 0001 0001

1111 1111 + 1111 1111 = 1 1111 1110

1010 1010 + 1001 1001 = 1 0100 0011

56 GHz



19


19




electronics




Future directions



Summary

20


20


Energy


E1

E2

Input energy E1

Output energy E2



switching errors

E1 gt 100 kBT

F0

Ib

21


21


Energy


E1

E2

Nonadiabatic

transition



F0

Ib

~ IbF0

22


22




23


23




Iout

E

Iout

E

Iout

E

t

Exciting

current

24


24


coscos2

2

)()( 22

qL

S

L

Ejqfp EU

2

2

22

22

22

212100

0

0

0

01

00

1

F

F

F

F

F

IEE

ILIL

ILIM

Jj

q

qL

Sq

SE

E


Normalized exciting

current

Normalized input

current

Normalized loop

inductance

Normalized output

inductance

E

S

q

L

E = 15 E = 27 E = 22

(L q) = (10 30)

25


25


(L q) = (10 30)

(L q) = (08 04)


Adiabatic-mode QFP

26



26



in AQFP change

adiabatically Ph

ase

diffe

ren

ce

s

Excitation flux

27



27


11000 of RSFQ

E

S

q

L

fEnergy dissipation


(L L)



28

Robust AQFP Design

(02 16)



(02 16)





29


29


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf


Damping

resistance



30



30


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf



31



31


Finite Temperatures


(L q) = (02 16) Ic = 50 mA




42 110 plusmn194

12 386 plusmn138

20 232 plusmn88


32


32




electronics




Future directions



Summary

33


33



Functionality

Speed

Energy consumption

Driving ability

Connectability

Robustness

Density

34


34


Excitation

Outputs

x2 = 05

(L q) = (02 16)

Ic = 50 mA

Iin1 = 5 mA

Lin = Lq kq = 03

35



35

Gain


If we assume



Ic dIin ~ 50


Iin ~ 20 mA Ic = 100 mA





36


36

Functionality



-



Buffer NOT



Majority a b c

x



37


37

Speed






119871119886119905119890119899119888119910 =119888119897119900119888119896 119901119890119903119894119900119889

119899119906119898119887119890119903 119900119891 119901ℎ119886119904119890


38


38

Energy Consumption




c is 1000 ps Ic = 50 mA


2 0rf

swcbit IE

F

ccc

swj

c

RI

00 2 F

F

Bit energy


39



39

Driving Ability



Fan-out 14 splitter


(STP2) was used

40

N


40

Connectability



Lmax ~ 1 mm

Iout vs Lwire



41


41

Robustness



42



42





Bias Current 360 mA

JJ number 83736




and inductances




43

Density


13times25 mm2


25times40 mm2

Excitation line

(upper layers)

Transformer

(lower layers)



Si Substrate

SiO 2

Nb JJ

Mo Resistor

AlOx

BAS (M2) ＧＣ

RC RC

JC

BC

COU (M3)

BAS (M2)

COU (M3)

CC CC

COU

CTL (M4) CTL (M4)

SiO 2


I1+I2+I3 +I4 (700 nm)

I5 (500 nm)

CC

CTL (M4)

CC

IN1 (100 nm)

Nb Pd - NW2 (40 nm + 40 nm) IN2 (100 nm)




~ 03M gatecm2

44


44




transformer can be



Schematic of an

AQFP buffer

15 mm x 20 mm


AIST HSTP process

MIT LL process

(SFQ5ee)


20 mm x 40 mm

45


45

Design Methodology



46

(

accbba

cbax

　　

MAJ (

ab

ba

bax

　　

　　

1MAJ azyx


Buffer 13-branch

NOT

1-constant


46


46


47





47


47

AQFP Logic Design


like Lego blocks


amp data flow

Inputs Phase 1

Phase 2

Phase 3

Phase 1

Phase 2

Phase 3

Phase 1

Outputs

Data

flo

w

AQFP design flow

48


48


49






49


Q Xu et al IEEE TAS 27 1301905 (2017)


49



50


50


Design Flow



ahead adder

12-bit instruction

decoder

Correct

operation

confirmed

1090 JJ

7100 JJ






51


51








~ 24 kBTjunction

5 GHz

52




52





5-GHz 4-phse

clock latency

~ 50 ps




Delay-line

clock latency

~ 5 ps

53


53







54


54



DGP HSTP


T Ando et al SUST 30 (2017) 075003

55



55




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66


1 mm

M9

M8

M7

M6M5M4M3M2

M1

Si Substrate

SiO2

Junction

Resistor



Main groundplane

Upper PTLs

Lower PTLs

DC power



clk

Op_and

Inv_x

Inv_y

C_out

Clk_outS0

S1S2

S3S4

S5S6

S7

Inpu

tO

utp

ut

Op_xor

Op_arith

Result

Input to SR_IN

AD

DA

DD

SU

B

SU

B


0 0

0 0

0 0

01 0

00 1

00

01

1 1

11

1 1

11 0

1 0

1 0

0 0

0 1

1

1111 1111 ndash 1111 1111 = 1 0000 0000

1010 1010 ndash 1001 1001 = 1 0001 0001

1111 1111 + 1111 1111 = 1 1111 1110

1010 1010 + 1001 1001 = 1 0100 0011

56 GHz



19


19




electronics




Future directions



Summary

20


20


Energy


E1

E2

Input energy E1

Output energy E2



switching errors

E1 gt 100 kBT

F0

Ib

21


21


Energy


E1

E2

Nonadiabatic

transition



F0

Ib

~ IbF0

22


22




23


23




Iout

E

Iout

E

Iout

E

t

Exciting

current

24


24


coscos2

2

)()( 22

qL

S

L

Ejqfp EU

2

2

22

22

22

212100

0

0

0

01

00

1

F

F

F

F

F

IEE

ILIL

ILIM

Jj

q

qL

Sq

SE

E


Normalized exciting

current

Normalized input

current

Normalized loop

inductance

Normalized output

inductance

E

S

q

L

E = 15 E = 27 E = 22

(L q) = (10 30)

25


25


(L q) = (10 30)

(L q) = (08 04)


Adiabatic-mode QFP

26



26



in AQFP change

adiabatically Ph

ase

diffe

ren

ce

s

Excitation flux

27



27


11000 of RSFQ

E

S

q

L

fEnergy dissipation


(L L)



28

Robust AQFP Design

(02 16)



(02 16)





29


29


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf


Damping

resistance



30



30


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf



31



31


Finite Temperatures


(L q) = (02 16) Ic = 50 mA




42 110 plusmn194

12 386 plusmn138

20 232 plusmn88


32


32




electronics




Future directions



Summary

33


33



Functionality

Speed

Energy consumption

Driving ability

Connectability

Robustness

Density

34


34


Excitation

Outputs

x2 = 05

(L q) = (02 16)

Ic = 50 mA

Iin1 = 5 mA

Lin = Lq kq = 03

35



35

Gain


If we assume



Ic dIin ~ 50


Iin ~ 20 mA Ic = 100 mA





36


36

Functionality



-



Buffer NOT



Majority a b c

x



37


37

Speed






119871119886119905119890119899119888119910 =119888119897119900119888119896 119901119890119903119894119900119889

119899119906119898119887119890119903 119900119891 119901ℎ119886119904119890


38


38

Energy Consumption




c is 1000 ps Ic = 50 mA


2 0rf

swcbit IE

F

ccc

swj

c

RI

00 2 F

F

Bit energy


39



39

Driving Ability



Fan-out 14 splitter


(STP2) was used

40

N


40

Connectability



Lmax ~ 1 mm

Iout vs Lwire



41


41

Robustness



42



42





Bias Current 360 mA

JJ number 83736




and inductances




43

Density


13times25 mm2


25times40 mm2

Excitation line

(upper layers)

Transformer

(lower layers)



Si Substrate

SiO 2

Nb JJ

Mo Resistor

AlOx

BAS (M2) ＧＣ

RC RC

JC

BC

COU (M3)

BAS (M2)

COU (M3)

CC CC

COU

CTL (M4) CTL (M4)

SiO 2


I1+I2+I3 +I4 (700 nm)

I5 (500 nm)

CC

CTL (M4)

CC

IN1 (100 nm)

Nb Pd - NW2 (40 nm + 40 nm) IN2 (100 nm)




~ 03M gatecm2

44


44




transformer can be



Schematic of an

AQFP buffer

15 mm x 20 mm


AIST HSTP process

MIT LL process

(SFQ5ee)


20 mm x 40 mm

45


45

Design Methodology



46

(

accbba

cbax

　　

MAJ (

ab

ba

bax

　　

　　

1MAJ azyx


Buffer 13-branch

NOT

1-constant


46


46


47





47


47

AQFP Logic Design


like Lego blocks


amp data flow

Inputs Phase 1

Phase 2

Phase 3

Phase 1

Phase 2

Phase 3

Phase 1

Outputs

Data

flo

w

AQFP design flow

48


48


49






49


Q Xu et al IEEE TAS 27 1301905 (2017)


49



50


50


Design Flow



ahead adder

12-bit instruction

decoder

Correct

operation

confirmed

1090 JJ

7100 JJ






51


51








~ 24 kBTjunction

5 GHz

52




52





5-GHz 4-phse

clock latency

~ 50 ps




Delay-line

clock latency

~ 5 ps

53


53







54


54



DGP HSTP


T Ando et al SUST 30 (2017) 075003

55



55




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66




electronics




Future directions



Summary

20


20


Energy


E1

E2

Input energy E1

Output energy E2



switching errors

E1 gt 100 kBT

F0

Ib

21


21


Energy


E1

E2

Nonadiabatic

transition



F0

Ib

~ IbF0

22


22




23


23




Iout

E

Iout

E

Iout

E

t

Exciting

current

24


24


coscos2

2

)()( 22

qL

S

L

Ejqfp EU

2

2

22

22

22

212100

0

0

0

01

00

1

F

F

F

F

F

IEE

ILIL

ILIM

Jj

q

qL

Sq

SE

E


Normalized exciting

current

Normalized input

current

Normalized loop

inductance

Normalized output

inductance

E

S

q

L

E = 15 E = 27 E = 22

(L q) = (10 30)

25


25


(L q) = (10 30)

(L q) = (08 04)


Adiabatic-mode QFP

26



26



in AQFP change

adiabatically Ph

ase

diffe

ren

ce

s

Excitation flux

27



27


11000 of RSFQ

E

S

q

L

fEnergy dissipation


(L L)



28

Robust AQFP Design

(02 16)



(02 16)





29


29


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf


Damping

resistance



30



30


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf



31



31


Finite Temperatures


(L q) = (02 16) Ic = 50 mA




42 110 plusmn194

12 386 plusmn138

20 232 plusmn88


32


32




electronics




Future directions



Summary

33


33



Functionality

Speed

Energy consumption

Driving ability

Connectability

Robustness

Density

34


34


Excitation

Outputs

x2 = 05

(L q) = (02 16)

Ic = 50 mA

Iin1 = 5 mA

Lin = Lq kq = 03

35



35

Gain


If we assume



Ic dIin ~ 50


Iin ~ 20 mA Ic = 100 mA





36


36

Functionality



-



Buffer NOT



Majority a b c

x



37


37

Speed






119871119886119905119890119899119888119910 =119888119897119900119888119896 119901119890119903119894119900119889

119899119906119898119887119890119903 119900119891 119901ℎ119886119904119890


38


38

Energy Consumption




c is 1000 ps Ic = 50 mA


2 0rf

swcbit IE

F

ccc

swj

c

RI

00 2 F

F

Bit energy


39



39

Driving Ability



Fan-out 14 splitter


(STP2) was used

40

N


40

Connectability



Lmax ~ 1 mm

Iout vs Lwire



41


41

Robustness



42



42





Bias Current 360 mA

JJ number 83736




and inductances




43

Density


13times25 mm2


25times40 mm2

Excitation line

(upper layers)

Transformer

(lower layers)



Si Substrate

SiO 2

Nb JJ

Mo Resistor

AlOx

BAS (M2) ＧＣ

RC RC

JC

BC

COU (M3)

BAS (M2)

COU (M3)

CC CC

COU

CTL (M4) CTL (M4)

SiO 2


I1+I2+I3 +I4 (700 nm)

I5 (500 nm)

CC

CTL (M4)

CC

IN1 (100 nm)

Nb Pd - NW2 (40 nm + 40 nm) IN2 (100 nm)




~ 03M gatecm2

44


44




transformer can be



Schematic of an

AQFP buffer

15 mm x 20 mm


AIST HSTP process

MIT LL process

(SFQ5ee)


20 mm x 40 mm

45


45

Design Methodology



46

(

accbba

cbax

　　

MAJ (

ab

ba

bax

　　

　　

1MAJ azyx


Buffer 13-branch

NOT

1-constant


46


46


47





47


47

AQFP Logic Design


like Lego blocks


amp data flow

Inputs Phase 1

Phase 2

Phase 3

Phase 1

Phase 2

Phase 3

Phase 1

Outputs

Data

flo

w

AQFP design flow

48


48


49






49


Q Xu et al IEEE TAS 27 1301905 (2017)


49



50


50


Design Flow



ahead adder

12-bit instruction

decoder

Correct

operation

confirmed

1090 JJ

7100 JJ






51


51








~ 24 kBTjunction

5 GHz

52




52





5-GHz 4-phse

clock latency

~ 50 ps




Delay-line

clock latency

~ 5 ps

53


53







54


54



DGP HSTP


T Ando et al SUST 30 (2017) 075003

55



55




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66


Energy


E1

E2

Input energy E1

Output energy E2



switching errors

E1 gt 100 kBT

F0

Ib

21


21


Energy


E1

E2

Nonadiabatic

transition



F0

Ib

~ IbF0

22


22




23


23




Iout

E

Iout

E

Iout

E

t

Exciting

current

24


24


coscos2

2

)()( 22

qL

S

L

Ejqfp EU

2

2

22

22

22

212100

0

0

0

01

00

1

F

F

F

F

F

IEE

ILIL

ILIM

Jj

q

qL

Sq

SE

E


Normalized exciting

current

Normalized input

current

Normalized loop

inductance

Normalized output

inductance

E

S

q

L

E = 15 E = 27 E = 22

(L q) = (10 30)

25


25


(L q) = (10 30)

(L q) = (08 04)


Adiabatic-mode QFP

26



26



in AQFP change

adiabatically Ph

ase

diffe

ren

ce

s

Excitation flux

27



27


11000 of RSFQ

E

S

q

L

fEnergy dissipation


(L L)



28

Robust AQFP Design

(02 16)



(02 16)





29


29


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf


Damping

resistance



30



30


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf



31



31


Finite Temperatures


(L q) = (02 16) Ic = 50 mA




42 110 plusmn194

12 386 plusmn138

20 232 plusmn88


32


32




electronics




Future directions



Summary

33


33



Functionality

Speed

Energy consumption

Driving ability

Connectability

Robustness

Density

34


34


Excitation

Outputs

x2 = 05

(L q) = (02 16)

Ic = 50 mA

Iin1 = 5 mA

Lin = Lq kq = 03

35



35

Gain


If we assume



Ic dIin ~ 50


Iin ~ 20 mA Ic = 100 mA





36


36

Functionality



-



Buffer NOT



Majority a b c

x



37


37

Speed






119871119886119905119890119899119888119910 =119888119897119900119888119896 119901119890119903119894119900119889

119899119906119898119887119890119903 119900119891 119901ℎ119886119904119890


38


38

Energy Consumption




c is 1000 ps Ic = 50 mA


2 0rf

swcbit IE

F

ccc

swj

c

RI

00 2 F

F

Bit energy


39



39

Driving Ability



Fan-out 14 splitter


(STP2) was used

40

N


40

Connectability



Lmax ~ 1 mm

Iout vs Lwire



41


41

Robustness



42



42





Bias Current 360 mA

JJ number 83736




and inductances




43

Density


13times25 mm2


25times40 mm2

Excitation line

(upper layers)

Transformer

(lower layers)



Si Substrate

SiO 2

Nb JJ

Mo Resistor

AlOx

BAS (M2) ＧＣ

RC RC

JC

BC

COU (M3)

BAS (M2)

COU (M3)

CC CC

COU

CTL (M4) CTL (M4)

SiO 2


I1+I2+I3 +I4 (700 nm)

I5 (500 nm)

CC

CTL (M4)

CC

IN1 (100 nm)

Nb Pd - NW2 (40 nm + 40 nm) IN2 (100 nm)




~ 03M gatecm2

44


44




transformer can be



Schematic of an

AQFP buffer

15 mm x 20 mm


AIST HSTP process

MIT LL process

(SFQ5ee)


20 mm x 40 mm

45


45

Design Methodology



46

(

accbba

cbax

　　

MAJ (

ab

ba

bax

　　

　　

1MAJ azyx


Buffer 13-branch

NOT

1-constant


46


46


47





47


47

AQFP Logic Design


like Lego blocks


amp data flow

Inputs Phase 1

Phase 2

Phase 3

Phase 1

Phase 2

Phase 3

Phase 1

Outputs

Data

flo

w

AQFP design flow

48


48


49






49


Q Xu et al IEEE TAS 27 1301905 (2017)


49



50


50


Design Flow



ahead adder

12-bit instruction

decoder

Correct

operation

confirmed

1090 JJ

7100 JJ






51


51








~ 24 kBTjunction

5 GHz

52




52





5-GHz 4-phse

clock latency

~ 50 ps




Delay-line

clock latency

~ 5 ps

53


53







54


54



DGP HSTP


T Ando et al SUST 30 (2017) 075003

55



55




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66


Energy


E1

E2

Nonadiabatic

transition



F0

Ib

~ IbF0

22


22




23


23




Iout

E

Iout

E

Iout

E

t

Exciting

current

24


24


coscos2

2

)()( 22

qL

S

L

Ejqfp EU

2

2

22

22

22

212100

0

0

0

01

00

1

F

F

F

F

F

IEE

ILIL

ILIM

Jj

q

qL

Sq

SE

E


Normalized exciting

current

Normalized input

current

Normalized loop

inductance

Normalized output

inductance

E

S

q

L

E = 15 E = 27 E = 22

(L q) = (10 30)

25


25


(L q) = (10 30)

(L q) = (08 04)


Adiabatic-mode QFP

26



26



in AQFP change

adiabatically Ph

ase

diffe

ren

ce

s

Excitation flux

27



27


11000 of RSFQ

E

S

q

L

fEnergy dissipation


(L L)



28

Robust AQFP Design

(02 16)



(02 16)





29


29


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf


Damping

resistance



30



30


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf



31



31


Finite Temperatures


(L q) = (02 16) Ic = 50 mA




42 110 plusmn194

12 386 plusmn138

20 232 plusmn88


32


32




electronics




Future directions



Summary

33


33



Functionality

Speed

Energy consumption

Driving ability

Connectability

Robustness

Density

34


34


Excitation

Outputs

x2 = 05

(L q) = (02 16)

Ic = 50 mA

Iin1 = 5 mA

Lin = Lq kq = 03

35



35

Gain


If we assume



Ic dIin ~ 50


Iin ~ 20 mA Ic = 100 mA





36


36

Functionality



-



Buffer NOT



Majority a b c

x



37


37

Speed






119871119886119905119890119899119888119910 =119888119897119900119888119896 119901119890119903119894119900119889

119899119906119898119887119890119903 119900119891 119901ℎ119886119904119890


38


38

Energy Consumption




c is 1000 ps Ic = 50 mA


2 0rf

swcbit IE

F

ccc

swj

c

RI

00 2 F

F

Bit energy


39



39

Driving Ability



Fan-out 14 splitter


(STP2) was used

40

N


40

Connectability



Lmax ~ 1 mm

Iout vs Lwire



41


41

Robustness



42



42





Bias Current 360 mA

JJ number 83736




and inductances




43

Density


13times25 mm2


25times40 mm2

Excitation line

(upper layers)

Transformer

(lower layers)



Si Substrate

SiO 2

Nb JJ

Mo Resistor

AlOx

BAS (M2) ＧＣ

RC RC

JC

BC

COU (M3)

BAS (M2)

COU (M3)

CC CC

COU

CTL (M4) CTL (M4)

SiO 2


I1+I2+I3 +I4 (700 nm)

I5 (500 nm)

CC

CTL (M4)

CC

IN1 (100 nm)

Nb Pd - NW2 (40 nm + 40 nm) IN2 (100 nm)




~ 03M gatecm2

44


44




transformer can be



Schematic of an

AQFP buffer

15 mm x 20 mm


AIST HSTP process

MIT LL process

(SFQ5ee)


20 mm x 40 mm

45


45

Design Methodology



46

(

accbba

cbax

　　

MAJ (

ab

ba

bax

　　

　　

1MAJ azyx


Buffer 13-branch

NOT

1-constant


46


46


47





47


47

AQFP Logic Design


like Lego blocks


amp data flow

Inputs Phase 1

Phase 2

Phase 3

Phase 1

Phase 2

Phase 3

Phase 1

Outputs

Data

flo

w

AQFP design flow

48


48


49






49


Q Xu et al IEEE TAS 27 1301905 (2017)


49



50


50


Design Flow



ahead adder

12-bit instruction

decoder

Correct

operation

confirmed

1090 JJ

7100 JJ






51


51








~ 24 kBTjunction

5 GHz

52




52





5-GHz 4-phse

clock latency

~ 50 ps




Delay-line

clock latency

~ 5 ps

53


53







54


54



DGP HSTP


T Ando et al SUST 30 (2017) 075003

55



55




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66




23


23




Iout

E

Iout

E

Iout

E

t

Exciting

current

24


24


coscos2

2

)()( 22

qL

S

L

Ejqfp EU

2

2

22

22

22

212100

0

0

0

01

00

1

F

F

F

F

F

IEE

ILIL

ILIM

Jj

q

qL

Sq

SE

E


Normalized exciting

current

Normalized input

current

Normalized loop

inductance

Normalized output

inductance

E

S

q

L

E = 15 E = 27 E = 22

(L q) = (10 30)

25


25


(L q) = (10 30)

(L q) = (08 04)


Adiabatic-mode QFP

26



26



in AQFP change

adiabatically Ph

ase

diffe

ren

ce

s

Excitation flux

27



27


11000 of RSFQ

E

S

q

L

fEnergy dissipation


(L L)



28

Robust AQFP Design

(02 16)



(02 16)





29


29


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf


Damping

resistance



30



30


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf



31



31


Finite Temperatures


(L q) = (02 16) Ic = 50 mA




42 110 plusmn194

12 386 plusmn138

20 232 plusmn88


32


32




electronics




Future directions



Summary

33


33



Functionality

Speed

Energy consumption

Driving ability

Connectability

Robustness

Density

34


34


Excitation

Outputs

x2 = 05

(L q) = (02 16)

Ic = 50 mA

Iin1 = 5 mA

Lin = Lq kq = 03

35



35

Gain


If we assume



Ic dIin ~ 50


Iin ~ 20 mA Ic = 100 mA





36


36

Functionality



-



Buffer NOT



Majority a b c

x



37


37

Speed






119871119886119905119890119899119888119910 =119888119897119900119888119896 119901119890119903119894119900119889

119899119906119898119887119890119903 119900119891 119901ℎ119886119904119890


38


38

Energy Consumption




c is 1000 ps Ic = 50 mA


2 0rf

swcbit IE

F

ccc

swj

c

RI

00 2 F

F

Bit energy


39



39

Driving Ability



Fan-out 14 splitter


(STP2) was used

40

N


40

Connectability



Lmax ~ 1 mm

Iout vs Lwire



41


41

Robustness



42



42





Bias Current 360 mA

JJ number 83736




and inductances




43

Density


13times25 mm2


25times40 mm2

Excitation line

(upper layers)

Transformer

(lower layers)



Si Substrate

SiO 2

Nb JJ

Mo Resistor

AlOx

BAS (M2) ＧＣ

RC RC

JC

BC

COU (M3)

BAS (M2)

COU (M3)

CC CC

COU

CTL (M4) CTL (M4)

SiO 2


I1+I2+I3 +I4 (700 nm)

I5 (500 nm)

CC

CTL (M4)

CC

IN1 (100 nm)

Nb Pd - NW2 (40 nm + 40 nm) IN2 (100 nm)




~ 03M gatecm2

44


44




transformer can be



Schematic of an

AQFP buffer

15 mm x 20 mm


AIST HSTP process

MIT LL process

(SFQ5ee)


20 mm x 40 mm

45


45

Design Methodology



46

(

accbba

cbax

　　

MAJ (

ab

ba

bax

　　

　　

1MAJ azyx


Buffer 13-branch

NOT

1-constant


46


46


47





47


47

AQFP Logic Design


like Lego blocks


amp data flow

Inputs Phase 1

Phase 2

Phase 3

Phase 1

Phase 2

Phase 3

Phase 1

Outputs

Data

flo

w

AQFP design flow

48


48


49






49


Q Xu et al IEEE TAS 27 1301905 (2017)


49



50


50


Design Flow



ahead adder

12-bit instruction

decoder

Correct

operation

confirmed

1090 JJ

7100 JJ






51


51








~ 24 kBTjunction

5 GHz

52




52





5-GHz 4-phse

clock latency

~ 50 ps




Delay-line

clock latency

~ 5 ps

53


53







54


54



DGP HSTP


T Ando et al SUST 30 (2017) 075003

55



55




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66




Iout

E

Iout

E

Iout

E

t

Exciting

current

24


24


coscos2

2

)()( 22

qL

S

L

Ejqfp EU

2

2

22

22

22

212100

0

0

0

01

00

1

F

F

F

F

F

IEE

ILIL

ILIM

Jj

q

qL

Sq

SE

E


Normalized exciting

current

Normalized input

current

Normalized loop

inductance

Normalized output

inductance

E

S

q

L

E = 15 E = 27 E = 22

(L q) = (10 30)

25


25


(L q) = (10 30)

(L q) = (08 04)


Adiabatic-mode QFP

26



26



in AQFP change

adiabatically Ph

ase

diffe

ren

ce

s

Excitation flux

27



27


11000 of RSFQ

E

S

q

L

fEnergy dissipation


(L L)



28

Robust AQFP Design

(02 16)



(02 16)





29


29


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf


Damping

resistance



30



30


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf



31



31


Finite Temperatures


(L q) = (02 16) Ic = 50 mA




42 110 plusmn194

12 386 plusmn138

20 232 plusmn88


32


32




electronics




Future directions



Summary

33


33



Functionality

Speed

Energy consumption

Driving ability

Connectability

Robustness

Density

34


34


Excitation

Outputs

x2 = 05

(L q) = (02 16)

Ic = 50 mA

Iin1 = 5 mA

Lin = Lq kq = 03

35



35

Gain


If we assume



Ic dIin ~ 50


Iin ~ 20 mA Ic = 100 mA





36


36

Functionality



-



Buffer NOT



Majority a b c

x



37


37

Speed






119871119886119905119890119899119888119910 =119888119897119900119888119896 119901119890119903119894119900119889

119899119906119898119887119890119903 119900119891 119901ℎ119886119904119890


38


38

Energy Consumption




c is 1000 ps Ic = 50 mA


2 0rf

swcbit IE

F

ccc

swj

c

RI

00 2 F

F

Bit energy


39



39

Driving Ability



Fan-out 14 splitter


(STP2) was used

40

N


40

Connectability



Lmax ~ 1 mm

Iout vs Lwire



41


41

Robustness



42



42





Bias Current 360 mA

JJ number 83736




and inductances




43

Density


13times25 mm2


25times40 mm2

Excitation line

(upper layers)

Transformer

(lower layers)



Si Substrate

SiO 2

Nb JJ

Mo Resistor

AlOx

BAS (M2) ＧＣ

RC RC

JC

BC

COU (M3)

BAS (M2)

COU (M3)

CC CC

COU

CTL (M4) CTL (M4)

SiO 2


I1+I2+I3 +I4 (700 nm)

I5 (500 nm)

CC

CTL (M4)

CC

IN1 (100 nm)

Nb Pd - NW2 (40 nm + 40 nm) IN2 (100 nm)




~ 03M gatecm2

44


44




transformer can be



Schematic of an

AQFP buffer

15 mm x 20 mm


AIST HSTP process

MIT LL process

(SFQ5ee)


20 mm x 40 mm

45


45

Design Methodology



46

(

accbba

cbax

　　

MAJ (

ab

ba

bax

　　

　　

1MAJ azyx


Buffer 13-branch

NOT

1-constant


46


46


47





47


47

AQFP Logic Design


like Lego blocks


amp data flow

Inputs Phase 1

Phase 2

Phase 3

Phase 1

Phase 2

Phase 3

Phase 1

Outputs

Data

flo

w

AQFP design flow

48


48


49






49


Q Xu et al IEEE TAS 27 1301905 (2017)


49



50


50


Design Flow



ahead adder

12-bit instruction

decoder

Correct

operation

confirmed

1090 JJ

7100 JJ






51


51








~ 24 kBTjunction

5 GHz

52




52





5-GHz 4-phse

clock latency

~ 50 ps




Delay-line

clock latency

~ 5 ps

53


53







54


54



DGP HSTP


T Ando et al SUST 30 (2017) 075003

55



55




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66


coscos2

2

)()( 22

qL

S

L

Ejqfp EU

2

2

22

22

22

212100

0

0

0

01

00

1

F

F

F

F

F

IEE

ILIL

ILIM

Jj

q

qL

Sq

SE

E


Normalized exciting

current

Normalized input

current

Normalized loop

inductance

Normalized output

inductance

E

S

q

L

E = 15 E = 27 E = 22

(L q) = (10 30)

25


25


(L q) = (10 30)

(L q) = (08 04)


Adiabatic-mode QFP

26



26



in AQFP change

adiabatically Ph

ase

diffe

ren

ce

s

Excitation flux

27



27


11000 of RSFQ

E

S

q

L

fEnergy dissipation


(L L)



28

Robust AQFP Design

(02 16)



(02 16)





29


29


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf


Damping

resistance



30



30


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf



31



31


Finite Temperatures


(L q) = (02 16) Ic = 50 mA




42 110 plusmn194

12 386 plusmn138

20 232 plusmn88


32


32




electronics




Future directions



Summary

33


33



Functionality

Speed

Energy consumption

Driving ability

Connectability

Robustness

Density

34


34


Excitation

Outputs

x2 = 05

(L q) = (02 16)

Ic = 50 mA

Iin1 = 5 mA

Lin = Lq kq = 03

35



35

Gain


If we assume



Ic dIin ~ 50


Iin ~ 20 mA Ic = 100 mA





36


36

Functionality



-



Buffer NOT



Majority a b c

x



37


37

Speed






119871119886119905119890119899119888119910 =119888119897119900119888119896 119901119890119903119894119900119889

119899119906119898119887119890119903 119900119891 119901ℎ119886119904119890


38


38

Energy Consumption




c is 1000 ps Ic = 50 mA


2 0rf

swcbit IE

F

ccc

swj

c

RI

00 2 F

F

Bit energy


39



39

Driving Ability



Fan-out 14 splitter


(STP2) was used

40

N


40

Connectability



Lmax ~ 1 mm

Iout vs Lwire



41


41

Robustness



42



42





Bias Current 360 mA

JJ number 83736




and inductances




43

Density


13times25 mm2


25times40 mm2

Excitation line

(upper layers)

Transformer

(lower layers)



Si Substrate

SiO 2

Nb JJ

Mo Resistor

AlOx

BAS (M2) ＧＣ

RC RC

JC

BC

COU (M3)

BAS (M2)

COU (M3)

CC CC

COU

CTL (M4) CTL (M4)

SiO 2


I1+I2+I3 +I4 (700 nm)

I5 (500 nm)

CC

CTL (M4)

CC

IN1 (100 nm)

Nb Pd - NW2 (40 nm + 40 nm) IN2 (100 nm)




~ 03M gatecm2

44


44




transformer can be



Schematic of an

AQFP buffer

15 mm x 20 mm


AIST HSTP process

MIT LL process

(SFQ5ee)


20 mm x 40 mm

45


45

Design Methodology



46

(

accbba

cbax

　　

MAJ (

ab

ba

bax

　　

　　

1MAJ azyx


Buffer 13-branch

NOT

1-constant


46


46


47





47


47

AQFP Logic Design


like Lego blocks


amp data flow

Inputs Phase 1

Phase 2

Phase 3

Phase 1

Phase 2

Phase 3

Phase 1

Outputs

Data

flo

w

AQFP design flow

48


48


49






49


Q Xu et al IEEE TAS 27 1301905 (2017)


49



50


50


Design Flow



ahead adder

12-bit instruction

decoder

Correct

operation

confirmed

1090 JJ

7100 JJ






51


51








~ 24 kBTjunction

5 GHz

52




52





5-GHz 4-phse

clock latency

~ 50 ps




Delay-line

clock latency

~ 5 ps

53


53







54


54



DGP HSTP


T Ando et al SUST 30 (2017) 075003

55



55




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66


(L q) = (10 30)

(L q) = (08 04)


Adiabatic-mode QFP

26



26



in AQFP change

adiabatically Ph

ase

diffe

ren

ce

s

Excitation flux

27



27


11000 of RSFQ

E

S

q

L

fEnergy dissipation


(L L)



28

Robust AQFP Design

(02 16)



(02 16)





29


29


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf


Damping

resistance



30



30


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf



31



31


Finite Temperatures


(L q) = (02 16) Ic = 50 mA




42 110 plusmn194

12 386 plusmn138

20 232 plusmn88


32


32




electronics




Future directions



Summary

33


33



Functionality

Speed

Energy consumption

Driving ability

Connectability

Robustness

Density

34


34


Excitation

Outputs

x2 = 05

(L q) = (02 16)

Ic = 50 mA

Iin1 = 5 mA

Lin = Lq kq = 03

35



35

Gain


If we assume



Ic dIin ~ 50


Iin ~ 20 mA Ic = 100 mA





36


36

Functionality



-



Buffer NOT



Majority a b c

x



37


37

Speed






119871119886119905119890119899119888119910 =119888119897119900119888119896 119901119890119903119894119900119889

119899119906119898119887119890119903 119900119891 119901ℎ119886119904119890


38


38

Energy Consumption




c is 1000 ps Ic = 50 mA


2 0rf

swcbit IE

F

ccc

swj

c

RI

00 2 F

F

Bit energy


39



39

Driving Ability



Fan-out 14 splitter


(STP2) was used

40

N


40

Connectability



Lmax ~ 1 mm

Iout vs Lwire



41


41

Robustness



42



42





Bias Current 360 mA

JJ number 83736




and inductances




43

Density


13times25 mm2


25times40 mm2

Excitation line

(upper layers)

Transformer

(lower layers)



Si Substrate

SiO 2

Nb JJ

Mo Resistor

AlOx

BAS (M2) ＧＣ

RC RC

JC

BC

COU (M3)

BAS (M2)

COU (M3)

CC CC

COU

CTL (M4) CTL (M4)

SiO 2


I1+I2+I3 +I4 (700 nm)

I5 (500 nm)

CC

CTL (M4)

CC

IN1 (100 nm)

Nb Pd - NW2 (40 nm + 40 nm) IN2 (100 nm)




~ 03M gatecm2

44


44




transformer can be



Schematic of an

AQFP buffer

15 mm x 20 mm


AIST HSTP process

MIT LL process

(SFQ5ee)


20 mm x 40 mm

45


45

Design Methodology



46

(

accbba

cbax

　　

MAJ (

ab

ba

bax

　　

　　

1MAJ azyx


Buffer 13-branch

NOT

1-constant


46


46


47





47


47

AQFP Logic Design


like Lego blocks


amp data flow

Inputs Phase 1

Phase 2

Phase 3

Phase 1

Phase 2

Phase 3

Phase 1

Outputs

Data

flo

w

AQFP design flow

48


48


49






49


Q Xu et al IEEE TAS 27 1301905 (2017)


49



50


50


Design Flow



ahead adder

12-bit instruction

decoder

Correct

operation

confirmed

1090 JJ

7100 JJ






51


51








~ 24 kBTjunction

5 GHz

52




52





5-GHz 4-phse

clock latency

~ 50 ps




Delay-line

clock latency

~ 5 ps

53


53







54


54



DGP HSTP


T Ando et al SUST 30 (2017) 075003

55



55




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66



in AQFP change

adiabatically Ph

ase

diffe

ren

ce

s

Excitation flux

27



27


11000 of RSFQ

E

S

q

L

fEnergy dissipation


(L L)



28

Robust AQFP Design

(02 16)



(02 16)





29


29


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf


Damping

resistance



30



30


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf



31



31


Finite Temperatures


(L q) = (02 16) Ic = 50 mA




42 110 plusmn194

12 386 plusmn138

20 232 plusmn88


32


32




electronics




Future directions



Summary

33


33



Functionality

Speed

Energy consumption

Driving ability

Connectability

Robustness

Density

34


34


Excitation

Outputs

x2 = 05

(L q) = (02 16)

Ic = 50 mA

Iin1 = 5 mA

Lin = Lq kq = 03

35



35

Gain


If we assume



Ic dIin ~ 50


Iin ~ 20 mA Ic = 100 mA





36


36

Functionality



-



Buffer NOT



Majority a b c

x



37


37

Speed






119871119886119905119890119899119888119910 =119888119897119900119888119896 119901119890119903119894119900119889

119899119906119898119887119890119903 119900119891 119901ℎ119886119904119890


38


38

Energy Consumption




c is 1000 ps Ic = 50 mA


2 0rf

swcbit IE

F

ccc

swj

c

RI

00 2 F

F

Bit energy


39



39

Driving Ability



Fan-out 14 splitter


(STP2) was used

40

N


40

Connectability



Lmax ~ 1 mm

Iout vs Lwire



41


41

Robustness



42



42





Bias Current 360 mA

JJ number 83736




and inductances




43

Density


13times25 mm2


25times40 mm2

Excitation line

(upper layers)

Transformer

(lower layers)



Si Substrate

SiO 2

Nb JJ

Mo Resistor

AlOx

BAS (M2) ＧＣ

RC RC

JC

BC

COU (M3)

BAS (M2)

COU (M3)

CC CC

COU

CTL (M4) CTL (M4)

SiO 2


I1+I2+I3 +I4 (700 nm)

I5 (500 nm)

CC

CTL (M4)

CC

IN1 (100 nm)

Nb Pd - NW2 (40 nm + 40 nm) IN2 (100 nm)




~ 03M gatecm2

44


44




transformer can be



Schematic of an

AQFP buffer

15 mm x 20 mm


AIST HSTP process

MIT LL process

(SFQ5ee)


20 mm x 40 mm

45


45

Design Methodology



46

(

accbba

cbax

　　

MAJ (

ab

ba

bax

　　

　　

1MAJ azyx


Buffer 13-branch

NOT

1-constant


46


46


47





47


47

AQFP Logic Design


like Lego blocks


amp data flow

Inputs Phase 1

Phase 2

Phase 3

Phase 1

Phase 2

Phase 3

Phase 1

Outputs

Data

flo

w

AQFP design flow

48


48


49






49


Q Xu et al IEEE TAS 27 1301905 (2017)


49



50


50


Design Flow



ahead adder

12-bit instruction

decoder

Correct

operation

confirmed

1090 JJ

7100 JJ






51


51








~ 24 kBTjunction

5 GHz

52




52





5-GHz 4-phse

clock latency

~ 50 ps




Delay-line

clock latency

~ 5 ps

53


53







54


54



DGP HSTP


T Ando et al SUST 30 (2017) 075003

55



55




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66


11000 of RSFQ

E

S

q

L

fEnergy dissipation


(L L)



28

Robust AQFP Design

(02 16)



(02 16)





29


29


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf


Damping

resistance



30



30


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf



31



31


Finite Temperatures


(L q) = (02 16) Ic = 50 mA




42 110 plusmn194

12 386 plusmn138

20 232 plusmn88


32


32




electronics




Future directions



Summary

33


33



Functionality

Speed

Energy consumption

Driving ability

Connectability

Robustness

Density

34


34


Excitation

Outputs

x2 = 05

(L q) = (02 16)

Ic = 50 mA

Iin1 = 5 mA

Lin = Lq kq = 03

35



35

Gain


If we assume



Ic dIin ~ 50


Iin ~ 20 mA Ic = 100 mA





36


36

Functionality



-



Buffer NOT



Majority a b c

x



37


37

Speed






119871119886119905119890119899119888119910 =119888119897119900119888119896 119901119890119903119894119900119889

119899119906119898119887119890119903 119900119891 119901ℎ119886119904119890


38


38

Energy Consumption




c is 1000 ps Ic = 50 mA


2 0rf

swcbit IE

F

ccc

swj

c

RI

00 2 F

F

Bit energy


39



39

Driving Ability



Fan-out 14 splitter


(STP2) was used

40

N


40

Connectability



Lmax ~ 1 mm

Iout vs Lwire



41


41

Robustness



42



42





Bias Current 360 mA

JJ number 83736




and inductances




43

Density


13times25 mm2


25times40 mm2

Excitation line

(upper layers)

Transformer

(lower layers)



Si Substrate

SiO 2

Nb JJ

Mo Resistor

AlOx

BAS (M2) ＧＣ

RC RC

JC

BC

COU (M3)

BAS (M2)

COU (M3)

CC CC

COU

CTL (M4) CTL (M4)

SiO 2


I1+I2+I3 +I4 (700 nm)

I5 (500 nm)

CC

CTL (M4)

CC

IN1 (100 nm)

Nb Pd - NW2 (40 nm + 40 nm) IN2 (100 nm)




~ 03M gatecm2

44


44




transformer can be



Schematic of an

AQFP buffer

15 mm x 20 mm


AIST HSTP process

MIT LL process

(SFQ5ee)


20 mm x 40 mm

45


45

Design Methodology



46

(

accbba

cbax

　　

MAJ (

ab

ba

bax

　　

　　

1MAJ azyx


Buffer 13-branch

NOT

1-constant


46


46


47





47


47

AQFP Logic Design


like Lego blocks


amp data flow

Inputs Phase 1

Phase 2

Phase 3

Phase 1

Phase 2

Phase 3

Phase 1

Outputs

Data

flo

w

AQFP design flow

48


48


49






49


Q Xu et al IEEE TAS 27 1301905 (2017)


49



50


50


Design Flow



ahead adder

12-bit instruction

decoder

Correct

operation

confirmed

1090 JJ

7100 JJ






51


51








~ 24 kBTjunction

5 GHz

52




52





5-GHz 4-phse

clock latency

~ 50 ps




Delay-line

clock latency

~ 5 ps

53


53







54


54



DGP HSTP


T Ando et al SUST 30 (2017) 075003

55



55




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66

Robust AQFP Design

(02 16)



(02 16)





29


29


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf


Damping

resistance



30



30


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf



31



31


Finite Temperatures


(L q) = (02 16) Ic = 50 mA




42 110 plusmn194

12 386 plusmn138

20 232 plusmn88


32


32




electronics




Future directions



Summary

33


33



Functionality

Speed

Energy consumption

Driving ability

Connectability

Robustness

Density

34


34


Excitation

Outputs

x2 = 05

(L q) = (02 16)

Ic = 50 mA

Iin1 = 5 mA

Lin = Lq kq = 03

35



35

Gain


If we assume



Ic dIin ~ 50


Iin ~ 20 mA Ic = 100 mA





36


36

Functionality



-



Buffer NOT



Majority a b c

x



37


37

Speed






119871119886119905119890119899119888119910 =119888119897119900119888119896 119901119890119903119894119900119889

119899119906119898119887119890119903 119900119891 119901ℎ119886119904119890


38


38

Energy Consumption




c is 1000 ps Ic = 50 mA


2 0rf

swcbit IE

F

ccc

swj

c

RI

00 2 F

F

Bit energy


39



39

Driving Ability



Fan-out 14 splitter


(STP2) was used

40

N


40

Connectability



Lmax ~ 1 mm

Iout vs Lwire



41


41

Robustness



42



42





Bias Current 360 mA

JJ number 83736




and inductances




43

Density


13times25 mm2


25times40 mm2

Excitation line

(upper layers)

Transformer

(lower layers)



Si Substrate

SiO 2

Nb JJ

Mo Resistor

AlOx

BAS (M2) ＧＣ

RC RC

JC

BC

COU (M3)

BAS (M2)

COU (M3)

CC CC

COU

CTL (M4) CTL (M4)

SiO 2


I1+I2+I3 +I4 (700 nm)

I5 (500 nm)

CC

CTL (M4)

CC

IN1 (100 nm)

Nb Pd - NW2 (40 nm + 40 nm) IN2 (100 nm)




~ 03M gatecm2

44


44




transformer can be



Schematic of an

AQFP buffer

15 mm x 20 mm


AIST HSTP process

MIT LL process

(SFQ5ee)


20 mm x 40 mm

45


45

Design Methodology



46

(

accbba

cbax

　　

MAJ (

ab

ba

bax

　　

　　

1MAJ azyx


Buffer 13-branch

NOT

1-constant


46


46


47





47


47

AQFP Logic Design


like Lego blocks


amp data flow

Inputs Phase 1

Phase 2

Phase 3

Phase 1

Phase 2

Phase 3

Phase 1

Outputs

Data

flo

w

AQFP design flow

48


48


49






49


Q Xu et al IEEE TAS 27 1301905 (2017)


49



50


50


Design Flow



ahead adder

12-bit instruction

decoder

Correct

operation

confirmed

1090 JJ

7100 JJ






51


51








~ 24 kBTjunction

5 GHz

52




52





5-GHz 4-phse

clock latency

~ 50 ps




Delay-line

clock latency

~ 5 ps

53


53







54


54



DGP HSTP


T Ando et al SUST 30 (2017) 075003

55



55




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf


Damping

resistance



30



30


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf



31



31


Finite Temperatures


(L q) = (02 16) Ic = 50 mA




42 110 plusmn194

12 386 plusmn138

20 232 plusmn88


32


32




electronics




Future directions



Summary

33


33



Functionality

Speed

Energy consumption

Driving ability

Connectability

Robustness

Density

34


34


Excitation

Outputs

x2 = 05

(L q) = (02 16)

Ic = 50 mA

Iin1 = 5 mA

Lin = Lq kq = 03

35



35

Gain


If we assume



Ic dIin ~ 50


Iin ~ 20 mA Ic = 100 mA





36


36

Functionality



-



Buffer NOT



Majority a b c

x



37


37

Speed






119871119886119905119890119899119888119910 =119888119897119900119888119896 119901119890119903119894119900119889

119899119906119898119887119890119903 119900119891 119901ℎ119886119904119890


38


38

Energy Consumption




c is 1000 ps Ic = 50 mA


2 0rf

swcbit IE

F

ccc

swj

c

RI

00 2 F

F

Bit energy


39



39

Driving Ability



Fan-out 14 splitter


(STP2) was used

40

N


40

Connectability



Lmax ~ 1 mm

Iout vs Lwire



41


41

Robustness



42



42





Bias Current 360 mA

JJ number 83736




and inductances




43

Density


13times25 mm2


25times40 mm2

Excitation line

(upper layers)

Transformer

(lower layers)



Si Substrate

SiO 2

Nb JJ

Mo Resistor

AlOx

BAS (M2) ＧＣ

RC RC

JC

BC

COU (M3)

BAS (M2)

COU (M3)

CC CC

COU

CTL (M4) CTL (M4)

SiO 2


I1+I2+I3 +I4 (700 nm)

I5 (500 nm)

CC

CTL (M4)

CC

IN1 (100 nm)

Nb Pd - NW2 (40 nm + 40 nm) IN2 (100 nm)




~ 03M gatecm2

44


44




transformer can be



Schematic of an

AQFP buffer

15 mm x 20 mm


AIST HSTP process

MIT LL process

(SFQ5ee)


20 mm x 40 mm

45


45

Design Methodology



46

(

accbba

cbax

　　

MAJ (

ab

ba

bax

　　

　　

1MAJ azyx


Buffer 13-branch

NOT

1-constant


46


46


47





47


47

AQFP Logic Design


like Lego blocks


amp data flow

Inputs Phase 1

Phase 2

Phase 3

Phase 1

Phase 2

Phase 3

Phase 1

Outputs

Data

flo

w

AQFP design flow

48


48


49






49


Q Xu et al IEEE TAS 27 1301905 (2017)


49



50


50


Design Flow



ahead adder

12-bit instruction

decoder

Correct

operation

confirmed

1090 JJ

7100 JJ






51


51








~ 24 kBTjunction

5 GHz

52




52





5-GHz 4-phse

clock latency

~ 50 ps




Delay-line

clock latency

~ 5 ps

53


53







54


54



DGP HSTP


T Ando et al SUST 30 (2017) 075003

55



55




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66


2 0rf

swcbit IE

F

Bit Energy



cccsw

I

C

RI

00 2 F

F

rf



31



31


Finite Temperatures


(L q) = (02 16) Ic = 50 mA




42 110 plusmn194

12 386 plusmn138

20 232 plusmn88


32


32




electronics




Future directions



Summary

33


33



Functionality

Speed

Energy consumption

Driving ability

Connectability

Robustness

Density

34


34


Excitation

Outputs

x2 = 05

(L q) = (02 16)

Ic = 50 mA

Iin1 = 5 mA

Lin = Lq kq = 03

35



35

Gain


If we assume



Ic dIin ~ 50


Iin ~ 20 mA Ic = 100 mA





36


36

Functionality



-



Buffer NOT



Majority a b c

x



37


37

Speed






119871119886119905119890119899119888119910 =119888119897119900119888119896 119901119890119903119894119900119889

119899119906119898119887119890119903 119900119891 119901ℎ119886119904119890


38


38

Energy Consumption




c is 1000 ps Ic = 50 mA


2 0rf

swcbit IE

F

ccc

swj

c

RI

00 2 F

F

Bit energy


39



39

Driving Ability



Fan-out 14 splitter


(STP2) was used

40

N


40

Connectability



Lmax ~ 1 mm

Iout vs Lwire



41


41

Robustness



42



42





Bias Current 360 mA

JJ number 83736




and inductances




43

Density


13times25 mm2


25times40 mm2

Excitation line

(upper layers)

Transformer

(lower layers)



Si Substrate

SiO 2

Nb JJ

Mo Resistor

AlOx

BAS (M2) ＧＣ

RC RC

JC

BC

COU (M3)

BAS (M2)

COU (M3)

CC CC

COU

CTL (M4) CTL (M4)

SiO 2


I1+I2+I3 +I4 (700 nm)

I5 (500 nm)

CC

CTL (M4)

CC

IN1 (100 nm)

Nb Pd - NW2 (40 nm + 40 nm) IN2 (100 nm)




~ 03M gatecm2

44


44




transformer can be



Schematic of an

AQFP buffer

15 mm x 20 mm


AIST HSTP process

MIT LL process

(SFQ5ee)


20 mm x 40 mm

45


45

Design Methodology



46

(

accbba

cbax

　　

MAJ (

ab

ba

bax

　　

　　

1MAJ azyx


Buffer 13-branch

NOT

1-constant


46


46


47





47


47

AQFP Logic Design


like Lego blocks


amp data flow

Inputs Phase 1

Phase 2

Phase 3

Phase 1

Phase 2

Phase 3

Phase 1

Outputs

Data

flo

w

AQFP design flow

48


48


49






49


Q Xu et al IEEE TAS 27 1301905 (2017)


49



50


50


Design Flow



ahead adder

12-bit instruction

decoder

Correct

operation

confirmed

1090 JJ

7100 JJ






51


51








~ 24 kBTjunction

5 GHz

52




52





5-GHz 4-phse

clock latency

~ 50 ps




Delay-line

clock latency

~ 5 ps

53


53







54


54



DGP HSTP


T Ando et al SUST 30 (2017) 075003

55



55




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66


Finite Temperatures


(L q) = (02 16) Ic = 50 mA




42 110 plusmn194

12 386 plusmn138

20 232 plusmn88


32


32




electronics




Future directions



Summary

33


33



Functionality

Speed

Energy consumption

Driving ability

Connectability

Robustness

Density

34


34


Excitation

Outputs

x2 = 05

(L q) = (02 16)

Ic = 50 mA

Iin1 = 5 mA

Lin = Lq kq = 03

35



35

Gain


If we assume



Ic dIin ~ 50


Iin ~ 20 mA Ic = 100 mA





36


36

Functionality



-



Buffer NOT



Majority a b c

x



37


37

Speed






119871119886119905119890119899119888119910 =119888119897119900119888119896 119901119890119903119894119900119889

119899119906119898119887119890119903 119900119891 119901ℎ119886119904119890


38


38

Energy Consumption




c is 1000 ps Ic = 50 mA


2 0rf

swcbit IE

F

ccc

swj

c

RI

00 2 F

F

Bit energy


39



39

Driving Ability



Fan-out 14 splitter


(STP2) was used

40

N


40

Connectability



Lmax ~ 1 mm

Iout vs Lwire



41


41

Robustness



42



42





Bias Current 360 mA

JJ number 83736




and inductances




43

Density


13times25 mm2


25times40 mm2

Excitation line

(upper layers)

Transformer

(lower layers)



Si Substrate

SiO 2

Nb JJ

Mo Resistor

AlOx

BAS (M2) ＧＣ

RC RC

JC

BC

COU (M3)

BAS (M2)

COU (M3)

CC CC

COU

CTL (M4) CTL (M4)

SiO 2


I1+I2+I3 +I4 (700 nm)

I5 (500 nm)

CC

CTL (M4)

CC

IN1 (100 nm)

Nb Pd - NW2 (40 nm + 40 nm) IN2 (100 nm)




~ 03M gatecm2

44


44




transformer can be



Schematic of an

AQFP buffer

15 mm x 20 mm


AIST HSTP process

MIT LL process

(SFQ5ee)


20 mm x 40 mm

45


45

Design Methodology



46

(

accbba

cbax

　　

MAJ (

ab

ba

bax

　　

　　

1MAJ azyx


Buffer 13-branch

NOT

1-constant


46


46


47





47


47

AQFP Logic Design


like Lego blocks


amp data flow

Inputs Phase 1

Phase 2

Phase 3

Phase 1

Phase 2

Phase 3

Phase 1

Outputs

Data

flo

w

AQFP design flow

48


48


49






49


Q Xu et al IEEE TAS 27 1301905 (2017)


49



50


50


Design Flow



ahead adder

12-bit instruction

decoder

Correct

operation

confirmed

1090 JJ

7100 JJ






51


51








~ 24 kBTjunction

5 GHz

52




52





5-GHz 4-phse

clock latency

~ 50 ps




Delay-line

clock latency

~ 5 ps

53


53







54


54



DGP HSTP


T Ando et al SUST 30 (2017) 075003

55



55




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66




electronics




Future directions



Summary

33


33



Functionality

Speed

Energy consumption

Driving ability

Connectability

Robustness

Density

34


34


Excitation

Outputs

x2 = 05

(L q) = (02 16)

Ic = 50 mA

Iin1 = 5 mA

Lin = Lq kq = 03

35



35

Gain


If we assume



Ic dIin ~ 50


Iin ~ 20 mA Ic = 100 mA





36


36

Functionality



-



Buffer NOT



Majority a b c

x



37


37

Speed






119871119886119905119890119899119888119910 =119888119897119900119888119896 119901119890119903119894119900119889

119899119906119898119887119890119903 119900119891 119901ℎ119886119904119890


38


38

Energy Consumption




c is 1000 ps Ic = 50 mA


2 0rf

swcbit IE

F

ccc

swj

c

RI

00 2 F

F

Bit energy


39



39

Driving Ability



Fan-out 14 splitter


(STP2) was used

40

N


40

Connectability



Lmax ~ 1 mm

Iout vs Lwire



41


41

Robustness



42



42





Bias Current 360 mA

JJ number 83736




and inductances




43

Density


13times25 mm2


25times40 mm2

Excitation line

(upper layers)

Transformer

(lower layers)



Si Substrate

SiO 2

Nb JJ

Mo Resistor

AlOx

BAS (M2) ＧＣ

RC RC

JC

BC

COU (M3)

BAS (M2)

COU (M3)

CC CC

COU

CTL (M4) CTL (M4)

SiO 2


I1+I2+I3 +I4 (700 nm)

I5 (500 nm)

CC

CTL (M4)

CC

IN1 (100 nm)

Nb Pd - NW2 (40 nm + 40 nm) IN2 (100 nm)




~ 03M gatecm2

44


44




transformer can be



Schematic of an

AQFP buffer

15 mm x 20 mm


AIST HSTP process

MIT LL process

(SFQ5ee)


20 mm x 40 mm

45


45

Design Methodology



46

(

accbba

cbax

　　

MAJ (

ab

ba

bax

　　

　　

1MAJ azyx


Buffer 13-branch

NOT

1-constant


46


46


47





47


47

AQFP Logic Design


like Lego blocks


amp data flow

Inputs Phase 1

Phase 2

Phase 3

Phase 1

Phase 2

Phase 3

Phase 1

Outputs

Data

flo

w

AQFP design flow

48


48


49






49


Q Xu et al IEEE TAS 27 1301905 (2017)


49



50


50


Design Flow



ahead adder

12-bit instruction

decoder

Correct

operation

confirmed

1090 JJ

7100 JJ






51


51








~ 24 kBTjunction

5 GHz

52




52





5-GHz 4-phse

clock latency

~ 50 ps




Delay-line

clock latency

~ 5 ps

53


53







54


54



DGP HSTP


T Ando et al SUST 30 (2017) 075003

55



55




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66



Functionality

Speed

Energy consumption

Driving ability

Connectability

Robustness

Density

34


34


Excitation

Outputs

x2 = 05

(L q) = (02 16)

Ic = 50 mA

Iin1 = 5 mA

Lin = Lq kq = 03

35



35

Gain


If we assume



Ic dIin ~ 50


Iin ~ 20 mA Ic = 100 mA





36


36

Functionality



-



Buffer NOT



Majority a b c

x



37


37

Speed






119871119886119905119890119899119888119910 =119888119897119900119888119896 119901119890119903119894119900119889

119899119906119898119887119890119903 119900119891 119901ℎ119886119904119890


38


38

Energy Consumption




c is 1000 ps Ic = 50 mA


2 0rf

swcbit IE

F

ccc

swj

c

RI

00 2 F

F

Bit energy


39



39

Driving Ability



Fan-out 14 splitter


(STP2) was used

40

N


40

Connectability



Lmax ~ 1 mm

Iout vs Lwire



41


41

Robustness



42



42





Bias Current 360 mA

JJ number 83736




and inductances




43

Density


13times25 mm2


25times40 mm2

Excitation line

(upper layers)

Transformer

(lower layers)



Si Substrate

SiO 2

Nb JJ

Mo Resistor

AlOx

BAS (M2) ＧＣ

RC RC

JC

BC

COU (M3)

BAS (M2)

COU (M3)

CC CC

COU

CTL (M4) CTL (M4)

SiO 2


I1+I2+I3 +I4 (700 nm)

I5 (500 nm)

CC

CTL (M4)

CC

IN1 (100 nm)

Nb Pd - NW2 (40 nm + 40 nm) IN2 (100 nm)




~ 03M gatecm2

44


44




transformer can be



Schematic of an

AQFP buffer

15 mm x 20 mm


AIST HSTP process

MIT LL process

(SFQ5ee)


20 mm x 40 mm

45


45

Design Methodology



46

(

accbba

cbax

　　

MAJ (

ab

ba

bax

　　

　　

1MAJ azyx


Buffer 13-branch

NOT

1-constant


46


46


47





47


47

AQFP Logic Design


like Lego blocks


amp data flow

Inputs Phase 1

Phase 2

Phase 3

Phase 1

Phase 2

Phase 3

Phase 1

Outputs

Data

flo

w

AQFP design flow

48


48


49






49


Q Xu et al IEEE TAS 27 1301905 (2017)


49



50


50


Design Flow



ahead adder

12-bit instruction

decoder

Correct

operation

confirmed

1090 JJ

7100 JJ






51


51








~ 24 kBTjunction

5 GHz

52




52





5-GHz 4-phse

clock latency

~ 50 ps




Delay-line

clock latency

~ 5 ps

53


53







54


54



DGP HSTP


T Ando et al SUST 30 (2017) 075003

55



55




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66


Excitation

Outputs

x2 = 05

(L q) = (02 16)

Ic = 50 mA

Iin1 = 5 mA

Lin = Lq kq = 03

35



35

Gain


If we assume



Ic dIin ~ 50


Iin ~ 20 mA Ic = 100 mA





36


36

Functionality



-



Buffer NOT



Majority a b c

x



37


37

Speed






119871119886119905119890119899119888119910 =119888119897119900119888119896 119901119890119903119894119900119889

119899119906119898119887119890119903 119900119891 119901ℎ119886119904119890


38


38

Energy Consumption




c is 1000 ps Ic = 50 mA


2 0rf

swcbit IE

F

ccc

swj

c

RI

00 2 F

F

Bit energy


39



39

Driving Ability



Fan-out 14 splitter


(STP2) was used

40

N


40

Connectability



Lmax ~ 1 mm

Iout vs Lwire



41


41

Robustness



42



42





Bias Current 360 mA

JJ number 83736




and inductances




43

Density


13times25 mm2


25times40 mm2

Excitation line

(upper layers)

Transformer

(lower layers)



Si Substrate

SiO 2

Nb JJ

Mo Resistor

AlOx

BAS (M2) ＧＣ

RC RC

JC

BC

COU (M3)

BAS (M2)

COU (M3)

CC CC

COU

CTL (M4) CTL (M4)

SiO 2


I1+I2+I3 +I4 (700 nm)

I5 (500 nm)

CC

CTL (M4)

CC

IN1 (100 nm)

Nb Pd - NW2 (40 nm + 40 nm) IN2 (100 nm)




~ 03M gatecm2

44


44




transformer can be



Schematic of an

AQFP buffer

15 mm x 20 mm


AIST HSTP process

MIT LL process

(SFQ5ee)


20 mm x 40 mm

45


45

Design Methodology



46

(

accbba

cbax

　　

MAJ (

ab

ba

bax

　　

　　

1MAJ azyx


Buffer 13-branch

NOT

1-constant


46


46


47





47


47

AQFP Logic Design


like Lego blocks


amp data flow

Inputs Phase 1

Phase 2

Phase 3

Phase 1

Phase 2

Phase 3

Phase 1

Outputs

Data

flo

w

AQFP design flow

48


48


49






49


Q Xu et al IEEE TAS 27 1301905 (2017)


49



50


50


Design Flow



ahead adder

12-bit instruction

decoder

Correct

operation

confirmed

1090 JJ

7100 JJ






51


51








~ 24 kBTjunction

5 GHz

52




52





5-GHz 4-phse

clock latency

~ 50 ps




Delay-line

clock latency

~ 5 ps

53


53







54


54



DGP HSTP


T Ando et al SUST 30 (2017) 075003

55



55




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66

Gain


If we assume



Ic dIin ~ 50


Iin ~ 20 mA Ic = 100 mA





36


36

Functionality



-



Buffer NOT



Majority a b c

x



37


37

Speed






119871119886119905119890119899119888119910 =119888119897119900119888119896 119901119890119903119894119900119889

119899119906119898119887119890119903 119900119891 119901ℎ119886119904119890


38


38

Energy Consumption




c is 1000 ps Ic = 50 mA


2 0rf

swcbit IE

F

ccc

swj

c

RI

00 2 F

F

Bit energy


39



39

Driving Ability



Fan-out 14 splitter


(STP2) was used

40

N


40

Connectability



Lmax ~ 1 mm

Iout vs Lwire



41


41

Robustness



42



42





Bias Current 360 mA

JJ number 83736




and inductances




43

Density


13times25 mm2


25times40 mm2

Excitation line

(upper layers)

Transformer

(lower layers)



Si Substrate

SiO 2

Nb JJ

Mo Resistor

AlOx

BAS (M2) ＧＣ

RC RC

JC

BC

COU (M3)

BAS (M2)

COU (M3)

CC CC

COU

CTL (M4) CTL (M4)

SiO 2


I1+I2+I3 +I4 (700 nm)

I5 (500 nm)

CC

CTL (M4)

CC

IN1 (100 nm)

Nb Pd - NW2 (40 nm + 40 nm) IN2 (100 nm)




~ 03M gatecm2

44


44




transformer can be



Schematic of an

AQFP buffer

15 mm x 20 mm


AIST HSTP process

MIT LL process

(SFQ5ee)


20 mm x 40 mm

45


45

Design Methodology



46

(

accbba

cbax

　　

MAJ (

ab

ba

bax

　　

　　

1MAJ azyx


Buffer 13-branch

NOT

1-constant


46


46


47





47


47

AQFP Logic Design


like Lego blocks


amp data flow

Inputs Phase 1

Phase 2

Phase 3

Phase 1

Phase 2

Phase 3

Phase 1

Outputs

Data

flo

w

AQFP design flow

48


48


49






49


Q Xu et al IEEE TAS 27 1301905 (2017)


49



50


50


Design Flow



ahead adder

12-bit instruction

decoder

Correct

operation

confirmed

1090 JJ

7100 JJ






51


51








~ 24 kBTjunction

5 GHz

52




52





5-GHz 4-phse

clock latency

~ 50 ps




Delay-line

clock latency

~ 5 ps

53


53







54


54



DGP HSTP


T Ando et al SUST 30 (2017) 075003

55



55




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66

Functionality



-



Buffer NOT



Majority a b c

x



37


37

Speed






119871119886119905119890119899119888119910 =119888119897119900119888119896 119901119890119903119894119900119889

119899119906119898119887119890119903 119900119891 119901ℎ119886119904119890


38


38

Energy Consumption




c is 1000 ps Ic = 50 mA


2 0rf

swcbit IE

F

ccc

swj

c

RI

00 2 F

F

Bit energy


39



39

Driving Ability



Fan-out 14 splitter


(STP2) was used

40

N


40

Connectability



Lmax ~ 1 mm

Iout vs Lwire



41


41

Robustness



42



42





Bias Current 360 mA

JJ number 83736




and inductances




43

Density


13times25 mm2


25times40 mm2

Excitation line

(upper layers)

Transformer

(lower layers)



Si Substrate

SiO 2

Nb JJ

Mo Resistor

AlOx

BAS (M2) ＧＣ

RC RC

JC

BC

COU (M3)

BAS (M2)

COU (M3)

CC CC

COU

CTL (M4) CTL (M4)

SiO 2


I1+I2+I3 +I4 (700 nm)

I5 (500 nm)

CC

CTL (M4)

CC

IN1 (100 nm)

Nb Pd - NW2 (40 nm + 40 nm) IN2 (100 nm)




~ 03M gatecm2

44


44




transformer can be



Schematic of an

AQFP buffer

15 mm x 20 mm


AIST HSTP process

MIT LL process

(SFQ5ee)


20 mm x 40 mm

45


45

Design Methodology



46

(

accbba

cbax

　　

MAJ (

ab

ba

bax

　　

　　

1MAJ azyx


Buffer 13-branch

NOT

1-constant


46


46


47





47


47

AQFP Logic Design


like Lego blocks


amp data flow

Inputs Phase 1

Phase 2

Phase 3

Phase 1

Phase 2

Phase 3

Phase 1

Outputs

Data

flo

w

AQFP design flow

48


48


49






49


Q Xu et al IEEE TAS 27 1301905 (2017)


49



50


50


Design Flow



ahead adder

12-bit instruction

decoder

Correct

operation

confirmed

1090 JJ

7100 JJ






51


51








~ 24 kBTjunction

5 GHz

52




52





5-GHz 4-phse

clock latency

~ 50 ps




Delay-line

clock latency

~ 5 ps

53


53







54


54



DGP HSTP


T Ando et al SUST 30 (2017) 075003

55



55




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66

Speed






119871119886119905119890119899119888119910 =119888119897119900119888119896 119901119890119903119894119900119889

119899119906119898119887119890119903 119900119891 119901ℎ119886119904119890


38


38

Energy Consumption




c is 1000 ps Ic = 50 mA


2 0rf

swcbit IE

F

ccc

swj

c

RI

00 2 F

F

Bit energy


39



39

Driving Ability



Fan-out 14 splitter


(STP2) was used

40

N


40

Connectability



Lmax ~ 1 mm

Iout vs Lwire



41


41

Robustness



42



42





Bias Current 360 mA

JJ number 83736




and inductances




43

Density


13times25 mm2


25times40 mm2

Excitation line

(upper layers)

Transformer

(lower layers)



Si Substrate

SiO 2

Nb JJ

Mo Resistor

AlOx

BAS (M2) ＧＣ

RC RC

JC

BC

COU (M3)

BAS (M2)

COU (M3)

CC CC

COU

CTL (M4) CTL (M4)

SiO 2


I1+I2+I3 +I4 (700 nm)

I5 (500 nm)

CC

CTL (M4)

CC

IN1 (100 nm)

Nb Pd - NW2 (40 nm + 40 nm) IN2 (100 nm)




~ 03M gatecm2

44


44




transformer can be



Schematic of an

AQFP buffer

15 mm x 20 mm


AIST HSTP process

MIT LL process

(SFQ5ee)


20 mm x 40 mm

45


45

Design Methodology



46

(

accbba

cbax

　　

MAJ (

ab

ba

bax

　　

　　

1MAJ azyx


Buffer 13-branch

NOT

1-constant


46


46


47





47


47

AQFP Logic Design


like Lego blocks


amp data flow

Inputs Phase 1

Phase 2

Phase 3

Phase 1

Phase 2

Phase 3

Phase 1

Outputs

Data

flo

w

AQFP design flow

48


48


49






49


Q Xu et al IEEE TAS 27 1301905 (2017)


49



50


50


Design Flow



ahead adder

12-bit instruction

decoder

Correct

operation

confirmed

1090 JJ

7100 JJ






51


51








~ 24 kBTjunction

5 GHz

52




52





5-GHz 4-phse

clock latency

~ 50 ps




Delay-line

clock latency

~ 5 ps

53


53







54


54



DGP HSTP


T Ando et al SUST 30 (2017) 075003

55



55




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66

Energy Consumption




c is 1000 ps Ic = 50 mA


2 0rf

swcbit IE

F

ccc

swj

c

RI

00 2 F

F

Bit energy


39



39

Driving Ability



Fan-out 14 splitter


(STP2) was used

40

N


40

Connectability



Lmax ~ 1 mm

Iout vs Lwire



41


41

Robustness



42



42





Bias Current 360 mA

JJ number 83736




and inductances




43

Density


13times25 mm2


25times40 mm2

Excitation line

(upper layers)

Transformer

(lower layers)



Si Substrate

SiO 2

Nb JJ

Mo Resistor

AlOx

BAS (M2) ＧＣ

RC RC

JC

BC

COU (M3)

BAS (M2)

COU (M3)

CC CC

COU

CTL (M4) CTL (M4)

SiO 2


I1+I2+I3 +I4 (700 nm)

I5 (500 nm)

CC

CTL (M4)

CC

IN1 (100 nm)

Nb Pd - NW2 (40 nm + 40 nm) IN2 (100 nm)




~ 03M gatecm2

44


44




transformer can be



Schematic of an

AQFP buffer

15 mm x 20 mm


AIST HSTP process

MIT LL process

(SFQ5ee)


20 mm x 40 mm

45


45

Design Methodology



46

(

accbba

cbax

　　

MAJ (

ab

ba

bax

　　

　　

1MAJ azyx


Buffer 13-branch

NOT

1-constant


46


46


47





47


47

AQFP Logic Design


like Lego blocks


amp data flow

Inputs Phase 1

Phase 2

Phase 3

Phase 1

Phase 2

Phase 3

Phase 1

Outputs

Data

flo

w

AQFP design flow

48


48


49






49


Q Xu et al IEEE TAS 27 1301905 (2017)


49



50


50


Design Flow



ahead adder

12-bit instruction

decoder

Correct

operation

confirmed

1090 JJ

7100 JJ






51


51








~ 24 kBTjunction

5 GHz

52




52





5-GHz 4-phse

clock latency

~ 50 ps




Delay-line

clock latency

~ 5 ps

53


53







54


54



DGP HSTP


T Ando et al SUST 30 (2017) 075003

55



55




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66

Driving Ability



Fan-out 14 splitter


(STP2) was used

40

N


40

Connectability



Lmax ~ 1 mm

Iout vs Lwire



41


41

Robustness



42



42





Bias Current 360 mA

JJ number 83736




and inductances




43

Density


13times25 mm2


25times40 mm2

Excitation line

(upper layers)

Transformer

(lower layers)



Si Substrate

SiO 2

Nb JJ

Mo Resistor

AlOx

BAS (M2) ＧＣ

RC RC

JC

BC

COU (M3)

BAS (M2)

COU (M3)

CC CC

COU

CTL (M4) CTL (M4)

SiO 2


I1+I2+I3 +I4 (700 nm)

I5 (500 nm)

CC

CTL (M4)

CC

IN1 (100 nm)

Nb Pd - NW2 (40 nm + 40 nm) IN2 (100 nm)




~ 03M gatecm2

44


44




transformer can be



Schematic of an

AQFP buffer

15 mm x 20 mm


AIST HSTP process

MIT LL process

(SFQ5ee)


20 mm x 40 mm

45


45

Design Methodology



46

(

accbba

cbax

　　

MAJ (

ab

ba

bax

　　

　　

1MAJ azyx


Buffer 13-branch

NOT

1-constant


46


46


47





47


47

AQFP Logic Design


like Lego blocks


amp data flow

Inputs Phase 1

Phase 2

Phase 3

Phase 1

Phase 2

Phase 3

Phase 1

Outputs

Data

flo

w

AQFP design flow

48


48


49






49


Q Xu et al IEEE TAS 27 1301905 (2017)


49



50


50


Design Flow



ahead adder

12-bit instruction

decoder

Correct

operation

confirmed

1090 JJ

7100 JJ






51


51








~ 24 kBTjunction

5 GHz

52




52





5-GHz 4-phse

clock latency

~ 50 ps




Delay-line

clock latency

~ 5 ps

53


53







54


54



DGP HSTP


T Ando et al SUST 30 (2017) 075003

55



55




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66

Connectability



Lmax ~ 1 mm

Iout vs Lwire



41


41

Robustness



42



42





Bias Current 360 mA

JJ number 83736




and inductances




43

Density


13times25 mm2


25times40 mm2

Excitation line

(upper layers)

Transformer

(lower layers)



Si Substrate

SiO 2

Nb JJ

Mo Resistor

AlOx

BAS (M2) ＧＣ

RC RC

JC

BC

COU (M3)

BAS (M2)

COU (M3)

CC CC

COU

CTL (M4) CTL (M4)

SiO 2


I1+I2+I3 +I4 (700 nm)

I5 (500 nm)

CC

CTL (M4)

CC

IN1 (100 nm)

Nb Pd - NW2 (40 nm + 40 nm) IN2 (100 nm)




~ 03M gatecm2

44


44




transformer can be



Schematic of an

AQFP buffer

15 mm x 20 mm


AIST HSTP process

MIT LL process

(SFQ5ee)


20 mm x 40 mm

45


45

Design Methodology



46

(

accbba

cbax

　　

MAJ (

ab

ba

bax

　　

　　

1MAJ azyx


Buffer 13-branch

NOT

1-constant


46


46


47





47


47

AQFP Logic Design


like Lego blocks


amp data flow

Inputs Phase 1

Phase 2

Phase 3

Phase 1

Phase 2

Phase 3

Phase 1

Outputs

Data

flo

w

AQFP design flow

48


48


49






49


Q Xu et al IEEE TAS 27 1301905 (2017)


49



50


50


Design Flow



ahead adder

12-bit instruction

decoder

Correct

operation

confirmed

1090 JJ

7100 JJ






51


51








~ 24 kBTjunction

5 GHz

52




52





5-GHz 4-phse

clock latency

~ 50 ps




Delay-line

clock latency

~ 5 ps

53


53







54


54



DGP HSTP


T Ando et al SUST 30 (2017) 075003

55



55




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66

Robustness



42



42





Bias Current 360 mA

JJ number 83736




and inductances




43

Density


13times25 mm2


25times40 mm2

Excitation line

(upper layers)

Transformer

(lower layers)



Si Substrate

SiO 2

Nb JJ

Mo Resistor

AlOx

BAS (M2) ＧＣ

RC RC

JC

BC

COU (M3)

BAS (M2)

COU (M3)

CC CC

COU

CTL (M4) CTL (M4)

SiO 2


I1+I2+I3 +I4 (700 nm)

I5 (500 nm)

CC

CTL (M4)

CC

IN1 (100 nm)

Nb Pd - NW2 (40 nm + 40 nm) IN2 (100 nm)




~ 03M gatecm2

44


44




transformer can be



Schematic of an

AQFP buffer

15 mm x 20 mm


AIST HSTP process

MIT LL process

(SFQ5ee)


20 mm x 40 mm

45


45

Design Methodology



46

(

accbba

cbax

　　

MAJ (

ab

ba

bax

　　

　　

1MAJ azyx


Buffer 13-branch

NOT

1-constant


46


46


47





47


47

AQFP Logic Design


like Lego blocks


amp data flow

Inputs Phase 1

Phase 2

Phase 3

Phase 1

Phase 2

Phase 3

Phase 1

Outputs

Data

flo

w

AQFP design flow

48


48


49






49


Q Xu et al IEEE TAS 27 1301905 (2017)


49



50


50


Design Flow



ahead adder

12-bit instruction

decoder

Correct

operation

confirmed

1090 JJ

7100 JJ






51


51








~ 24 kBTjunction

5 GHz

52




52





5-GHz 4-phse

clock latency

~ 50 ps




Delay-line

clock latency

~ 5 ps

53


53







54


54



DGP HSTP


T Ando et al SUST 30 (2017) 075003

55



55




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66





Bias Current 360 mA

JJ number 83736




and inductances




43

Density


13times25 mm2


25times40 mm2

Excitation line

(upper layers)

Transformer

(lower layers)



Si Substrate

SiO 2

Nb JJ

Mo Resistor

AlOx

BAS (M2) ＧＣ

RC RC

JC

BC

COU (M3)

BAS (M2)

COU (M3)

CC CC

COU

CTL (M4) CTL (M4)

SiO 2


I1+I2+I3 +I4 (700 nm)

I5 (500 nm)

CC

CTL (M4)

CC

IN1 (100 nm)

Nb Pd - NW2 (40 nm + 40 nm) IN2 (100 nm)




~ 03M gatecm2

44


44




transformer can be



Schematic of an

AQFP buffer

15 mm x 20 mm


AIST HSTP process

MIT LL process

(SFQ5ee)


20 mm x 40 mm

45


45

Design Methodology



46

(

accbba

cbax

　　

MAJ (

ab

ba

bax

　　

　　

1MAJ azyx


Buffer 13-branch

NOT

1-constant


46


46


47





47


47

AQFP Logic Design


like Lego blocks


amp data flow

Inputs Phase 1

Phase 2

Phase 3

Phase 1

Phase 2

Phase 3

Phase 1

Outputs

Data

flo

w

AQFP design flow

48


48


49






49


Q Xu et al IEEE TAS 27 1301905 (2017)


49



50


50


Design Flow



ahead adder

12-bit instruction

decoder

Correct

operation

confirmed

1090 JJ

7100 JJ






51


51








~ 24 kBTjunction

5 GHz

52




52





5-GHz 4-phse

clock latency

~ 50 ps




Delay-line

clock latency

~ 5 ps

53


53







54


54



DGP HSTP


T Ando et al SUST 30 (2017) 075003

55



55




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66

Density


13times25 mm2


25times40 mm2

Excitation line

(upper layers)

Transformer

(lower layers)



Si Substrate

SiO 2

Nb JJ

Mo Resistor

AlOx

BAS (M2) ＧＣ

RC RC

JC

BC

COU (M3)

BAS (M2)

COU (M3)

CC CC

COU

CTL (M4) CTL (M4)

SiO 2


I1+I2+I3 +I4 (700 nm)

I5 (500 nm)

CC

CTL (M4)

CC

IN1 (100 nm)

Nb Pd - NW2 (40 nm + 40 nm) IN2 (100 nm)




~ 03M gatecm2

44


44




transformer can be



Schematic of an

AQFP buffer

15 mm x 20 mm


AIST HSTP process

MIT LL process

(SFQ5ee)


20 mm x 40 mm

45


45

Design Methodology



46

(

accbba

cbax

　　

MAJ (

ab

ba

bax

　　

　　

1MAJ azyx


Buffer 13-branch

NOT

1-constant


46


46


47





47


47

AQFP Logic Design


like Lego blocks


amp data flow

Inputs Phase 1

Phase 2

Phase 3

Phase 1

Phase 2

Phase 3

Phase 1

Outputs

Data

flo

w

AQFP design flow

48


48


49






49


Q Xu et al IEEE TAS 27 1301905 (2017)


49



50


50


Design Flow



ahead adder

12-bit instruction

decoder

Correct

operation

confirmed

1090 JJ

7100 JJ






51


51








~ 24 kBTjunction

5 GHz

52




52





5-GHz 4-phse

clock latency

~ 50 ps




Delay-line

clock latency

~ 5 ps

53


53







54


54



DGP HSTP


T Ando et al SUST 30 (2017) 075003

55



55




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66




transformer can be



Schematic of an

AQFP buffer

15 mm x 20 mm


AIST HSTP process

MIT LL process

(SFQ5ee)


20 mm x 40 mm

45


45

Design Methodology



46

(

accbba

cbax

　　

MAJ (

ab

ba

bax

　　

　　

1MAJ azyx


Buffer 13-branch

NOT

1-constant


46


46


47





47


47

AQFP Logic Design


like Lego blocks


amp data flow

Inputs Phase 1

Phase 2

Phase 3

Phase 1

Phase 2

Phase 3

Phase 1

Outputs

Data

flo

w

AQFP design flow

48


48


49






49


Q Xu et al IEEE TAS 27 1301905 (2017)


49



50


50


Design Flow



ahead adder

12-bit instruction

decoder

Correct

operation

confirmed

1090 JJ

7100 JJ






51


51








~ 24 kBTjunction

5 GHz

52




52





5-GHz 4-phse

clock latency

~ 50 ps




Delay-line

clock latency

~ 5 ps

53


53







54


54



DGP HSTP


T Ando et al SUST 30 (2017) 075003

55



55




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66

Design Methodology



46

(

accbba

cbax

　　

MAJ (

ab

ba

bax

　　

　　

1MAJ azyx


Buffer 13-branch

NOT

1-constant


46


46


47





47


47

AQFP Logic Design


like Lego blocks


amp data flow

Inputs Phase 1

Phase 2

Phase 3

Phase 1

Phase 2

Phase 3

Phase 1

Outputs

Data

flo

w

AQFP design flow

48


48


49






49


Q Xu et al IEEE TAS 27 1301905 (2017)


49



50


50


Design Flow



ahead adder

12-bit instruction

decoder

Correct

operation

confirmed

1090 JJ

7100 JJ






51


51








~ 24 kBTjunction

5 GHz

52




52





5-GHz 4-phse

clock latency

~ 50 ps




Delay-line

clock latency

~ 5 ps

53


53







54


54



DGP HSTP


T Ando et al SUST 30 (2017) 075003

55



55




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66


47





47


47

AQFP Logic Design


like Lego blocks


amp data flow

Inputs Phase 1

Phase 2

Phase 3

Phase 1

Phase 2

Phase 3

Phase 1

Outputs

Data

flo

w

AQFP design flow

48


48


49






49


Q Xu et al IEEE TAS 27 1301905 (2017)


49



50


50


Design Flow



ahead adder

12-bit instruction

decoder

Correct

operation

confirmed

1090 JJ

7100 JJ






51


51








~ 24 kBTjunction

5 GHz

52




52





5-GHz 4-phse

clock latency

~ 50 ps




Delay-line

clock latency

~ 5 ps

53


53







54


54



DGP HSTP


T Ando et al SUST 30 (2017) 075003

55



55




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66

AQFP Logic Design


like Lego blocks


amp data flow

Inputs Phase 1

Phase 2

Phase 3

Phase 1

Phase 2

Phase 3

Phase 1

Outputs

Data

flo

w

AQFP design flow

48


48


49






49


Q Xu et al IEEE TAS 27 1301905 (2017)


49



50


50


Design Flow



ahead adder

12-bit instruction

decoder

Correct

operation

confirmed

1090 JJ

7100 JJ






51


51








~ 24 kBTjunction

5 GHz

52




52





5-GHz 4-phse

clock latency

~ 50 ps




Delay-line

clock latency

~ 5 ps

53


53







54


54



DGP HSTP


T Ando et al SUST 30 (2017) 075003

55



55




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66


49






49


Q Xu et al IEEE TAS 27 1301905 (2017)


49



50


50


Design Flow



ahead adder

12-bit instruction

decoder

Correct

operation

confirmed

1090 JJ

7100 JJ






51


51








~ 24 kBTjunction

5 GHz

52




52





5-GHz 4-phse

clock latency

~ 50 ps




Delay-line

clock latency

~ 5 ps

53


53







54


54



DGP HSTP


T Ando et al SUST 30 (2017) 075003

55



55




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66



50


50


Design Flow



ahead adder

12-bit instruction

decoder

Correct

operation

confirmed

1090 JJ

7100 JJ






51


51








~ 24 kBTjunction

5 GHz

52




52





5-GHz 4-phse

clock latency

~ 50 ps




Delay-line

clock latency

~ 5 ps

53


53







54


54



DGP HSTP


T Ando et al SUST 30 (2017) 075003

55



55




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66


Design Flow



ahead adder

12-bit instruction

decoder

Correct

operation

confirmed

1090 JJ

7100 JJ






51


51








~ 24 kBTjunction

5 GHz

52




52





5-GHz 4-phse

clock latency

~ 50 ps




Delay-line

clock latency

~ 5 ps

53


53







54


54



DGP HSTP


T Ando et al SUST 30 (2017) 075003

55



55




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66








~ 24 kBTjunction

5 GHz

52




52





5-GHz 4-phse

clock latency

~ 50 ps




Delay-line

clock latency

~ 5 ps

53


53







54


54



DGP HSTP


T Ando et al SUST 30 (2017) 075003

55



55




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66





5-GHz 4-phse

clock latency

~ 50 ps




Delay-line

clock latency

~ 5 ps

53


53







54


54



DGP HSTP


T Ando et al SUST 30 (2017) 075003

55



55




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66







54


54



DGP HSTP


T Ando et al SUST 30 (2017) 075003

55



55




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66



DGP HSTP


T Ando et al SUST 30 (2017) 075003

55



55




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66




electronics




Future directions



Summary

56


56

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66

Future Directions

Memories


Magnetic memories



Other applications



57


57



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66



64-kb Cryo-CMOS RAM



Concept of hybrid

Josephson-CMOS RAM


a cryo-CMOS memory


58


58



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66



AQFP read-out





decreasing VDD



59


59





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66





Use of low VTH

process

Use of adiabatic

decoder


(nTron)



60


60



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66



nTron chips




and CMOS circuits


Trimming of small

wafers

Josephson circuit

fabrication

61


61



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66



information entropy








101100010100110

62


62



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66



during computation



c p q x y z

0 0 0 0 0 0

0 0 1 0 1 0

0 1 0 0 0 1

0 1 1 0 1 1

1 0 0 1 0 0

1 0 1 1 0 1

1 1 0 1 1 0

1 1 1 1 1 1

Fredkin gate




219-253 (1982)


63


63





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66





AQFP gates



64


64







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66







kBT ln2


65


65

Summary


logic circuits




applications



by using RQFP

66


66

Summary


logic circuits




applications



by using RQFP

66


66

Superconducting computing: present status and perspectives · Phys. Rev. Appl. 4, 034007 (2015)....

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Transcript of Superconducting computing: present status and perspectives · Phys. Rev. Appl. 4, 034007 (2015)....