Lithography

Summer 2000 Yield Management Solutions 27

S P E C I A L F O C U S

Application of Automatic DefectClassification in Photolithography

by Gary Stinson, Microchip Technology Inc. and Bo Magluyan, KLA-Tencor Corporation

This paper presents two applications of Automatic Defect Classification (ADC) to monitor and control defect density inphotolithography processing. These techniques can also apply to any process module. Many defect types are only generatedwhen wafer pattern is present, while other yield impacting defects are detected only on monitor wafers due to a low signal-to-noise ratio on product wafers. The use of ADC in both cases to find root cause solutions is a powerful tool enablingquick time to results and reduced yield risk in the manufacture of integrated circuits.

results generated from such a study is directly depen-dent on the accuracy and purity of the classification ofthe defect.

Microchip’s ADC program, consisting of KLA-Tencor’sIMPACT ADC, 2135 inspection system, and KlarityData Analysis is used extensively in this engineering role.

Case 1: Problem descriptionYield trends for a new device were trending belowexpectations. One of the primary failure modes for thedevice was high standby current. Failure analysisrevealed a trench from metal to substrate causing thehigh standby current failure (Figure 1).

ADC is a powerful technique that has truly come into its own in recent years.Envisioned as a logical progression of defectinspection and review, the ADC concept hasbeen faced with serious technical challengesthat have taken time to overcome. Its pri-mary focus is to replace the manual reviewof defects detected by the inspection sys-tems. Classification accuracy, speed, andcost are all significant factors relating to thejustification of ADC, especially for fabs thatalready have manual classification systemsin place. In this paper another perspectiveconcerning the justification of ADC overmanual review is presented.

Identifying a defect and finding the piece ofequipment or process module that is gener-ating the defect is only the first part ofimproving yields. Eliminating the rootcause is always a difficult task that oftenrequires designed experiments to identifythe defect mechanism. When designedexperiments are used to solve a defect issue,the output response is the number of thedefect type of interest. Depending on thecomplexity of the process, many wafers mayneed to be inspected and reviewed to deter-mine the statistical validity of the changesmade. Additionally, the confidence level of

Figure 1. SEM image of device failure.

Spring 2000 Yield Management Solutions28

S P E C I A L F O C U S

The spatial signature of the defect showed a higherdensity in the center of the wafer. Analysis of multipledie failing for the same bin found that there was a ten-dency for the defect to occur around specific types ofstructures. The source of the defect appeared to bebetween the second poly silicon level and first metaldeposition. The crack would travel along the edge ofthe poly2 until it found relief.

To investigate further, a newly installed KLA-Tencor2135 with IMPACT ADC was brought on-line. Initialinspections prior to Metal1 deposition detected thedefect, which appeared to be a stress-relieving crack inthe dielectric. This was allowing the remaining etchprocesses to trench into the silicon substrate causingthe current leakage. Since the dielectric was identicalto previous technologies, which were not experiencingthe problem, it was suspected that the defect had to bepatterned on the wafer in the contact photo step andsubsequently etched through to the substrate.Inspection of wafers after the contact photo step detect-ed the stress crack in the resist as suspected. SEMimages showed that the contacts were not distorted,but lifted from the wafer intact (Figure 2).

Figure 2. SEM image of resist crack.

The sequence of events in the investigative process,from the failure analysis results to locating the defectin the resist took a relatively short period of time.Solving the problem without significantly changing acritical photo process appeared to be a much more dif-ficult task.

ADC on product wafersAfter the defect was found patterned in the photoresist,the process module was shut down until a solutioncould be found. Photo engineering evaluated all litho-cells qualified for the process to ensure that specifica-tions were being adhered to. All systems were func-tioning normally and in control. After the setup para-meters were verified, monitor wafers were processedwith individual photo process steps and film stressmeasurements were made. Although the stress mea-surements were tensile, consistent with the formationof these types of cracks, the data failed to indicate apart of the process causing the defects (Figure 3).

While these experiments were being conducted, anADC classifier based on the initial wafer inspectiondata was being developed. This rudimentary classifierwas constructed from only two wafers from one lot, butsince the defect features were unique, the accuracy andpurity were high.

ADC was used to generate results for the next designedexperiment, which focused on various modifications ofthe process. Data from the ADC bin for resist crackswas able to show that the number of cracks werereduced on each of the non-standard splits, but werenot eliminated entirely (Figure 4).

If manual review utilizing defect sampling were used,it is possible that split #5 could have given a false goodresult. Not only did ADC return information morequickly, but the data was also more accurate.

Since the first tests reduced the number of cracks butdid not eliminate them entirely, the root cause was stillto be determined. Several process splits were generated,varying the resist thickness and coat procedures. Again,ADC was used to review all the defects detected. Thistime the data showed the stress cracks to be eliminatedon all splits except the standard process. The standard

Process Stress (mPa Tensile)

Bare Si BPSG

Prime/Coat 16.4 12.9

Prime/Coat/Soft Bake 15.1 4.6

Prime/Coat/SB/PE Bake 13.5 10.2

Prime/Coat/SB/PEB/Develop 18.4 18

Prime/Coat/SB/PEB/Dev/Expose 14.3 12.3

Figure 3. Film stress data.

Summer 2000 Yield Management Solutions 29

S P E C I A L F O C U S

process used a high spin speed for an extended period oftime to accomplish both the cast (step used to get theproper thickness) and dry (step used to allow solvents toevaporate). The ADC data showed conclusively that byslowing down the dry step or by increasing the resistthickness, the defect was eliminated entirely (Figure 5).

The quickest and best solution was to leave the resistthickness unchanged and implement the changes to thedry step. Within hours, production was resumed with anADC wafer inspection implemented. After the processchange, the ADC classifier detected no additional cracks.

Inspections continued until yield data could be gatheredusing the new process. A dramatic yield improvementin the form of reduced variation confirmed the dataalready available from the ADC classifier (Figure 6).

Case 2: Problem descriptionThe second case applies to an incident of contaminatedphotoresist. A simple EPROM device has historicallybeen used as a defect monitor since it has relativelyhigh circuit density and significantly larger die thanthe majority of other microcontroller products. Yield

trends on this device had not been meeting expectedgoals. Several failure analysis attempts to identify thecause pointed to 0.5 µm to 1.0 µm Poly2 bridgingbetween adjacent memory cells, but visual and laserscattering inspections were not able to find the defect

Num

ber

of P

arts

Pas

sed

Lot Number

Resist Crack Eliminated

Split Description Wafer Cracks# Found

1 Standard Resist Thickness 7 0

with Split Cast/Dry Steps 12 0

14 0

21 0

25 0

2 Thicker Resist with 1 0

Extended Dry Step 8 0

15 11

10 0

22 0

3 Thicker Resist with 2 0

Split Cast/Dry/Step 9 0

17 0

18 0

23 0

4 Thicker Resist with 3 0

Modified Prime Step 4 0

5 0

10 0

24 0

5 Standard Process 11 6

13 3

20 3

6 Standard Process 6 3

without PEB 19 3

Split Description Wafer Cracks# Found

1 Standard Process 1 33

2 12

3 20

4 46

5 21

2 Standard Process with 18 7

Modified Prime 20 7

21 11

3 Standard Process 22 9

without ARC 23 7

24 18

25 7

4 ARC after Soft Bake 14 5

17 3

5 ARC after SB, 10 2

rinsed before PEB 13 3

6 Standard Process with 6 8

extended Prime 8 10

9 2

Figure 4. ADC results of first experiment.

Figure 5. ADC results of second experiment.

Figure 6. Parts Passed trend chart shows case 1 yield improvement.

Summer 2000 Yield Management Solutions30

in-line. A sharp downturn in yield for this device andothers relating to the same defect mechanism raised thepriority for eliminating the defect.

A KLA-Tencor 2135 inspection system was broughton-line and quickly detected the defect. Resist precipi-tates that were not being developed away were pro-truding from the resist lines causing the blocked polyetch (Figure 7).

The defect density was very high indicating that some-thing had gone wrong with the resist quality. All prod-uct lines using this resist were shut down until theproblem could be solved.

The Photo Group’s efforts to find the source of thedefect focused on several possible causes. Photoresisthandling and storage techniques were verified to be inspec. Particle tests for contaminated batch also provedto be within the manufacturing tolerances. Yield datavs process dates were analyzed showing the downturnto loosely correlate with a change in resist filter type.Since the precipitates were larger than the filter rating,and the particle counts of the resist were in spec, therehad to be more to the problem than the filter issue.

ADC on monitor wafersWhile photo engineering was investigating the resist,an ADC classifier was developed using the initial datathat detected the defects in the resist. Overall setup ofthe classifier took only a few hours and appeared very

promising. The first experiment was to put the old filtertype back on line to see if it would get the problemunder control so that production could continue.Product wafers were processed and inspected using theADC classifier to measure effectiveness. Although therewas a decrease in defect density, it was not significantenough to resume production. More tests were attemptedwith a new bottle of resist, hand dispensed resist, newresist lines, new resist pump, etc. The defect densityand defect size were reduced with each test as the resistdelivery system was purged of the contamination.Production was resumed and the inspection with ADCwas used to monitor the defectivity level.

As the precipitates became smaller, it became obviousthat background nuisance defects in the underlyingpoly silicon were causing confusion. A better solutionhad to be found to monitor for additional excursions.The product inspection was replaced with a daily pat-terned resist monitor. The use of monitor wafersbrought about new types of defects not seen on prod-uct, but since the poly silicon was not present, theaccuracy and purity of the classifier were muchimproved. Monitoring the defect level of the resistADC bin was successful in measuring additionalimprovements and monitoring for excursions.

Additional tests indicated that an interaction wasoccurring between the resist and the pumping system,causing the precipitates to form downstream of the fil-ter. Since no other resist in use was showing the prob-lem, the root cause solution was determined to be aresist change. Qualification of a new resist can take aconsiderable amount of time especially for a criticallayer like Poly2. Using the ADC classifier, a mainte-nance procedure was identified to control the defectivi-ty until a new resist could be qualified. This procedurewas incorporated in the scheduled quarterly PM andinvolved changing the pump, filter, and chemicallycleaning the delivery lines. By having a cleaned pumpready at all times, the time required to perform theprocedure did not significantly increase downtime.

As the monitor wafer procedure was fine-tuned, itbecame possible to control the defectivity by using theraw counts from the inspection. The defect mechanismproved to follow a predictable failure cycle that wascontrollable through a scheduled maintenance proce-dure. Defect images captured using the ADC systemwere still useful to verify the defect type, but the con-trol charts were changed to total counts for simplicity.

S P E C I A L F O C U S

Figure 7. Resist precipitate.

Device yield for all products using the resist increasedby a step function in response to the actions taken. Theresist monitors were changed from daily to weekly asconfidence in the maintenance procedures increased(Figure 8).

SummaryIn this paper two examples of the use of ADC to findroot-cause solutions for yield limiting defect excursionshave been presented . The first utilized ADC on prod-uct wafer splits since the defect was generated only onwafers with topography. The second example showedthat ADC’s capability can be extended beyond theinspection noise level inherent in product inspectionsby using monitor wafers. By using ADC, useful infor-mation from the wafer inspection data was generatedfaster and with improved signal to noise than if manualreview were used. This technique demonstrates thenatural extension of ADC from the production-moni-toring arena into complex engineering studies to elimi-nate defects and improve yields.

Num

ber

of P

arts

Pas

sed

Lot Number

Resist Defect Eliminated

Figure 8. Parts Passed trend chart shows case 2 yield improvement.

S P E C I A L F O C U S

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Presented at 10th Annual IEEE/SEMI Advanced Semiconductor ManufacturingConference and Workshop (ASMC), September 8-10, 1999, Boston, MA.

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