JIMS Engineering Management Technical Campus

Greater Noida, UP -201308 (Affiliated to Guru Gobind Singh Indraprastha University, New Delhi)

Subject Name : Microprocessors and Microcontrollers

Department of : ECE

Created By: Dr. Ravinder Nath Rajotiya

Subject : Microprocessors and Microcontrollers

Topic : MN/MX’ Mode 8086

List of Topics to be covered

PIN Diagram of 8086

Difference between MN/MX Mode

Minimum Mode

Maximum Mode

8086 PIN

Min and Max Mode Differences

Maximum mode Minimum Mode

When MN/MX(bar) low 8086 is in maximum

mode.

When MN/MX(bar) high 8086 is in minimum

mode.

In maximum mode 8086 generates

QS1,QS0,S0(bar),S1(bar),S2(bar),

LOCK(bar),RQ(bar)/GT1,RQ(bar)/GT0 control

signals.

In minimum mode 8086 generates INTA(bar),

ALE, DEN(bar), DT/R(bar), M/IO(bar),

HLDA,HOLD and WR(bar) control signals.

So clearly there are multiple processors in the

system.

There is only one processor in the system

minimum mode.

Whereas in maximum mode interfacing,

master/slave and multiplexing and several such

control signals are required

In minimum mode no interfacing or master/slave

signals is required.

In maximum mode a bus controller is required to

produce control signals. This bus controller

produces MEMRDC, MEMWRC, IORDC,

IOWRC, ALE, DEN, DT/R control signals.

In minimum mode direct RD / WR signals can be

used. No bus controller required. A simple

demultiplexer would do the job. of producing the

control signals. This demultiplexer produces

MEMRD, MEMWR, IORD, IOWR control signals.

Minimum Mode Signals

status signals S6 through S3

Bit S 4 and S 3 together from a 2 bit binary code that

identifies which of the 8086 internal segment registers

are used to generate the physical address that was

output on the address bus during the current bus cycle.

• Code S4 S3 = 00 identifies a register known as extra

segment register as the source of the segment address.

S4 S3 Segment

0 0 ES

0 1 SS

1 0 CS/None

1 1 DS

Minimum Mode Configuration

It is for single

processor

applications:

2-3 latched for

demultiplexing of

address/data/statu

s signal

Transceiver may

be required,

connect with DEN’

and DT/R’ for

direction control

External clock

generator IC(8284)

Minimum Mode Read Cycle Timing Diagram

Fetch/Read cycle

ALE goes high, enables the latches, demultipxes

and 20-bit Address put on address bus during T1

When M/IO’=1 and RD’=0 memory is selected for

read operation and Data put on data bus during T3

Write cycle

ALE goes high, enables the latches, demultipxes

and 20-bit Address put on address bus during T1

When M/IO’=1 and WR’=0 memory is selected for

write operation and Data from data bus is written on

the memory, this is valid for T3 and T4

Bus Request and Grant Minimum Mode

The HOLD pin is checked at leading edge of each clock

pulse. If it is received active by the processor before T4

of the previous cycle or during T1 state of the current

cycle, the CPU activates HLDA in the next clock cycle

and for succeeding bus cycles, the bus will be given to

another requesting master.

The control of the bus is not regained by the processor

until the requesting master does not drop the HOLD pin

low.

When the request is dropped by the requesting master,

the HLDA is dropped by the processor at the trailing edge

of the next clock

MAXIMUM MODE Operation

Maximum mode of operation is used for multi-processor environment. In

maximum mode a bus controller is required to produce control signals.

This bus controller produces MEMRDC, MEMWRC, IORDC, IOWRC,

ALE, DEN, DT/R control signals.

8086 Maximum Mode

Signal Name Function

RQ/GT1,0’ Bus Request Grant

Lock’ Bus Priority Lock Control

S2’ – S0’ Bus Cycle Status

QS1-QS0 Instruction Queue Status

8086 Maximum Mode

In MAX mode 8086

uses another device

8288 Bus Controller –

Bus Command and

Control Signals They

are provided through

S2,s1,s0 as: for

generating control

signals

S2’ S1’ S0’ CPU Cycle 8288 Command

0 0 0 Interrupt Ack INTA’

0 0 1 Read I/O Port IORC’

0 1 0 Write I/O Port IOWC’, AIOWC’

0 1 1 Halt None

1 0 0 Instruction fetch MRDC’

1 0 1 Read Memory MCE, PDEN’

1 1 0 Write memory MWTC’ AMWC’

1 1 1 Passive None

8086 Queue Status QS0, QS1

The four different queue status.

QS1 QS 0 Queue Status

0 0 No Operation. During the last clock cycle,

nothing was taken from the queue.

0 1 First Byte. The byte taken from the queue was

the first byte of the instruction.

1 0 Queue Empty. The queue has been reinitialized

as a result of the execution of a transfer

instruction

1 1 Subsequent Byte. The byte taken from the

queue was a subsequent byte of the instruction

8086

HOLD, HLDA interface is also changed. These two are

replaced by request/grant lines RQ/ GT0 and RQ/ GT1,

respectively.

They provide a prioritized bus access mechanism for

accessing the local bus.

• AEN and IOB are generally grounded. CEN pin is usually

tied to +5V. The significance of the MCE/PDEN output

depends upon the status of the IOB pin. • If IOB is

grounded, it acts as master cascade enable to control

cascade 8259A, else it acts as peripheral data enable used

in the multiple bus configurations.

Local Bus Control Signal – Request / Grant Signals:

Maximum Mode 8086

Thank You !!