Student Presentation Topic 5 - High-Speed Circuits...
Transcript of Student Presentation Topic 5 - High-Speed Circuits...
Student Presentation Topic 5
IEEE Transactions on Circuit and Systems (Vol. 58, No. 9, Sep. 2011) J. Kim , Rambus, Inc. Sunnyvale
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I. INTRODUCTIONII. REDUCED‐SLICER PARTIAL‐RESPONSE DECISION FEEDBACK EQUALIZER (RS‐
PRDFE)A. Equivalence Between ADC‐Based DFE and Loop‐Unrolling DFE ReceiversB. BER Model for ADC‐Based DFE Receivers
III. OPTIMIZATION OF RS‐PRDFE SLICER THRESHOLDSA. ADC Threshold Placements for Minimum BER Versus Minimum
Quantization ErrorIV. EXPERIMENTAL RESULTSV. JOINT OPTIMIZATION WITH LINEAR EQUALIZERS
A. RS‐PRDFE With Transmit FIR EqualizersB. RS‐PRDFE With Receive Linear EqualizersC. Digital Versus Analog Receive Linear Equalizers
VI. CONCLUSION
Contents
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• Scaling of CMOS fast digital logic (Tx based on ADC and DSP)
• 2010 : 10Gbps ADC‐based backplane Tx using low power
• Maximizing the performance of ADC‐based Rx
: Nonuniformly quantized ADC‐based DFE low resolution ADC is OK
• Bit error rate(BER) / quantization error
: ADC‐based DFE ≡ loop unrolling DFE (PRDFE)
• Proposing Reduced‐slicer partial‐response DFE (RS‐PRDFE)
:Optimally configured nonuniform ADC‐based DFE
• Optimizing programming algorithm
• Jointly optimizing the RS‐PRDFE Rx with various types of linear equalizers
Introduction
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ADC-based DFE ≡ loop unrolling DFE (PRDFE)
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• ADC : converting the received signal into a digital form
• DSP : DFE operation (subtracting appropriate amount of offset)
• High resolution ADC for high SNR
ADC-based DFE ≡ loop unrolling DFE (PRDFE)
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• Analog DFE Rxs
• DFE Rx : DFE operation (subtracting the offset in analog domain)
• Feedback path : 2 analog/digital conversions timing problem
• Loop‐unrolling DFE (PRDFE) : moving timing loop in to the digital domain
Number of slicers grows exponentially (2N) with the number of tap (N)
ADC-based DFE ≡ loop unrolling DFE (PRDFE)
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• ADC‐based DFE : determining whether the quantized output is greater than a
certain offset
• PRDFE : determining whether the analog input signal is above a quantization
threshold that is closest to this offset
• Possible to Optimize using same principle
Reduced-Slicer PRDFE
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• ADC‐based DFE : Digital feedback equalizer(hDFE) Look‐up table(LUT) & MUX
• PRDFE : merging slicers having similar threshold values
• Saving power & area by removing redundant or unused slicers without
degrading BER performance
BER Model for ADC-Based DFE Rx
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• Consider N‐tap DFE Rx, Intersymbol interference(ISI) spans L (>N)
• Tj: threshold of slicer (j=1,2,…2N)
• yISI : yj (possible to cancel by DFE)+ yr(out of range N<r<L)
• If Tj is close to yj : Q ↓ BER ↓
N L
Optimization of RS-PRDFE Slicer Thresholds
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• Placing M slicer thresholds for the minimum BER in set of 2N yj• Optimal grouping of ISI levels(yj) to any number of M group
• Using programming procedure, finding optimal M
• Varying strongly with channel characteristics
Minimum BER vs. Minimum Quantization Error
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• Optimal threshold placements with number of slicers
• Min BER and min Quantization error : different placements
• Reduced FSR ADC‐based DFE resembling optimal RS‐PRDFE
• 10 Gbps, 700 mVpp‐diff, 231‐1 PRBS data pattern• 25‘’‐long Nelco backplane channel • 17 dB loss at 5 GHz
Channel Characteristic
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Measurement Results
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• Rx performance ↑ with HPF, FIR filter, VGA
• Effective SBR
• Voltage margin at BER=10‐7
Measurement Results
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• SBR has 5 post cursor ISIs with very distinct values
no performance gain over PRDFE
• Prefiltering is important way to improve the performance of the RS‐PRDFE
RS-PRDFE With Transmit FIR Equalizers
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• Peak sing constraint
can’t alter the channel response too much
RS-PRDFE With Transmit FIR Equalizers
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• 4 slicers (N=4) achieving comparable signal margin with 4‐tap PRDFE Rx
RS-PRDFE With Receive Linear Equalizers
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• CTLE(continuous‐time linear equalizer), FIR equalizer
• Input : discrete‐time sampled analog input
• Ability to individually adjust the tap coefficients
RS-PRDFE With Receive Linear Equalizers
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• Effectively cancel the remaining ISI with only 4 slicers (N=4)
• Reduce 12 slicers
• Superior to 16‐slicer PRDFE Rx
Digital vs. Analog Receive Linear Equalizers
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• Analog FIR filter : large power consumption
• Implemen ng Rx FIR equalizer in digital domain : Signal Margin↓
• RS‐PRDFE & digital FIR equalizers : conflicting requirements on ADC threshold
placement
• Introducing a way of designing high‐performance with low‐resolution ADCs.
• Optimizing for the best signal margins
: quantization thresholds > quantization errors
• RS‐PRDFE receiver with only 4 slicers
: equivalent performance with uniformly quantizing ADC (N=3,4)
• Synergistic effects of combining RS‐PRDFE with Les
: especially with the receive FIR equalizers in analog domain
Conclusion
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