STRJ-WG1 February 9,2000 - 1 Proposed Roadmap Tables on SOC Design Productivity, SOC Low Power, and...

February 9,2000 - 1 STRJ-WG1

Proposed Roadmap Tables Proposed Roadmap Tables onon

SOC Design Productivity,SOC Design Productivity,SOC Low Power, andSOC Low Power, andDSM related issuesDSM related issues

STRJ-WG1March 2000


Contents(1)SOC Design Productivity

(2)SOC Low Power

(3)DSM Related Issues

Assumptions and study reaching to the table

SOC Design Productivity Table

Assumptions and study reaching to the table

SOC Low Power Table

Potential solution map

P.3 - P.9

P.10

P.11 - P.17

P.18

P.19 - p.20

An overall DSM requirements table P.21 - p.22

Assumptions and study reaching to the tablefor each DSM issue those are Crosstalk noise,RC delay, EMI, IR drop and Electro-migraton

P.23 - p.30


SOC Design ProductivitySOC Design Productivity

Premises

Technology Node, ASIC Usable Transistors, and DRAM capacity conform to ITRS99 ORTC.

Die size remains around 10mm

Application is not specified, but surely it is high-end SOC in each generation.

ProspectsLogic gate count ratio continuously decreases from 80%(1999) thru50%(2002), 35%(2005), into 15%(2011).

Contrarily, re-use circuit ratio within Logic gate count grows from 20%(1999), thru 50%(2002), 70%(2005), to be 90%(2011) .

Power supply voltage goes down from 1.5V(1999) to 0.5V(2011) .

Operation frequency goes up from 150MHz(1999) to 2000MHz(2011) .

Design 　 Productivity


SOC Design ProductivitySOC Design Productivity(cont.)(cont.)

Assumptions

Total design resource is in proportion to size of newly designedcircuit, e.g. 1Man*Year as 360Kgates.

There now exists approximately 50% design overhead for re-usecircuit, namely it costs 50% of design resource with same size newlydesigned circuit.

Contribution from both productivity improvement for Newly designedcircuit and Overhead reduction for Re-use circuit are consideredas gate size reduction for each circuit in accordance with amount ofimprovement and overhead reduction, respectively.




Productivity Requirement

Total required design resource is unchangingly kept around 10 Man*Year.

Solution to be accomplished

Both 30% improvement per every 3 years for newly designed circuitand 30% improvement per every 3 years for design overhead for re-usecircuit are needed to be accomplished.




SOC consists of Logic blocks and existing hard IP(mainly Memory)

Logic block

Existing hard IP

Each logic block can be implemented by newly designed portion and re-use portion such as IPs

Newly designed portion

Re-use portion




0

50

100

150

200

250

1999 2002 2005 2011

Logic Non-Logi c

0

5

10

15

20

25

30

35

1999 2002 2005 2011

New Re-use

MGatesMGates

Total gate countand Logic/Non-Logic ratio

Total logic gate countand Newly/Re-use ratio




How to derive “Total Design Resource” and “Target Design Resource”

Total Design Resource( M gates)

= #(Newly designed circuit) x [Productivity improvement(%)] + #(Re-use circuit) x [Overhead in Re-use circuit(%)]

Target Design Resource( Man * Year)

= (Total Design Resource) / (Normalized unit Man*Year productivity)

here, “Normalized unit Man*Year productivity” is assumed as 0.36M gates

(Ex.) in 2005Total Design Resource( M gates)= (11.64 x (1 - 0.7) ) x 0.49 + (11.64 x 0.7 ) x 0.24 = 3.67 M gates

Hence, Target Design Resource( Man * Year)

= 3.67 / 0.36 = 10.19 Man * Year




05

101520253035404550

1999 2002 2005 2011Target No-imp Case A Case B

Man*Years

No-imp : in case of No improvementCase A : in case of achieving improvement only for Newly designed circuitCase B : in case of achieving improvement only for Re-use overhead



SOC Design Productivity TableSOC Design Productivity Table

(*2) 30% off / 3 years improvement(*3) 30% off / 3 years improvement

20111999 2002 2005

Re-use circuit ratio 90%20% 50% 70%

Newly designed circuit 3.043.20 3.38 3.49

Productivity improvement 24.%100% 70% 49%

Overhead in Re-use circuit 12%50% 35% 24%

Target Design Resource 10 9.8 10.2 11.2

(*2)

(*3)

Unit

Logic gate count ratio in area 15%80% 50% 35%

Logic Gate count 30.414.00 6.75 11.64

DRAM (Production) 7,510200 525 1,230

ASIC Usable Transistors M Tr./cm2 20 54 133 811

%M gates

M bits/cm2

Embedded Memory size 2,55316 105 319.8M bits

Technology Node 50180 130 100nm

Design Resource 7.61 1.7 2.9

Power supply voltage 0.51.5 1.2 0.9V

Operation Frequency 2000150 400 1000MHz

(ratio)%

M gates

%Resource for Newly designed(A) 3.20 2.36 1.71 0.73M gates

%Resource for Re-use circuit(B) 3.290.40 1.18 2.00M gatesTotal Design resource(A+B) 4.023.60 3.54 3.67M gates

Man*Years

(*1)

(*1)

(*1) ITRS‘99 ORTC



SOC Low PowerSOC Low Power

Premises & Prospects

Technology Node, ASIC Usable Transistors, DRAM capacity, andPower Supply Voltage conform to ITRS99 ORTC.

Application is not specified, but surely it is high-end SOC in each generation.

Other premises or prospects are consistent with those of “SOC Design Productivity”, such as ;



Logic gate count ratio continuously decreases from 80%(1999) thru50%(2002), 35%(2005), into 15%(2011) .

Low 　 Power


SOC Low PowerSOC Low Power(cont.)

Assumptions

Power consumption follows a basic well-known formula, that isPower ∝ C * V * V * f .

“C” can be decomposed into “size factor” and “process factor”.Total transistor count and technology node represents “size factor”and “process factor”, respectively.

“V*V” is considered as “voltage factor”, and it is just internal voltage.Also, “f” is considered as “frequency factor”, and it is just max frequency.

“total power trend” is defined as relative amount of power consumptionfor each year(2002, 2005, and 2011) comparing each of above four“factor” for 1999 as unit(=1).

Low 　 Power



Assumptions(cont.)

“total power trend” is derived by the following calculation,

“total power trend” = “size factor” x “process factor” x ”voltage factor” x “frequency factor”

Current SOC power consumption is assumed around 3W.

For “size factor”, constant coefficient 0.85 is applied to Memoryportion, while 1.0 to Logic portion.

Low 　 Power



Low Power Target

Current power consumption(around 3W) should be kept at the minimumlevel.

A Scenario for solution to keep 3W

By virtue of a set of potential low power technology, reduction foreach “factor” in the following table is needed to be realized.

Ultimate goal is to achieve 0.5W in any technology node generation.

2002 20112005

Size factorProcess factorFrequency factorVoltage factor

50% 70% 60%

10% 20% 30%

25% 50% 60% 17% 33% 40%

Low 　 Power



How to derive “Total Power trend” and “Power estimation”

Total Power trend

Power estimation (W)

= (Total Power Trend) x 3W

(Ex.) in 2002Total Power trend= 3.93 x 0.72 x 0.64 x 2.67 = 4.84

Hence, Power estimation( W )

= 4.84 x 3 = 14.52 W

= “size factor” x “process factor” x ”voltage factor” x “frequency factor”

Low 　 Power



0.1

1

10

100

1999 2002 2005 2011

size process voltage frequency total

0.01

0.1

1

10

100

1999 2002 2005 2011

size process volatage frequency total

Total Power Trend withNo Low Power Solution

Total Power Trend withLow Power Solution Scenarioto keep 3W

Low 　 Power



0

20

40

60

80

100

120

1999 2002 2005 2011

W/ O Solution W/ Solution

W

Low 　 Power


SOC Low Power TableSOC Low Power Table

unit current 2002 2005 2011 logic tr count Mtr 16 27 46.55 121.7 memory tr count Mtr 16 105 319.8 2553.4 total tr count Mtr 32 132 366.4 2675.1size factor(logic*1.0+mem*0.85) 1 3.93 → 1.96 10.76 → 4.30 77.43 → 23.23 factor reduction % 0 50 60 70 technology node nm 180 130 100 50 process factor 1.00 0.72 → 0.65 0.56 → 0.44 0.28 → 0.19 factor reduction % 0 10 20 30 max frequency MHｚ 150 400 1000 2000 frequency factor 1.00 2.67 → 2.00 6.67 → 3.33 13.33 → 5.33 factor reduction % 0 25 50 60 internal voltage V 1.5 1.2 → 1.0 0.9 → 0.6 0.5 → 0.3 voltage factor 1 0.64 → 0.44 0.36 → 0.16 0.11 → 0.04 voltage reduction % 0 17 33 40 total power trend 1 4.84 → 1.13 14.34 → 1.02 31.87 → 0.96 estimation W 3 14.52 → 3.40 43.02 → 3.06 95.60 → 2.89 target W 0.5 0.5 0.5 0.5 Low Power Spec switching activity % 1.8 2.66 → 2.61 2.7 → 2.67 1.85 → 0.96 external voltage V 1.7 5.0～ 1.2 5.0～ 1.2 5.0～ 0.9 5.0～ battery Wh/ kg 120 130～ 140 150～ 200 250～ 400 500～

Low 　 Power


SOC Low Power DesignSOC Low Power Design

10

100

1000

10000

1 10 100 1000 10000size (M tr)

Max

freq

. (M

Hz)

1999 0.5W（）2002 0.5W（）2005 0.5W（）2011 0.5W（）

year: 1999node: 0.18




(3-5 clks)

speed

size(capacitance)

overall

Ultra-low voltagedata transfer

Data compressionon a chip

Dynamic voltagecontrol

Multi-clocking

Clock gating

Memory bankoptimization

(5-50 clks)Sytem leveloptimization

Low-poweralgorithm(HW&SW)

Asynchronus

Tr/wire sizingFloorplan optimization

Low 　 Power

- Potential Solution Map -


Low 　 Power

SOC Low Power DesignSOC Low Power Design- Potential Solution Map -

What this figure means ….

Trade-off line between operation frequency and size(Mtr) is put for eachTechnology node under the condition to accomplish 0.5W power consumption.

A set of potential low power technology is overlaid in accordance with those contribution area and degree of range.

Each potential technology is classified into three types( speed, size, and all ) with respect to main contribution.


DSM

Overall Premises & Prospects

Technology Node and Power Supply Voltage conform to ITRS99 ORTC.

Other premises or prospects are consistent with those of “SOC Design Productivity”, such as ;



DSM Related Issues

Wiring metal is assumed Al till 2002 and Cu after 2005.

Issues to be examined

For each issue, “estimated value” will be examined in contrast to “required value” at each Technology node.

Crosstalk noise, RC delay, EMI, IR Drop, and ElectroMigration


An overall DSM requirements table

See tab.2-1-4-2

See tab.2-1-4-3

See tab.2-1-4-4

See tab.2-1-4-5

See tab.2-1-4-6

DSM

unit 1999 2002 2005 2011 Reference

Technology node nm 180 130 100 50

Nominal Ion [25c,NMOS,low power] uA/um 490 490 490 490 ITRS99 Table28

Nominal Ion [25c,PMOS,low power] uA/um 230 230 230 230 ITRS99 Table28

Voltage V 1.5 1.2 0.9 0.6 STRJ-WG1/LP-SWG

Frequency MHz 150 400 1000 2000 STRJ-WG1/LP-SWG

Die size cm□ 1 1 1 1 STRJ-WG1/LP-SWG

Metal height/width aspect 2 2.1 1.7 2.1 STRJ -WG4

Metal effective resistivity μ Ω -cm 2.2 2.2 2.2 <1.8 STRJ -WG4

Maximum metal current mA 2.16 1.56 1.2 0.6 STRJ -WG4

Crosstalk noise Required

Required parallel interconnect maximum allowable lengthwhich considers parastic capacitence effect

mm 1.08 0.78 0.60 0.30

EstimatedEstimated parallel interconnect maximum allowable lengthwhich considers parastic capacitence effect

mm 2.70 0.21 0.00 0.00RC delay Required

Required interconnect maximum allowable length whichconsiders resistence

mm 10 10 10 10

EstimatedEstimated interconnect maximum allowable length whichconsiders resistence

mm 289 67 12 2Inductance

Interconnect Inductance Effect CP1 (*1) CP2 (*2)EMI Allowed

Allowable EMI by FCCclassB (at a distance of 3.0m ) uV/m 150 200 500 500

EstimatedEstimated EMI by a chip (observation point =3.0m) uV/m 11 22 43 43

IR drop Required

Required maximum allowable number of FF which isdriven by power line without failure due to IR Drop. 20 20 20 20

EstimatedEstimated maximum allowable number of FF which isdriven by power line without failure due to IR Drop. 34 21 10 5

Number of Power Pads (High Performance) 342 472 800 1,066

Number of Power Pads (Battery/Hand-Held) 6 9 16 16

Number of Power Pads (Target of LP-SWG) 2 2 3 4

Man

ufa

ctu

re OPE Optical Proximity Correction CP CP

CP1(1st Crisis Point): Interconnect effects becomes critical in high speed blocks(1GHz).

CP2(2nd Crisis Point): Interconnect effects becomes major delay in high speed blocks(2GHz).

Ba

se

da

ta/C

on

dit

ion

ElectroMigration

(table 2-1-4-1) DSM requirements S

ign

al I

nte

gri

tyR

elia

bili

ty

DSM Category

(*a) Next Page

(*b) Next Page

(*c) Next Page

(*d) Next Page


DSM

An overall DSM requirements table--- A supplementary explanation ---

(*a) Derived from 3000 x ( wiring pitch ), and wiring pitch is assumed as 2X ofTechnology node. Namely, 1.08 mm is coming from 180nm x 2 x 3000. At least 3000 wiring pitch parallel interconnect is required.

(*b) 10mm interconnect length is directly coming from that Die size remains 10mm Obviously, the longest interconnect probably reaches to 10mm under theabove assumption.

(*c) Source of these values is FCC classB standard( at a distance of 3.0m).

(*d) Because estimated number of FFs in 2002 is 21, around 20 should beconsidered as required number of FFs at each Technology node era.


Crosstalk NoiseCrosstalk Noise

unit 1999 2002 2005 2011 Reference

Technology node nm 180 130 100 50Voltage V 1.5 1.2 0.9 0.6 STRJ -WG1/ LP-SWG

Frequency MHz 150 400 1000 2000 STRJ -WG1/ LP-SWG

Die size cm□ 1 1 1 1 STRJ - WG4

Metal height/ width aspect 2 2.1 1.7 2.1 STRJ - WG4

Interlevel metal insulator effective dielectric constant k 2.5 3.0～ 2.0 2.5～ <1.5 STRJ - WG4

Maximum parallel lengthMetal effective resistivity μ Ω - cm 2.2 2.2 2.2 1.8 STRJ - WG4

Nominal Metal width nm 360 260 200 100 STRJ - WG4

Metal Thickness nm 720 546 340 210 STRJ -WG1/ DSM-SWG

Resistance / Metal length Ω / mm 85 155 324 857 STRJ -WG1/ DSM-SWG

Lumped Capacitance / Metal length fF/ mm 51 30 28 22 *1

Coupled Capacitance / Metal length fF/ mm 58 42 45 40 *1

Output resistance in aggressor Ω 1000 1300 1400 1450 STRJ -WG1/ DSM-SWG *2

Output resistance in victim Ω 300 390 420 435 STRJ -WG1/ DSM-SWG *2

Maximum parallel length mm 2.70 0.21 -0.33 -0.26 STRJ -WG1/ DSM-SWG *3

*1 The values are from Table2 in Challenges and Opportunities for Design Innovations in Nanometer Technologies J . Cong UCLA『』*2 The values are calculated on the model assuming that drivability of a victim net is 3 times as large as that of an aggressor net.*3 Maximum parallel length is calculated from eqation (3).

(table 2-1-4-2) Parallel maximum length

DSM


DSM

Reference [1] describes the following simplified model of coupled wires.

| | === Ci,a | _ Rout,a Rline,a/ 2 | Rline,a/ 2 aggressor - - ( | )- - - VVVVVV- - - - - - - - VVVVVV- - - - - - +- - - - - - - VVVVVV- - - - - - - - - - - - - - ~ | | === Cc | | Rout,v Rline,v/ 2 | Rline,v/ 2 victim - - - - - - - - - - - - VVVVVV- - - - - - - - VVVVVV- - - - - - +- - - - - - - VVVVVV- - - - - - - - - - - - - - | | === Ci,v | |

Rout,a : Output resistance of a driver in an aggressor net Rout,v : output resistance of a driver in a victim net Ci,a : Intrinsic capacitance of a line in an aggressor net Ci,v : Intrinsic capacitance of a line in a victim net Cc : Coupling capacitance between two lines Rline,a: Longitudinal resistance of a line in an aggressor net Rline,v: Longitudinal resistance of a line in a victim net

According to reference [1],[2], the peak noise voltage of the above model is shown below.

Vdd Vnoise = - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - (1) Rout,a * Ci,a Ci,v - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - - - - - (Rout,v + Rline,v / 2) * Cc Cc

To derive an upper limit of geometrical adjacent lengh not to exceed allowable peak noise Vdd/ 3, the model is further simplified as follows.

Vnoise = Vdd/ 3 Ci,a = Ci,v = L * c Cc = L * cc Rline,a = Rline,v = L * r

L : Geometrical adjacent length (victim and aggressor running in parallel) c : Intrinsic line capacitance per unit length cc: Coupling capacitance per unit length r : Longitudinal line resisitance per unit length R : Output resistance

The above terms are substituted for equation (1).

Vdd Vdd - - - - - - = - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - (2) 3 Rout,a * L * c L * c - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - - - - - - - (Rout,v + L * r / 2) * L * cc L * cc

An upper limit of geometrical adjacent length is calculated according to equation (2).

6 * Rout,v * cc - 2 * Rout,v * c - 2 * Rout,a * c L = - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - (3) r * c - 3 * r * cc

[1] "Analysis, Reduction and Avoidance of Crosstalk on VLSI Chips", IBM International Symposium on Physical Design, 1998 [2] A.Vittal, M.Marek- Sadowska, University of California, Santa Barbara, "Reducing Coupled Noise During Routing", Proceedings, Fifth ACM SIGDA Phisical Design Workshop, 1996, pp.27- 33

Reference [1] describes the following simplified model of coupled wires.

| | === Ci,a | _ Rout,a Rline,a/ 2 | Rline,a/ 2 aggressor - - ( | )- - - VVVVVV- - - - - - - - VVVVVV- - - - - - +- - - - - - - VVVVVV- - - - - - - - - - - - - - ~ | | === Cc | | Rout,v Rline,v/ 2 | Rline,v/ 2 victim - - - - - - - - - - - - VVVVVV- - - - - - - - VVVVVV- - - - - - +- - - - - - - VVVVVV- - - - - - - - - - - - - - | | === Ci,v | |

Rout,a : Output resistance of a driver in an aggressor net Rout,v : output resistance of a driver in a victim net Ci,a : Intrinsic capacitance of a line in an aggressor net Ci,v : Intrinsic capacitance of a line in a victim net Cc : Coupling capacitance between two lines Rline,a: Longitudinal resistance of a line in an aggressor net Rline,v: Longitudinal resistance of a line in a victim net

According to reference [1],[2], the peak noise voltage of the above model is shown below.

Vdd Vnoise = - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - (1) Rout,a * Ci,a Ci,v - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - - - - - (Rout,v + Rline,v / 2) * Cc Cc

To derive an upper limit of geometrical adjacent lengh not to exceed allowable peak noise Vdd/ 3, the model is further simplified as follows.

Vnoise = Vdd/ 3 Ci,a = Ci,v = L * c Cc = L * cc Rline,a = Rline,v = L * r

L : Geometrical adjacent length (victim and aggressor running in parallel) c : Intrinsic line capacitance per unit length cc: Coupling capacitance per unit length r : Longitudinal line resisitance per unit length R : Output resistance

The above terms are substituted for equation (1).

Vdd Vdd - - - - - - = - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - (2) 3 Rout,a * L * c L * c - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + - - - - - - - (Rout,v + L * r / 2) * L * cc L * cc

An upper limit of geometrical adjacent length is calculated according to equation (2).

6 * Rout,v * cc - 2 * Rout,v * c - 2 * Rout,a * c L = - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - (3) r * c - 3 * r * cc

[1] "Analysis, Reduction and Avoidance of Crosstalk on VLSI Chips", IBM International Symposium on Physical Design, 1998 [2] A.Vittal, M.Marek- Sadowska, University of California, Santa Barbara, "Reducing Coupled Noise During Routing", Proceedings, Fifth ACM SIGDA Phisical Design Workshop, 1996, pp.27- 33

- How the the maximal parallel length is calculated -


Interconnect DelayInterconnect Delay

unit 1999 2002 2005 2011 ID Equation ReferenceTechnology node nm 180 130 100 50 A

Frequency MHz 150 400 1000 2000 B STRJ - WG1/ LP- SWG

Metal height/ width aspect 2 2.1 1.7 2.1 C STRJ - WG4

Maximum wire length

Cycle Time ps 6667 2500 1000 500 E = 1 / B

Allowable Time for RC delay ps 3333 1250 500 250 F = E x 0.5 STRJ - WG1/ DSM- SWG(*1)Metal effective resistivity μ Ω -cm 2.2 2.2 2.2 1.8 G STRJ - WG4Nominal Metal Width nm 360 260 200 100 H = A x 2

Metal Thickness nm 720 546 340 210 I = H x C

Resistance / Metal len g t hΩ / mm 84.88 154.97 323.53 857.14 J = G / H / I

Plate Capacitance per area fF/ um2 0.10 0.08 0.06 0.04 K STRJ - WG1/ DSM- SWG(*2)Fringe Capacitance per length fF/ um 0.10 0.10 0.12 0.15 L STRJ - WG1/ DSM- SWG(*3)

Plate Capacitance / Metal length fF/ um 36.00 20.80 12.00 4.00 M = K x H

FringeCapacitance / Metal length fF/ um 100.00 100.00 120.00 150.00 N = L

Total Capacitance / Metal length fF/ um 136.00 120.80 132.00 154.00 O = M + N

RC delay / Metal length ps/ mm 11.54 18.72 42.71 132.00 P = J x O

Interconnect maximum allowable length wh i c hconsiders resistence

mm 288.770 66.771 11.708 1.894 Q = F / P

(*1) Allowable RC delay is defined as the half time of cycle time(*2) Plate Capacitance per area are derived by the trend of process technology(*3) Fringe Capacitance per area are derived by the trend of process technology

(table 2-1-4-3) Maximum length

DSM


Electro Magnetic InterferenceElectro Magnetic Interference

unit 1999 2002 2005 2011Technology node nm 180 130 100 50Size in gate count Mgate s5 20 100 1000 Logic gate count ratio % 80 50 30 10 Logic gate count Mgates 4 10 30 100Total Transistor count Mtrs 25 100 500 5000Voltage V 1.5 1.2 0.9 0.6Frequency MHz 150 400 1000 2000Die size cm□ 1 1 1 1Metal height/ width aspect 2 2.1 1.7 2.1Maximum metal current mA 2.16 1.56 1.2 0.6Metal effective resistivity μ Ω -cm 2.2 2.2 2.2 <1.8Interlevel metal insulator effective dielectric k 2.5 3.0～ 2.0 2.5～ <1.5

EMI

Allowable EMI by FCC classB (at a distance of 3.0m )uV/ m 150.0 200.0 500.0 500.0

Estimated EMI by a chip (at a distance of 3.0m ) uV/ m 11.4 22.1 43.3 42.8

(table 2-1-4-4) EMI

DSM


IR DropIR Drop

unit 1999 2002 2005 2011 ID Equation ReferenceTechnology node nm 180 130 100 50 ANominal Ion [25c,NMOS,low power] uA/ um 490 490 490 490 B ITRS99 Table28Nominal Ion [25c,PMOS,low power] uA/ um 230 230 230 230 C ITRS99 Table28Voltage V 1.5 1.2 0.9 0.6 E STRJ - WG1/ LP- SWG

Metal height/ width aspect 2 2.1 1.7 2.1 F STRJ - WG4

Maximum number of F/ FsMetal effective resistivity μ Ω - cm 2.2 2.2 2.2 1.8 G STRJ - WG4Nominal Metal Width nm 360 260 200 100 H = A x 2Metal Thickness nm 720 546 340 210 I = H x FAverage Power Wire Length for each Trs mm 2.0 2.0 2.0 2.0 J STRJ - WG1/ DSM- SWG

Nominal Power Metal Width um 1.8 1.3 1.0 0.5 K = A x 10 STRJ - WG1/ DSM- SWG

Resistance / Power Metal Length Ω / mm 17.0 31.0 64.7 171.4 L = G / I / KAverage Power Wire resistance per Trs Ω 34.0 62.0 129.4 342.9 M = J x LTypical Gate Width of Tr um 1.800 1.300 1.000 0.500 N = A * 10 STRJ - WG1/ DSM- SWG

Average Current Consumption per Tr (m A )mA 0.648 0.468 0.360 0.180 O = (B+C)/ 2*NAverage IR Drop per Trs mV 22.0 29.0 46.6 61.7 P = M x OActivation ratio % 5 5 5 5 Q STRJ - WG1/ DSM- SWG

Effective IR Drop perTtrs mV 1.1 1.5 2.3 3.1 R =P*QMaximum allowable IR drop ratio % 10.0 10.0 10.0 10.0 S STRJ - WG1/ DSM- SWG

Maximum allowable IR Drop mV 150 120 90 60 T = E x SMaximum number of trs on each power line 136 83 39 19 U = T / RAverage number of clock Trs in a FF 4 4 4 4 VMaximum allowable number of FF which is driven by powerline without failure due to IR Drop

34 21 10 5 W = U / V

(table 2-1-4-5) IR drop

DSM


DSM

IR DropIR Drop

Assumed Conditions in table 2-1-4-5

H : Nominal Metal width is assumed as 2X of Technology node.

J : Average power wire length from a pad to Trs. is assumed as 2mm.

K : Nominal power wire width is assumed as 10X of Technology node.

N : Typical gate width(W) is assumed as 10X of Technology node.

Q : Overall average activation ratio is assumed as 5%.

S : Maximum allowable IR drop ratio is defined as 10% of power supply voltage.

V : Average number of clock Trs. driven by one FF is assumed as 4.


Electro MigrationElectro Migration

unit 1999 2002 2005 2011 ID Reference / Equation

Technology Node nm 180 130 100 50 A Metal Material Al Al Cu Cu STRJ - WG1/ DSM- SWG Me ta l Thickness/ Width Aspect 2.0 2.1 1.7 2.1 B STRJ - WG4 J ma xA/ cm2 5.8E+05 9.6E+05 1.4E+06 3.7E+06 C STRJ - WG4 Wire Width from Pads to Core um 70.0 70.0 70.0 70.0 D

Power W 90 130 160 174 E ITRS99 (Maximum Power, High- performance) Power Supply Voltage V 1.8 1.5 1.2 0.6 F ITRS99 (Minimum logic VDD - maximum) Chip Power Current A 50.0 86.7 133.3 290.0 G = E/ F Nominal Meta l Width nm 360 260 200 100 H = A*2 Metal Thickness nm 720 546 340 210 I = B*H Number of Power Pads 342 472 800 1,066 J = D/ (C*D*I), (Number of pads for VDD and GND)

Power W 1.4 2.0 2.4 2.2 E ITRS99 (Maximum Power, Battery) Power Supply Voltage V 1.5 1.2 0.9 0.5 F ITRS99 (Minimum logic VDD - minimum) Chip Power Current A 0.9 1.7 2.7 4.4 G = E/ F Nomina l Meta l Width nm 360 260 200 100 H = A*2 Metal Thickness nm 720 546 340 210 I = B*H Number of Power Pads 6 9 16 16 J = D/ (C*D*I), (Number of pads for VDD and GND)

Power W 0.5 0.5 0.5 0.5 H STRJ - WG1/ LP- SWG (Target) Power Supply Voltage V 1.5 1.2 0.9 0.5 F ITRS99 (Minimum logic VDD - minimum) Chip Power Current A 0.3 0.4 0.6 1.0 G = E/ F Nomina l Meta l Width nm 360 260 200 100 H = A*2 Metal Thickness nm 720 546 340 210 I = B*H Number of Power Pads 2 2 3 4 J = D/ (C*D*I), (Number of pads for VDD and GND)

(*) To show the relative difficulty of electro migration problem, we estimated the number of pads needed for power supply at each technology node.

(Table 2-1-4-6) Electro Migration

High Performance

Batte r y

Target of LP-SWG

DSM

STRJ-WG1 February 9,2000 - 1 Proposed Roadmap Tables on SOC Design Productivity, SOC Low Power, and...

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