STICK DIAGRAM EMT251. Schematic vs Layout In Out V DD GND Inverter circuit.
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Transcript of STICK DIAGRAM EMT251. Schematic vs Layout In Out V DD GND Inverter circuit.
![Page 1: STICK DIAGRAM EMT251. Schematic vs Layout In Out V DD GND Inverter circuit.](https://reader036.fdocuments.net/reader036/viewer/2022062517/56649f395503460f94c556e9/html5/thumbnails/1.jpg)
STICK DIAGRAM
EMT251
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Schematic vs Layout
OutIn
VDD
M2
M1
InOut
VDD
GND
Inverter circuit
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Schematic vs Layout
A
Out
VDD
GND
B
2-input NAND gate
B
VDD
A
![Page 4: STICK DIAGRAM EMT251. Schematic vs Layout In Out V DD GND Inverter circuit.](https://reader036.fdocuments.net/reader036/viewer/2022062517/56649f395503460f94c556e9/html5/thumbnails/4.jpg)
Stick Diagram
A stick diagram is a graphical view of a layout.
Does show all components/vias (except possibly tub ties), relative placement.
Does not show exact placement, transistor sizes, wire lengths, wire widths, tub boundaries.
![Page 5: STICK DIAGRAM EMT251. Schematic vs Layout In Out V DD GND Inverter circuit.](https://reader036.fdocuments.net/reader036/viewer/2022062517/56649f395503460f94c556e9/html5/thumbnails/5.jpg)
Stick Diagram Represents relative positions of transistors Stick diagrams help plan layout quickly
Need not be to scaleDraw with color pencils or dry-erase markers
In
Out
VDD
GND
Inverter
A
Out
VDD
GNDB
NAND2
![Page 6: STICK DIAGRAM EMT251. Schematic vs Layout In Out V DD GND Inverter circuit.](https://reader036.fdocuments.net/reader036/viewer/2022062517/56649f395503460f94c556e9/html5/thumbnails/6.jpg)
Stick Diagram
Metal (BLUE)
Polysilicion (RED )
N-Diffusion (Green)
P-Diffusion (Brown)
Contact / Via
Layers
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How to design?
C
A B
X = C • (A + B)
B
AC
i
j
j
VDDX
X
i
GND
AB
C
PUN
PDNABC
Logic Graph / Euler Path
![Page 8: STICK DIAGRAM EMT251. Schematic vs Layout In Out V DD GND Inverter circuit.](https://reader036.fdocuments.net/reader036/viewer/2022062517/56649f395503460f94c556e9/html5/thumbnails/8.jpg)
Stick Diagram of C • (A + B)
X
CA B A B C
X
VDD
GND
VDD
GND
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Consistent Euler Path
j
VDDX
X
i
GND
AB
C
A B C
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Example
C
A B
X = (A+B)•(C+D)
B
A
D
VDDX
X
GND
AB
C
PUN
PDN
C
D
D
ABCD
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LAYOUT DESIGN RULES
EMT251
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3D View
![Page 13: STICK DIAGRAM EMT251. Schematic vs Layout In Out V DD GND Inverter circuit.](https://reader036.fdocuments.net/reader036/viewer/2022062517/56649f395503460f94c556e9/html5/thumbnails/13.jpg)
Design Rules
Interface between designer and process engineer
Guidelines for constructing process masks Unit dimension: Minimum line width
scalable design rules: lambda parameter
absolute dimensions (micron rules)
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CMOS Process Layers
Layer
Polysilicon
Metal1
Metal2
Contact To Poly
Contact To Diffusion
Via
Well (p,n)
Active Area (n+,p+)
Color Representation
Yellow
Green
Red
Blue
Magenta
Black
Black
Black
Select (p+,n+) Green
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Draw NMOS:1. Active + Poly2. Contact_to_active3. Metal1 above Contact4. N-Plus Select5. P-Well6. P-Well Contact
Draw PMOS:1. Active + Poly2. Contact_to_active3. Metal1 above Contact4. P-Plus Select5. N-Well6. N-Well Contact
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Layers in 0.35 m CMOS process
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Intra-Layer Design Rules
Metal24
3
10
90
Well
Active3
3
Polysilicon
2
2
Different PotentialSame Potential
Metal13
3
2
Contactor Via
Select
2
or6
2Hole
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Transistor Layout
1
2
5
3
Tra
nsis
tor
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Vias and Contacts
1
2
1
Via
Metal toPoly ContactMetal to
Active Contact
1
2
5
4
3 2
2
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Select Layer
1
3 3
2
2
2
WellSubstrate
Select3
5
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CMOS Inverter Layout
In
Out
GND VDD
(a) Layout