Stavelet Status Report
description
Transcript of Stavelet Status Report
Stavelet Status Report
30.09.2010Peter W Phillips
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The Stavelet
Hybrid 0 1 2 3 4 5 6 7
BCC 62 61 60 59 58 57 56 55
MUX 7 6 5 4 3 2 1 0
DEMUX 14/15 12/13 10/11 8/9 6/7 4/5 2/3 0/1
Coupling DC AC AC DC AC DC AC DC
Module 0 1 2 4
s/n 1 9 3 4
Stavelet Numerology
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Stavelet IV Data at 22C
Detector Bias (V)
Leak
age
Curr
ent (
mic
roA)
All consistent with HPK data
0 50 100 150 200 2500
2
4
6
8
10
12
14
16
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M0 FZ2 (sn 1)M1 FZ1 (sn 9)M2 FZ2 (sn 3)M3 FZ2 (sn 4)
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Operating Information• Stavelet cooling
– Pipes specified for CO2 but running with water for now
– Water at 12.5C gives typically 45C on hybrids
• Stavelet has many power options– So far using Serial Power with
“M” shunt and PPB protection– Other options to be tested later
(Spi, DC-DC, ...)
• Low Voltage from either– Commercial TTi PSU– Jan Stastny’s Current Source
• High Voltage from– SCTHV (VME version)
• One Wire controller– Commercial DS8490R unit
• Readout with HSIO– Stavelet is main testbed for
development activity– Firmware by Matt Warren with
contributions from Alexander Law and Bruce Gallop
– Software by Peter and Bruce– AC coupled LVDS, MLVDS signals– BCC V2, 80 MHz dclk
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Checking the Basics
Measure Vdd
Probe BCO
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Hybrid Voltages vs CurrentI H0 H1 H2 H3 H4 H5 H6 H7
3.52.29 2.3 2.3 2.31
3.62.31 2.35 2.36 2.36
3.72.39 2.4 2.4 2.42
3.82.43 2.44 2.45 2.46
3.92.476 2.485 2.495 2.496
4.02.499 2.496 2.504 2.498 2.495 2.504 2.501 2.496
4.02.499 2.496 2.504 2.498 2.495 2.504 2.501 2.496
5.02.499 2.496 2.504 2.498 2.495 2.504 2.501 2.496
A V V V V V V V V3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2
2.15
2.2
2.25
2.3
2.35
2.4
2.45
2.5
2.55
Hybrid 0Hybrid 1Hybrid 2Hybrid 3Hybrid 4Hybrid 5Hybrid 6Hybrid 7
V (V)
I (A)
The ABCN-25 “M” shunt and the hybrid’s control circuitry work as expected:Constant hybrid voltage from 4.0A
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Duty Cycle of Recovered BCO
Hybrid 0 Hybrid 7
Hybrid 0 1 2 3 4 5 6 7
Duty 55.1 53.8 53.3 53.1 53.4 52.6 52.4 51.8 %
Output of MLVDS driver on End of Stave Card has 51.5% duty cycle
Preliminary termination resistors: 56R end term, 100R back term
Further optimisation could improve this, but already a good place to start
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Thermal images of The Stavelet in Operation
All hybrids on
Slow control disablesodd hybrids
Slow control disableseven hybrids
22.7V5.09A
12.7V5.09A
Each hybrid may be bypassed using the PPB 1-wire operated shuntVoltage differences consistent with 2.5V per hybrid
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Stavelet ENC @2fC, JS CS II@5AAfter Trimming, reading all hybrids simultaneously, column 1 strip order corrected.
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Stavelet ENC @2fC, JS CS II@5AAfter Trimming, even hybrids bypassed, column 1 strip order corrected.
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Hybrid Column TTi 5.0A ENC@1fC
TTi 5.0A ENC@2fC
CS 5.0A ENC@1fC
CS 5.0A ENC@2fC
CS 5.0A ENC@2fC
CS 4.5A ENC@2fC
0 0 660 675 663 679 - 6780 1 611 620 611 623 - 6211 0 639 645 633 642 628 6381 1 673 684 671 683 672 6762 0 633 650 640 658 - 6552 1 609 620 614 625 - 6233 0 623 626 621 631 631 6253 1 653 662 651 665 678 658
4 0 651 665 660 669 - 6674 1 621 629 628 636 - 6315 0 683 684 691 694 677 674
5 1 707 711 715 721 703 6986 0 672 673 688 685 - 6896 1 645 647 661 659 - 6667 0 690 693 700 702 683 6827 1 724 717 739 733 711 706
p15 p16 p17 p9 p10
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Preliminary Stavelet NO, JS CS II@5AAfter Trimming.
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Summary• The first stavelet has been successfully built
– Sensors not damaged during assembly
• HSIO Firmware and software developed to the point at which the stavelet may be read out– Using BCC V2, 80 MHz DCLK
• Preliminary results are very encouraging– SP with shunt “M” and PPB protection working– AC coupled LVDS (data) and MLVDS (clk, com) working– Noise approximately correct
• Work in progress to define a full list of tests to be made– To include other power options
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Backup Slides
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Stavelet ENC @1fC, TTi Supply @ 5AAfter Trimming, reading all hybrids simultaneously, column 1 strip order corrected.
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Stavelet ENC @2fC, TTi Supply @ 5AAfter Trimming, reading all hybrids simultaneously, column 1 strip order corrected.
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Stavelet ENC @1, JS CS II@5AAfter Trimming, reading all hybrids simultaneously, column 1 strip order corrected.