StaticRoute: A novel router for the dynamic partial

reconfiguration of FPGAsBrahim Al Farisi,

Karel Bruneel, Dirk Stroobandt2/9/2013

Dynamic partial reconfiguration (DPR)

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• Advantages:• Smaller area• Lower power usage

M1 M2 M3

• Goal: area reduction with reduced reconfiguration time

M1M2M3

• Disadvantage:• Reconfiguration

time

Conventional DPR tool flow

• Different circuits are implemented independently

• Complete area is rewritten

Problem: long reconfiguration times

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Static vs dynamic bits

After implementation:– Each memory cell corresponds to a collection of bit values – This collection of bit values is called • a static bit, when the values are the same for all circuits• a dynamic bit, otherwise

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Clustering of dynamic bits

• Only memory cells that contain a dynamic bit need to be rewritten during run-time

• Configuration memory of an FPGA is frame-based• Dynamic bits are scattered over the frames• Approach in this work:– Divide configuration frames into dynamic and static ones– Cluster dynamic bits into the dynamic frames

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CLBs vs routing

• In our experiments:– 10% of the configuration memory consists of CLB bits– 90% of the configuration memory consists of routing bits

Most of the time spent in reconfiguring the routing infrastructure

• Focus on reducing reconfiguration time of routing– All CLB frames are dynamic– Routing frames are divided in static and dynamic ones– Novel router, called StaticRoute, that clusters dynamic routing

bits in the dynamic routing frames

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Proposed DPR tool flow

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PathFinder

• Makes use of a routing resource graph (RRG): directed graph where nodes represent wires and edges represent routing switches

• For each net PathFinder finds a minimum cost tree in the RRG• In a first iteration nets are allowed to share resources, i.e. wire

congestion is allowed• Negotiated congestion• Cost function of a node in the RRG:

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StaticRoute

• Extended Pathfinder algorithm that also clusters dynamic routing bits into dynamic routing frames

• Makes use of an extended routing resource graph (eRRG): – switches are also represented by nodes– mark switches as static/dynamic– keep information about the switches during routing

• Detecting dynamic bits– After routing: easy– During routing: not obvious

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Detecting dynamic bits

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Novel cost function StaticRoute

• Switch congestion: when a static switch is controlled by a dynamic bit

• StaticRoute iterates until both wire and switch congestion are resolved

• Novel cost function:

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Experiments

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• Regular expression matching, adaptive filtering, general MCNC and MCNC20 benchmarks

• 200-1500 LBs• Considered only 2 circuits at a time• Comparison of conventional DPR and new

flow that uses StaticRoute• Metrics:• Reconfiguration time• Wire length (of each circuit separately)

Results – Reconfiguration time

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Results – Reconfiguration time

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Decrease in total reconfiguration time rel. to conventional DPR

Relative portion of static switch blocks

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Results – Wire length

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Conclusions

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• Possible to detect dynamic bits during routing• Introduced notion of switch congestion• Novel router, called StaticRoute, that resolves both

wire and switch congestion• Using novel DPR tool flow that uses StaticRoute:• Total reconfiguration speed-up of approx. 2X• Increase in wire length is limited

StaticRoute: A novel router for the dynamic partial reconfiguration of

Brahim Al Farisi, Karel Bruneel, Dirk Stroobandt

2/9/2013