static and dynamic principle - TU/estatic and dynamic principle static principle: output determined...

static and dynamic principlestatic and dynamic principle

static principle:

output determined by a connectionwith “strong” node

pmosnetwork

nmosnetwork

vout

dynamic principle:

output (sometimes) determined

Cspassnetwork

charging

evaluation

output (sometimes) determined by a “weak” (floating) node

charging:

Cs is being charged up to V+ - level

evaluation:

Cs is being discharged whenthere is a conducting path to mass

controlwithlevels

realisation of dynamic logicrealisation of dynamic logic

P

N Cs

φφφφ

prechargeswitch

N

P

Cs

φφφφ P

N Cs

φφφφ

prechargeswitch

P

passnetwork

CsN

P

Cs

φφφφ

"precharge"switch

Cspassnetwork

controlwithlevels

passnetwork

evaluationswitch

toggle switchbecomes selector

Cspassnetwork

controlwithlevels

passnetwork

passnetwork

evaluationswitch

Nφφφφ

network

interchange network and evaluation switch

passnetwork

evaluationswitch

P

passnetwork

Cs

"precharge"switch

"precharge"switch

passnetwork

Cs

φφφφ low: Cs is being charged up toV+ - level ("precharge")

cmos-realisation of dynamic logiccmos-realisation of dynamic logic

Cs is being dischargedhigh:when the nmos network has a conducting path;

φφφφ

else: vout shifts slowlytowards an intermediate

vuit

Nφφφφ

network

evaluationswitch

φφφφ

network

evaluationswitch

towards an intermediatelevel

V

tprecharge evaluation

φφφφ

vout

TD

evaluationevaluation speedspeed

2

3

4

5

TD

NOR(S) NOR(S)

NAND(S)

NAND(S)

NAND(S)

NAND(D)

fanout : 1 inverterpmos : 7.25/1.75nmos : 4.00/1.75ground switch : 10.5/1.75

1

# inputs1 2 3 4 5

NOR(S)

φφφφNOR(D)

NOR(D)

NAND(S)

φφφφ

NAND(D)

evaluation speed of dynamic logic is faster, but what about precharge

“hiding” precharge time“hiding” precharge time

slave latches

combinatoriallogic

slavetransparant

slaveclock TS

prechargep-eclock TP

master latches

logic

mastertransparant

masterclock TM

dynamic logic:

(((( )))) (((( ))))(((( )))) TmaxT,TmaxT DGATE

pathDPSM ∑∑∑∑++++++++(((( ))))(((( )))) TmaxTT SGATE

pathbSM ∑∑∑∑++++++++

static logic:

the cascade problemthe cascade problem

vout

a

b

d

solutions:

1. "dummy" imitates theslowest gate ("self timing")

φφφφ'

φφφφ φφφφ'

c

φφφφ' must come suffuciently later than φφφφ

otherwise spurious discharge occurs(als a=b=c=d=1)

φφφφ'

φφφφ

no-race logic (nora)no-race logic (nora)

vout

a

b

d

solutions:


φφφφ'

2. alternate nmos and pmos

floatingnode

floating

• more complicated logic synthesis

φφφφ φφφφ'

cφφφφ'

φφφφ

floatingnode

• noise sensitivity because of possibly large floating nodes

• an extra clock line -> area• more pmos network (and therefore slower)• dead time for "skew" protection (more delay, unless . . . . )

domino logicdomino logic

vout

a

b

d

solutions:


φφφφ'


floatingnode

floating

3. invert the output

• only unate logic possible

φφφφ φφφφ'

cφφφφ'

φφφφ

floatingnode

vout

• less noise sensitivity because – output from strong logic– concentrated floating node– effect only when sense node changes >> Vt

sense node

domino logicdomino logicsolutions:


φφφφ'


floatingnode

floating

3. invert the output

• only unate logic possible

precharge:

"sense node" is being chargedvsense � V+ ; vout � 0 V;nmos transistors in fanout� do not conduct!

evaluation:

if "sense node" is being chargedvsense � 0 V ; vout � V+; φφφφ'

φφφφ

floatingnode

voutsense node

vsense � 0 V ; vout � V+;transistors in fanout will openelse vout stays low;nmos transistors in fanoutstill do not conduct

• less noise sensitivity because – output from strong logic– concentrated floating node– effect only when sense node changes >> Vt

charge sharing in domino logiccharge sharing in domino logic

Vout

C1

Cs

Vs

LLH

LH

vi

ti

:ttt i0 <<<<<<<< ++++==== Vsv

++++==== VsCtotQ

(((( )))) sv2C1CsvsCtotQ ++++++++==== :itt >>>>>>>>

when tis vvv −−−−<<<<

: t ∞∞∞∞→→→→ 2C1CsC

VsCsv

++++++++

++++→→→→ 1

V

2C1C ++++++++

++++ ====

C2L

L Hφφφφ

V+

t0 ti t

φφφφ

vi

vsvs

2C1CsCs ++++++++ 1sC

2C1C ++++++++

Vv IHs ≥≥≥≥ V

VV

C

CC

IH

IH

s

21 −−−−<<<<

++++→→→→ ++++

charge sharing in domino logiccharge sharing in domino logic

Vout

C1

Cs

Vs

LLH

LH

vi

ti

reduce charge sharing by:

• enlarging Cs• precharging internal nodes• bleeders

bleeder

bleeder

C2L

L Hφφφφ

small, becauseof ratio effect

bleeder

nmosnetwork

small, forminga skewed latch :design!

nmosnetwork

all measuresdelay evaluation!

complementary network pairs in nmos

a cascode switch is a network between two decision nodes and a strong nodewith the property that always exactly one decision nodeis electrically connected with the strong node.

d

D2

a d

D1

e

D D

example:pull-down cascode switch(strong node is low).

"pull-down cascode switchesconsists of two complementary networks (n-type switches),but now with the complementary signals controlled.

e b c c

b

a

D2 D1

cascode-switch

differential cascode-switches

D2 D1

cascodeswitch

D1D2

cascode-switch

D2 D1

cascodeswitch

φφφφ φφφφ

various pull-up possibilities for pull-down cascode switches

latchedweak

(pseudo-nmos)

switchswitch

precharged

if low, than D1 and D2 high!

φφφφ

switch

φφφφ

if high, than either D1 or D2 low!

φφφφ

attention: low levels strong,but high levels are weak!

differential cascode switchdifferential cascode switch

d

Q

a d

Q

e

Q Q

cascodeswitch

here tooa complementary network!

but now: - both nmost- complementary

signals needed

more wires, better testability

e b c c

b

a

switch

from table to decision diagramfrom table to decision diagram

00

10

1

00 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 1

a b c d

representations of logic functions

•minterms or maxterms•truth table•sum of products

or product of sums•factored expressions• .........•tree structures

01

1

0

10

1

0

10

1

0 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

•tree structures

c

c

b


00

10

1

00 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 1

a b c d

d

d

d

0

10

10

1

0

1

0

0

1 0




c

c

c

b

01

1

0

10

1

0

10

1

0 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

d

d

d

d

d

a

10

10

10

10

10

1

1

0

1

0

1

0

1

1 0

1

-- each path from the rootto a leaf is a minterm

-- function value “in” leaf

•tree structures

c

c

b


00

10

1

0 d

d

d

0

10

10

1

0

1

0

0

1 0




c

c

c

b

01

1

0

10

1

0

10

1d

d

d

d

d

a

10

10

10

10

10

1

1

0

1

0

1

0

1

1 0

1

•tree structures

-- each path from the rootto a leaf is a minterm

-- function value “in” leaf

d

d

d00

10

1

c

c

b


0 0

10

10

1

0

1

0

0

1 0variable dhas in the

eliminate variables with two identical sub trees !

d

d

d10

1

0

10

1

c

c

c

b

01

1

0 d

d

a

10

10

10

10

10

1

1

0

1

0

1

0

1

1 0

1

has in the green sub treesno impact:“does not discriminate"

0

1

c

c

b


0 0

1

0

0

1 0


variable dis in the

1

0

1

c

c

c

b

01

1

0 d

d

a

0

10

1

1

0

1

0

1

0

1

1 0

1

is in the green sub treeseliminated !

b

c

c0

1


0 0

1

0

0

1 0


variabele bhas in the green sub tree no impact :“does not discriminate"

variable dis in the

1

0c

c

1

c

b

01

1

0 d

d

a

0

10

1

1

0

1

0

1

0

1

1 0

1

is in the green sub treeseliminated !

c

1

0


0

1

variable bis in the green sub tree eliminated


1

0c

c

b

01

1

0 d

d

a

0

10

1

0

1

0

1

0

1

0

1

c

1

0


0

1

identify identical sub trees !

the two greensub trees are (inclusive labels)

eliminate variables with two identical sub trees ! 1.

2.

c

1

0

c

b

01

1

0 d

d

a

0

10

1

0

1

0

1

0

1

0

1

sub trees are (inclusive labels)identical !




2.

the two greensub trees are(inclusive labels)

c

1

0

c

b

01

1

0 d

d

a

0

10

1

0

1

0

1

0

1

0

1

sub trees are(inclusive labels)identified !




2.

the diagram is no longer a “tree" !("dag" : directed acyclic graph )

c01

1

0 d

d

c

1

0

b

a

0

10

1

0

1

0

1

0

1

0

1

variable chas in the green sub treeno impact:“does not discriminate"




2.


10 d

c

1

0

b

a

0

1

0

10

1

0

1

variable cis in the green sub treeeliminated !




2.


3. identify the 0- and 1-leafs !

1

0

10 d

c

b

a

0

1

0

10

1

0

1




2.


3. identify the 0- and 1-leafs !

0

1 d

c

b

a

0

1

0

1 0

1

0

1

after identificationof leafsthe diagram hasonly two leafsleft !

from decision diagram to pass networkfrom decision diagram to pass network

0 c a

0

0

10

0

10

x

replace

x

1 d b

1 1

1

x

x

by

a realisation is obtained by replacing every node by a 2-selector (or a pair of complementary switches)

from decision diagram to pass networkfrom decision diagram to pass network

a

b

c

d

0

ab

c

d

1

static and dynamic principle - TU/estatic and dynamic principle static principle: output determined...

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Transcript of static and dynamic principle - TU/estatic and dynamic principle static principle: output determined...