SRAM Mohammad Sharifkhani. Effect of Mismatch.
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Transcript of SRAM Mohammad Sharifkhani. Effect of Mismatch.
![Page 1: SRAM Mohammad Sharifkhani. Effect of Mismatch.](https://reader038.fdocuments.net/reader038/viewer/2022102907/56649d355503460f94a0bb3f/html5/thumbnails/1.jpg)
SRAM
Mohammad Sharifkhani
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Effect of Mismatch
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Data Retention Voltage
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DRV Mote-carlo simulation
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Inv. with VL Input @ Read load
Inv. with VR Input @ Write load
Init cond. VL=1, VH=0
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Shmoo plot
• A shmoo plot is a graph that represents how a particular test passes or fails when parameters like frequency, voltage, or temperature are varied and the test is executed repeatedly.
• The shape of the failing region is meaningful and helps in determining the cause of the failure.
• A shmoo plot of normal circuit operation shows better high-frequency performance as supply voltage increases, as shown in Fig. 1a.
• Other shapes frequently seen include the curlback (Fig. 1b), ceiling (Fig. 1c), floor (Fig. 1d), wall (Fig. 1e), finger (Fig. 1f), and breaking wave (Fig. 1g).
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Techniques for improving reliability
• Read assist circuits
• Write assist circuits
• Error correction methods
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Multiple voltages for NM improvement
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Threshold voltage variation
S. Mukhopadhyay, JSSC 2007
Monte-carlo simulationAccess (reductionin the BL-differential produced), Higher Vt lower BL swing
Read (data flipping while reading), lower v-trip
write (unsuccessful write) Higher Vt weaker PU ration
hold (data flipping at a lower supply voltage in standby mode)
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Solution: Adaptive body bias
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Dynamic VDD Selection
Higher write noise margin more power
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Read Write-assist circuitsKeeps WL voltage in check (lower for stable read)
Charge redistribution between cell VDD and down Vdd
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Pulsed WL and BL
Minimization of WL activation
Threats write:Read Modify Write is used for all columns
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Pulsed WL and BL
On pseudo read columns the BLs are precharged to a lower voltage than VDD to maintain stability of the cell Weaker access lower delta V to trip the cell
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Dynamic Body Bias
Forward BB: stronger PMOS makes a wider butter fly curve more SNM during read operationHigher leakage (only applied on selected banks)
On-chip programmable voltage generator with N-well resistors
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Read assist
Pilo, JSSC’07 Divided BLs
Local SA
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Read assist
When enabled the half selected BL/read BL get full swing
Masks the BL of the half selected columns that do not need full amplification to save power
10% more power at nominal voltageYet allows for 1.20.9 VDD reduction and keeps the array stable saves power at the endMask registers are
loaded during power up
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Write assistWeaker PMOS is needed
Supply reduction of the to be written cells by ~200mV
Only the columns to be written on get the lower supply voltage: a power decoder is needed
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Reference generator
Write voltageBi-directional/data dependent current flow
Old data: VDDVWR
New data: sink data from VWR to charge up the new 1 node
Writing old data pulls up VWR push-pull is needed at Ref. Generator
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Redundancy in SRAMs
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Redundancy
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Error Correction Code
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Multi-bit errors
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Multi-bit errors: Interleaving
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Future trends
• More than 6T cells
• Change in technology
• eDRAM
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More transistors
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Thin Body MOSFETs
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Double Gate FinFET
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Double Gate vs. Tri-Gate
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Independent Gate operation
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Applications
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Independent Gate Operation6-T SRAM in Bulk-Si
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6T SRAM with FinFET
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6T SRAM with 2 FinFET
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Embedded DRAM