Sprinkler Buddy

Kalyan Kommineni | Panchalam Ramanujan | Sasidhar Uppuluri Kartik Murthy | Devesh Nema | Design Manager: Bowei Gai

“Low Cost Irrigation Management For Everyone !”

Presentation Outline

• Marketing • Project Description • Behavior/Algorithmic Description • Design Process • Floor Plan Evolution • Layout • Verification• Issues Encountered • Specifications • Conclusions

1.1 Billion potential customers

$52 Million market potential

100% yearly market growth

5 month payback to customer

Sprinkler Buddy at-a-glance

Large and Untapped Market

• 95% of the 1.1 billion farmers are from developing nations

• 60% of irrigation water wastage in these nations

Drip Irrigation

The South Asian Farmer• Earns $795.56 annually

• Purchases 4 months of water to supplement 4 months of rain water

• Wastes 25 % of yearly earnings in water costs

Sprinkler Buddy: The low cost, automated solution !

Includes:

The Sprinkler Buddy Advantage

Simple ease of use

Low Power Design

Exhaustive Metrics

Low Cost Solution

Rain Bird

Gorman-Rupp Jain Sprinklers

Sprinkler Buddy

Minimal Setup

Solar Powered Design

UN Certified Water Output Calculations

Low Cost Alternative

UN Specified Water Equation

Water Output = KC*ETo

Look-up from table based on type/stage of crop(P)*(.46*Tmean+8)

Mean Daily % of Daylight Hours

(TmaxAvg+TminAvg) /2

Innovative Key Features• Quiet Bit-line SRAM• Semi-Clocked Control Architecture

– Broken into five distinct modes

• Power Shut Off– Almost 60% is off during the day

Behavioral Description

Hourly Update

Daily Update

Computation

Feedback

Temperature from Sensor

Current TMax and TMin

Current TMax Avg and TMin Avg

Water Output

Month

Crop Type

Water At Plant

Water Tank Level

Valve Enable

Error Signal

Daily Clock

HourlyClock

FP AdderReset

(HU & DU & C)

FSM Start(HU & DU)

Standby

Main FSM(Init and PSO)

Hourly Update

Daily Update

Computation

Feedback

Main FSM

Hourly Update Mode

20:10 Mux

FP Subtractor

Add Sign

Temp Register

Temperature from Sensor

TMax Register TMin Register

-> Stores Max and Min Temperatures for each day

Daily Update Mode

50:20 Mux

FP Add/Sub

TMax Sum Register TMin Sum Register

20:10 Mux

sramInput

TMax SRAM

5 BitCounter

cROMsel

Old Value Max Register Old Value Min Register

TMin SRAM

20:10 Mux

15:5 MuxConstant ROMFP Multiplier

Tmax Avg RegisterTMin Avg Register

HU TMax HU TMin

[9:0][19:10]10:5 Mux

PG SRAM en

10:5 Mux

5 BitCounter

PG State

cROMsel

index index

inputinput

outout

2:1 Mux

ch max

count (max) count (min) 11111

-> Saves temperatures for past 32 days and updates averages

Computation Mode5 Bit Add/Sub 5 Bit Add/Sub

TMax Avg Exp

TMin Avg Exp

TMax Avg (w/o Exp)

TMin Avg (w/o Exp)

FP Multiplier

Water Output Register

FP Adder

40:20 Mux

8

[19:10] [9:0]

KC ROM

P ROM

60:20 Mux

.46

Month

Crop Type

[19:10] [9:0]

-> Computes final water output using UN FAO Equation

Feedback Mode

40:20 Mux

FP Subtractor

Valve Enable Register Error Signal Register

Adder Output Register

WaterOutput

Water AtPlant

Water AtTank

[19:10] [9:0]

Add Sign(Add Sign)’

Valve Enable Error Signal

-> Enables valve until UN approved water amount has been supplied -> Outputs an error signal in case of water shortage

Main FSM-> Initializes SRAM and manages Power Shutoff

Initialize SRAM

Standby

Power Up Hourly Update

Reset HU FP Adder

Hourly Update On

Power Up Daily Update and Computation

Reset Daily Update and Computation FP Adders

Daily Update and Computation On

Hourly Clock Signal Daily Clock Signal

Hourly Update Done Daily Update and Computation Done

Design Process Overview• Emphasized low power design

– Re-use of components

• Focused on compact layout

• Used 10 bit floating point format

• Employed Semi-Clocked Design with handoff between modes

Design Process – Verilog/Floor Plan

• Verilog:– All changes were first verified in Verilog then

translated into schematic.

• Floor plan– Created a detailed floor plan early on to avoid

later routing issues– Early Floor plan iterations were completed

before schematics

Design Process – Schematic

• Selected topologies and logic styles of components based on low power requirements

• Shutoff power to unused components to cut down on leakage current

• Sized buffers for optimal rise and fall times• Removed glitches to avoid layout issues

Design Process – Layout• Focused on maximum density to reduce

parasitics

• Simulated all intermediate layouts to isolate problems

• Used wider interconnects for long paths and supply rails

Floor Plan Progression

Layout - FPUs

FP Adder

FP Multiplier

Layout - FSMs

FP Add FSMDaily FSM Feed Back FSM

ComputationFSM

Power FSM

Layout – Other Interesting Things

Sense Amp Flip FlopsIs Zero Unit

Register EnablesSRAM I/O and Sense-Amp

Layout – Whole Chip

Layout – Whole Chip

Verification Methodology

• Verilog Functionality– “C” vs. Verilog

• Schematic Checks– Schematic vs. Verilog

• Layout Verification• Mode outputs • FSM signals

• Power Gating

VDD Rise Verification

VDD Fall Verification

Final Output Verification

Issues Encountered

• Determination of distribution of work between FPUs

• Routing of control signals

• Ground gating was not feasible

• Metal directionality problems

• FSM design issues

Sprinkler Buddy Specification

• Area– 362um x 361 um – 1:1.0001 Aspect Ratio– .129 mm2 area

• Density – .232 transistors / um2

• I/O– 43 Inputs– 2 Outputs

• Power– Off State Power 2.4 mW– With Standby 1.12 mW

Sprinkler Buddy

• Affordable, comprehensive, seamless

• Low risk, high gain

• Automated and low cost

• Vast potential

Create System Prototype

Beta Testing Period

VC Investment

International Entry

End of 2007

Mid 2008

End of 2008

Mid

2009

Company Expansion

Where do we go now ?

Sprinkler Buddy Goes Global

IndiaSouth Asia

Asia

World