Spring 2010Spring 2010 - MIT OpenCourseWare · s1 s2 use x s4 3 4 . Saman Amarasinghe & Armando...
Transcript of Spring 2010Spring 2010 - MIT OpenCourseWare · s1 s2 use x s4 3 4 . Saman Amarasinghe & Armando...
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Spring 2010Spring 2010
Register Allocation
Courtesy of Saman Amarasinghe and Armando Solar-Lezama. Used with permission.
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Outline • What is register allocation • Webs • Interference Graphs • Graph coloring • Spilling
S litti • Splitting • More optimizations
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Storing values between def and useg• Program computes with values
– value definitions (where computed)value definitions (where computed) – value uses (where read to compute new values)
• Values must be stored between def and use – First Option
• store each value in register at definition • retrieve value from register at each use
t h l i t d fi iti• store each value in memory at definition • retrieve from memory at each use
– Second Optionp
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performance – Affects almost every statement of the program
• Limited mem-to-mem ALU ops, may need two instructions – Probably is the optimization with the most impact!
Register Allocationg• Deciding which values to store in limited
b f i tnumber of registers
• Register allocation has a direct impact onRegister allocation has a direct impact on
– Eliminates expensive memory instructions – # of instructions goes down due to direct
manipulation of registersmanipulation of registers
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What can be put in a register?p g • Values stored in compiler-generated temps
• Language-level values
–
– Values stored in local scalar variables – Big constants
Values stored in array elements and object fields Values stored in array elements and object fields
• Issue: alias analysis
• Register set depends on the data-type – floating-point values in floating point registers – integer and pointer values in integer registers
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Issues • Fewer instructions when using registers
– Additional instructions when using memory accesses
• Registers are faster than memory wider gap in faster newer processors wider gap in faster, newer processors
– Factor of about 4 bandwidth, factor of about 3 latency
–
– Could be bigger if program characteristics were different
• But only a small number of registers available
Usually 16 integer and 16 floating point registers Usually 16 integer and 16 floating-point registers – Some of those registers have fixed users (ex: RSP, RBP)
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Outline 15
• What is register allocation • Key ideas in register allocation • Webs • Interference Graphs • Graph coloring
S litti• Splitting • More optimizations
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Summary of Register Allocationy g • You want to put each temporary in a register
– But, you don’t have enough registers.
• Key Ideas: 1 When a temporary goes dead its register can be reused 1. When a temporary goes dead, its register can be reused
2. Two live temporaries can’t use the same register at the same time
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Summary of Register Allocationy g • When a temporary goes dead, its register can be reused •• Example:Example:
a := c + d
e := a + b
f := e - 11f := e (assume that a and e die after use)
• temporaries a, e and f can go in the same register
1 + d
r1 := c + d
r1 := r1 + b
r1:= r1 – 1
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Summary of Register Allocationy g • Two live temporaries can’t use the same register at the
same timesame time
• Example 2: a := c + d a := c + d
e := a + b
f := e - a
• ttemporariies e andd a can nott go iin th the same regiistter
r1 := c + d
r2 := r1 + b
r1 := r2 r1r1 := r2 – r1
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When things don’t work out • Sometimes more live variables than registers
g
a := c + d e := c + b f := e – c
+ f
Won’t work for 2 registers g := e + f
h := a + g
(assume only g and h live at the end)
g
• You can split a live range by storing to memory a := c + d store a e := c + b f := e – c g := e + f load a h := a + g
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Web-Based Register Allocationg• Determine live ranges for each value (web) • Determine overlapping ranges (interference) • Compute the benefit of keeping each web in a
register (spill cost)register (spill cost) • Decide which webs get a register (allocation) • Split webs if needed (spilling and splitting) • Split webs if needed (spilling and splitting) • Assign hard registers to webs (assignment) • Generate code including spills (code gen) • Generate code including spills (code gen)
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Outline 25
• What is register allocation • Key ideas in register allocation • Webs • Interference Graphs • Graph coloring
S litti• Splitting • More optimizations
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–
web – Def and all reachable uses must be in same web
Webs • Starting Point: def-use chains (DU chains)
Connects definition to all reachable usesConnects definition to all reachable uses
• Conditions for putting defs and uses into sameConditions for putting defs and uses into same
– All defs that reach same use must be in same web
• Use a union-find algorithm
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Exampple
def yy
def x def x def x use y
def x def y
use x def x
use x use y
use x
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use x
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Exampple
def yy
def x def x def x use y
def x def y
use x def x
use x use y
use x
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use x
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Examplep
def yy
def x def x def x use y
def x def y
use x def x
use x use y
use x
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use x
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Examplep
def yy
def x def x def x use y
def x def y
use x def x
use x use y
use x
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use x
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Examplep
def yy
def x def x def x use y
def x def y
use x def x
use x use y
use x
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use x
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Examplep
def yy
def x def x def x use y
def x def y
use x def x
use x use y
use x
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use x
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Examplep
def yy
def x def x def x use y
def x def y
use x def x
use x use y
use x
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use x
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Examplep
def y s1y
def x def x 2 def x use y
def x def y
s2
use x def x
use x use y
s3
use x
s4
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use x
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Webs • Web is unit of register allocation
• If web allocated to a given register R – All definitions computed into R – All uses read from R
• If web allocated to a memory location M All d fi iti t d i t M– All definitions computed into M
– All uses read from M
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31
Outline • What is register allocation • Webs • Interference Graphs • Graph coloring • Splitting • MMore opti timiizati tions
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S a d C s o a o to es
Convex Sets and Live Rangesg• Concept of convex set
• A set S is convex if – A, B in S and C is on a path from A to B implies, pat p – C is in S
• Concept of live range of a web – Minimal convex set of instructions that includes all defs
and uses in web – Intuitively, region in which web’s value is live
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Interference • Two webs interfere if their live ranges overlap
(have a nonemtpy intersection)
• If two webs interfere, values must be stored in different registers or memory locations
• If two webs do not interfere, can store values in same register or memory locationsame register or memory location
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Examplep
def y s1y
def x def x 2 def x use y
def x def y
s2
use x def x
use x use y
s3
use x
s4
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use x
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Examplep
def y s1y
def x 2def x def x use y
s2def x def y
use x def x
s3 use x use y
use x
s4
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use x
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Examplep
def y s1 Webs s1 and s2 interfere Webs s2 and s3 interfere y
def x 2def x def x use y
s2def x def y
use x def x
s3 use x use y
use x
s4
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use x
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Interference Graphp• Representation of webs and their interference
– Nodes are the webs – An edge exists between two nodes if they interfere
s1 s2
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s3 s4
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Examplep
def y s1y
def x 2def x def x use y
s2def x def y
use x def x
s3 use x use y
s1 s2
use x
s4
3 4
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use x s3 s4
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Examplep
def y s1 Webs s1 and s2 interfere Webs s2 and s3 interfere y
def x 2def x def x use y
s2def x def y
use x def x
s3 use x use y
s1 s2
use x
s4
3 4
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use x s3 s4
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a
Outline 37
• Overview of procedure optimizations • What is register allocation • A simple register allocator • Webs • Interference Graphs • GGraphh colloriing • Splitting
More optimi tions• More optimizations
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Register Allocation Using
Graph Coloring
–
Graph Coloring
• Each web is allocated a register
each node gets a register (color)
• If two webs interfere they cannot use the same
register register – if two nodes have an edge between them, they cannot
have the same color
s1 s2
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s3 s4
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Graph Coloringp g • Assign a color to each node in graph
• Two nodes connected to same edge must have different colors
Cl i bl i h h• Classic problem in graph theory
• NP lNP complette – But good heuristics exist for register allocation
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Graph Coloring Examplep g p
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Graph Coloring Examplep g p
• 1 Color
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Graph Coloring Examplep g p
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Graph Coloring Examplep g p
• 2 Colors
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Graph Coloring Examplep g p
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Graph Coloring Examplep g p
• Still 2 Colors
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Graph Coloring Examplep g p
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Graph Coloring Examplep g p
• 3 Colors
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Heuristics for Register Coloringg g • Coloring a graph with N colors • If degree < N (degree of a node = # of edges)
– Node can always be colored – After coloring the rest of the nodes, you’ll have at least
one color left to color the current node • IfIf d degree >>= NN
– still may be colorable with N colors
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Heuristics for Register Coloringg g • Remove nodes that have degree < N
– push the removed nodes onto a stack • When all the nodes have degree >= N
– Find a node to spill (no color for that node) – Remove that node
–
• When empty, start to color – pop a node from stack back
AAssiign it a collor th that i t is different f t from itit s connectteddit diff nodes (since degree < N, a color should exist)
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Coloring Exampleg p N = 3
s1 s2
s0
s3 s4
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Coloring Exampleg p N = 3
s1 s2
s0
s3 s4
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Coloring Exampleg p N = 3
s1 s2
s0
4 s3 s4
s4
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Coloring Exampleg p N = 3
s1 s2
s0
4 s2
s3 s4 s4
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Coloring Exampleg p N = 3
s1 s2
s0
4 s2 s1
s3 s4 s4
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Coloring Exampleg p N = 3
s1 s2
s0
4 s2 s1 s3
s3 s4 s4
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Coloring Exampleg p N = 3
s1 s2
s0
4 s2 s1 s3
s3 s4 s4
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Coloring Exampleg p N = 3
s1 s2
s0
4 s2 s1 s3
s3 s4 s4
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Coloring Exampleg p N = 3
s1 s2
s0
4 s2 s1
s3 s4 s4
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Coloring Exampleg p N = 3
s1 s2
s0
4 s2 s1
s3 s4 s4
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Coloring Exampleg p N = 3
s1 s2
s0
4 s2
s3 s4 s4
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Coloring Exampleg p N = 3
s1 s2
s0
4 s2
s3 s4 s4
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Coloring Exampleg p N = 3
s1 s2
s0
4 s3 s4
s4
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Coloring Exampleg p N = 3
s1 s2
s0
4 s3 s4
s4
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Coloring Exampleg p N = 3
s1 s2
s0
s3 s4
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Coloring Exampleg p N = 3
s1 s2
s0
s3 s4
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Another Coloring Exampleg p N = 3
s1 s2
s0
s3 s4
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Another Coloring Exampleg p N = 3
s1 s2
s0
4 s3 s4
s4
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Another Coloring Exampleg p N = 3
s1 s2
s0
4 s3 s4
s4
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Another Coloring Exampleg p N = 3
s1 s2
s0
4 s3
s3 s4 s4
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Another Coloring Exampleg p N = 3
s1 s2
s0
4 s3 s2
s3 s4 s4
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Another Coloring Exampleg p N = 3
s1 s2
s0
4 s3 s2
s3 s4 s4
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Another Coloring Exampleg p N = 3
s1 s2
s0
4 s3 s2
s3 s4 s4
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Another Coloring Exampleg p N = 3
s1 s2
s0
4 s3
s3 s4 s4
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Another Coloring Exampleg p N = 3
s1 s2
s0
4 s3
s3 s4 s4
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Another Coloring Exampleg p N = 3
s1 s2
s0
4 s3 s4
s4
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Another Coloring Exampleg p N = 3
s1 s2
s0
4 s3 s4
s4
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Another Coloring Exampleg p N = 3
s1 s2
s0
s3 s4
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Another Coloring Exampleg p N = 3
s1 s2
s0
s3 s4
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What Now? • Option 1
– Pick a web and allocate value in memory – All defs go to memory, all uses come from memory
• Option 2 – Split the web into multiple webs
• In either case, will retry the coloring
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Which web to pick?p• One with interference degree >= N • One with minimal spill cost (cost of placing value
in memory rather than in register) • What is spill cost?
– Cost of extra load and store instructions
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–
Solution: Use a static approximation – profiling can give instruction execution frequencies – or use heuristics based on structure of control flow
Ideal and Useful Spill Costsp• Ideal spill cost - dynamic cost of extra load and
store instructions. Can’t expect to compute this. – Don’t know which way branches resolve
D ’ k h i l– Don’t know how many times loops execute – Actual cost may be different for different executions
Solution: Use a static approximation •
or use heuristics based on structure of control flow graph
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t t t t
One Way to Compute Spill Costy p p • Goal: give priority to values used in loops • So assume loops execute 10 or 100 times
–
• Spill cost = – sum over all def sites of cost of a store instruction
times 10 to the loop nesting depth power, plus ll it f f l d i i isum over all use sites of cost of a load instruction times
10 to the loop nesting depth power •• Choose the web with the lowest spill cost Choose the web with the lowest spill cost
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With 1 R i t Whi h
Spill Cost Examplep p
Spill Cost For x def x def y
Spill Cost For x storeCost+loadCost
use y Spill Cost For y
9*storeCost+9*loadCost y def y
9 storeCost+9 loadCost
use x use y
With 1 Register, Which Variable Gets Spilled?
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use y
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a
Outline 47
• Overview of procedure optimizations • What is register allocation • A simple register allocator • Webs • Interference Graphs • GGraphh colloriing • Splitting
More optimi tions• More optimizations
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6.035
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Splitting Rather Than Spilling
–
p g p g • Split the web
Split a web into multiple webs so that there will be less interference in the interference graph making it N-colorable
– Spill the value to memory and load it back at the points where the web is split
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Splitting Examplep g p def z
x y z
use z
def xdef x def y use x use x use y
use z
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Splitting Examplep g p def z
x y z
use z
def xdef x def y use x x y use x use y
z
use z
z
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Splitting Examplep g p def z
x y z
use z
def xdef x def y use x x y use x use y
z
use z
z
2 colorable?
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Splitting Examplep g p def z
x y z
use z
def xdef x def y use x x y use x use y
z
use z
z
2 colorable? NO!
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NO!
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Splitting Examplep g p def z
x y z
use z
def xdef x def y use x use x use y
use z
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Splitting Examplep g p def z
x y z
use z
def xdef x def y use x use x use y
use z
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Splitting Examplep g p def z
x y z
use z
def x z1
def x def y use x x y use x use y
z2
use z
z2
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Splitting Examplep g p def z
x y z
use z
def x z1
def x def y use x x y use x use y
z2
use z
z2
2 colorable?
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Splitting Examplep g p def z
x y z
use z
def x z1
def x def y use x x y use x use y
z2
use z
z2
2 colorable? YES!
Saman Amarasinghe & Armando Solar-Lezama 90 6.035 ©MIT
YES!
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Splitting Examplep g p def z
x y z
use z
def x
r1 r2
1
z1 def x def y use x
r1
x y use x use y
r1 z2
use z r1 z2
2 colorable? YES!
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YES!
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Splitting Examplep g p def z use z str z
x y z
str z
def x
r1 r2
1
z1 def x def y use x
r1
x y use x use y
r1 z2
ld z use z
r1 z2
2 colorable? YES!
Saman Amarasinghe & Armando Solar-Lezama 92 6.035 ©MIT
YES!
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Splitting Heuristicp g • Identify a program point where the graph is not R-
colorable (point where # of webs > N) – Pick a web that is not used for the largest enclosing
block around that point of the program
Redo the interference graph
block around that point of the program – Split that web at the corresponding edge – Redo the interference graph– Try to re-color the graph
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Cost and benefit of splitting
–
Estimate by its loop nesting
p g • Cost of splitting a node
Proportion to number of times splitted edge has to be crossed dynamically
– Estimate by its loop nesting• Benefit
– Increase colorability of the nodes the splitted web
interferes with
– Can approximate by its degree in the interference graph
•• Greedy heuristic Greedy heuristic – pick the live-range with the highest benefit-to-cost ration to
spill
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a
Outline 52
• Overview of procedure optimizations • What is register allocation • A simple register allocator • Webs • Interference Graphs • GGraphh colloriing • Splitting
More optimi tions• More optimizations
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Further Optimizationsp• Register coalescing • Register targeting (pre-coloring) • Presplitting of websg• Interprocedural register allocation
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Register Coalescingg g • Find register copy instructions sj = si
• If sj and si do not interfere, combine their webs
similar to copy propagation• Pros
– similar to copy propagation– reduce the number of instructions
–
• Cons – may increase the degree of the combined node
a colorable graph may become non-colorable
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Register Targeting (pre-coloring)g g g (p g) • Some variables need to be in special registers at
a given time – fist 6 arguments to a function – return vallue
• Pre color those webs and bind them to the right Pre-color those webs and bind them to the right register
• Will eliminate unnecessary copy instructions
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–
Pre-splitting of the websp g • Some live ranges have very large “dead” regions.
– Large region where the variable is unused
• Break up the live ranges Break-up the live ranges – need to pay a small cost in spilling
but the graph will be very easy to colorbut the graph will be very easy to color
• Can find strateggic locations to break-upp – at a call site (need to spill anyway) – around a large loop nest (reserve registers for values
used in the loop))
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Interprocedural register allocationallocation
• saving registers across procedure boundaries is expensive – especially for programs with many small functions
• Calling convention is too general and inefficient
• Customize calling convention per function by
doing interprocedural register allocation doing interprocedural register allocation
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–
Summaryy • Register Allocation
– Store values in registers between def and use – Can improve performance substantially
–• Key concepts
W b Webs – Interference graphs
Colorability Colorability – Splitting
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6.035 Computer Language Engineering Spring 2010
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