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RT Box

DEMO MODEL

SPI interface loop-back demo on a single RT Box

Last updated in RT Box Target Support Package 2.1.1

SPI interface loop-back demo on a single RT Box

1 Overview

The Serial Peripheral Interface (SPI) is a synchronous serial communication interface specificationused for short-distance communication, primarily with peripheral devices. SPI devices communicatein full duplex mode using a master-slave architecture between a single master and multiple slaves.

The SPI Master block from the RT Box Target Support Library implements SPI communication viadigital outputs/inputs. There are 2 SPI modules available on the RT Box. Each SPI module can outputdata on up to 4 paralleled data channels (using a common clock and chip select signal).

This demo model shows:

• a simple loop-back scenario that wires the SPI module digital output channel with the digital inputchannel,

• how to configure the parameters inside the SPI Master block,• both synchronous and asynchronous SPI transmission with regards to the RT Box model step size.

One additional model shows the use case of the RT Box as SPI Master connected to an external ADCdevice as the SPI slave.

1.1 Requirements

• One PLECS RT Box and one PLECS Coder license. For the RT Box 1 the minimum hardware revi-sion is 1.2.

• The RT Box Target Support Library (minimum version 2.1.1)• Follow the step-by-step instructions on configuring PLECS and the RT Box in the Quick Start guide

of the RT Box User Manual.• One wire to connect the digital output channel 2 and digital input channel 2 on the front panel of

the RT Box.

2 Model

This demo model uses the SPI Master data output and data input on the same SPI module inside thesame subsystem. With the wiring between the SPI Master data output and input channel, a loop-backof the SPI data is formed.

The circuit schematic is shown in Fig. 1. A Sine wave and a Pulse wave are packed into two 16-bitwords and transmitted out from the SPI Master data output channel. Through the loop-back wire, itis received at the SPI Master data input channel, and then displayed in the Scope in Fig. 1 for com-parison.

SPIMaster

v

SPIMaster

SineWave

PulseGenerator

TX/RXOverview

PWMOut

PWMOut0.5

TX RX

TX

RXSinePulse

Figure 1: Subsystem circuit schematic for SPI loop-back demo

Additionally, a PWM Out block generates a PWM signal with 0.5 duty cycle synchronized with the RTBox model step size by configuring its Synchronization with model step option as Enabled. ThisPWM signal can be used as a reference to observe the different behaviors of SPI transmission withinsingle or multiple RT Box model steps.

Fig. 2 shows the mask content of the SPI Master block. For the fields not mentioned in the followingexplanation, please refer to the Help page of the SPI Master block.

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SPI interface loop-back demo on a single RT Box

SPI Master Setup tab

Figure 2: Mask content of the SPI Master block

• SPI module: there are 2 SPI modules integrated into the RT Box for choosing, either SPI1 or SPI2.• The Delay first clock after CS active and Hold CS active after last clock pulse fields are used

in case of special timing needed between the clock signal and CS (chip select) signal. In this demothe default value of 1 (tick) is used in each field.

• The Delay CS after simulation step is useful to adjust the beginning of SPI data transmissionwith regards to the RT Box simulation step. In this demo, Minimum is used by default.

• Mode [CPOL, CPHA]: Note that the same SPI mode has to be configured between the SPI Masterand an external SPI Slave device to ensure correct data interpretation.

• Skew-matched clock input can be enabled when the signal transmission delay from the masteroutput to its input exceeds half an SPI clock period. When enabled, the corresponding Digital in-put channel for skew-matched SPI clock under Input tab has to be specified to receive the in-coming clock, otherwise this field is greyed out.

• Number of parallel data channels: Note that the dimension of the Digital input channel(s)for SPI data and Digital output channel(s) for SPI data under Input and Output tabs has tomatch the number chosen here. In this demo only 1 data channel is used.

• Words per transmission: In this demo, one word is used for the Sine wave and the other word isused for the Pulse wave.

• Sample time: Putting 0 here means that the SPI transmission happens within every single model

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SPI interface loop-back demo on a single RT Box

step. The SPI transmission can also be extended over multiple model steps by putting a numberhere which is an integer multiple of the model step size. In the following section, it showcases bothscenarios. Besides, putting -1 means to inherit the sample time of the Atomic Subsystem or Taskframe that this SPI Master block resides in.

SPI Master Input and Output Tabs

Since each SPI module can only output one SPI clock signal and one CS signal, the Digital outputchannel for SPI clock and Digital output channel for CS require both a single channel number.

3 Simulation

From the System tab of the Coder options... window, select the “Subsystem” and go to the Targettab. Build the “RT Box” model onto the RT Box. Once the model is uploaded, from the ExternalMode tab of the Coder options... window, Connect to the RT Box and Activate autotriggering.The real-time simulation results can be observed via PLECS Scope called “TX/RX Overview”.

3.1 SPI Transmission within a Single Model Step

This is the default setup in the Model initialization commands of this demo model. It is done by en-abling type = ‘single’, which sets:

• RT Box discretization step size = 20µs• SPI transmission sample time = 20µs

Sinewave

Pulsewave

Validport

0

0

Time(s)0.0 0.1 0.2 0.3 0.4

0.0

0.5

1.0

1.5

ReferenceReceivedvalue

ReferenceReceivedvalue

SPIMaster:v

Figure 3: Real-time simulation result on PLECS Scope for SPI transmission within single model step

Once the real-time simulation is running on the RT Box and the external mode is enabled, the wave-forms on “TX/RX Overview” Scope are shown in Fig. 3. The received value matches the reference valuein terms of amplitude and frequency for both the sine wave and the pulse wave, which validates theSPI loop-back function.

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SPI interface loop-back demo on a single RT Box

Fig. 4 shows the zoom-in of Fig. 3 around 0.3 s. The incoming SPI Master data exhibits a staircasewaveform with step size of 20µs, which equals to the RT Box discretization step size. There is a delayof two SPI transmission intervals between the outgoing reference signal and the received data.

Sinewave

Pulsewave

Validport

×1e4

3.20

3.25

3.30

0.0

0.5

1.0

×1e-1Time(s)

2.9996 2.9998 3.0000 3.0002 3.00040.0

0.5

1.0

1.5

ReferenceReceivedvalue

ReferenceReceivedvalue

SPIMaster:v

Figure 4: Zoom-in around 0.3 s of the real-time simulation result on PLECS Scope for SPI transmissionwithin single model step

For more insight on the timing, an external oscilloscope is used to measure the different digital chan-nels and the RT Box step size. In Fig. 5 probe CH1 shows the 0.5 duty cycle PWM synchronized to the20µs model step size. Since the PWM is generated with positive polarity, from the center of the highstate to the center of the next high state marks exactly one model step. One can see that in this sce-nario, the SPI transmission happens within every RT Box model step.

3.2 SPI Transmission over Multiple Model Steps

This scenario can be chosen by commenting out the previous type=‘single’ and enablingtype=‘multi’ in the model initialization commands of this demo model. This sets:

• RT Box discretization step size = 5µs• SPI transmission sample time = 20µs

This is to demonstrate the case when the SPI transmission time (approx. SPI clock period x Bits perword x Words per transmission) requires more time than what a single RT Box step offers. Note thatthe SPI transmission interval can only be integer multiples of the RT Box step size.

The real-time simulation waveforms on the “TX/RX Overview” Scope look similar to Fig. 3 on a largetime scale. However, the zoom-in shown in Fig. 6 reveals the difference. For example, the Sine wavereference signal is discretized with 5µs now, while the incoming SPI data is still updated every 20µs.The complete SPI transmission takes 4 full RT Box calculation steps. There are still two SPI transmis-sion steps delay in the loop-back scenario between the reference signal and the received data.

Fig. 7 provides more insight with the oscilloscope measurement. Probe CH1 shows the 0.5 duty cyclePWM indicating the new 5µs model step size. CH2 to CH4 show the SPI transmission at 20µs sampletime, which are exactly 4 times a model step.

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SPI interface loop-back demo on a single RT Box

Figure 5: External oscilloscope measurement for SPI transmission within single model step

Sinewave

Pulsewave

Validport

×1e4

3.20

3.25

3.30

0.0

0.5

1.0

×1e-1Time(s)

2.9996 2.9998 3.0000 3.0002 3.00040.0

0.5

1.0

1.5

ReferenceReceivedvalue

ReferenceReceivedvalue

SPIMaster:v

Figure 6: Zoom-in around 0.3 s of the real-time simulation result on PLECS Scope for SPI transmissionextended over multiple model steps

4 Conclusion

This RT Box demo model demonstrates a loop-back test using the integrated SPI interface on the RTBox. It shows how to set up the SPI Master block in a PLECS model. The demo model runs in bothoffline and in real-time simulation.

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SPI interface loop-back demo on a single RT Box

Figure 7: External oscilloscope measurement for SPI transmission extended over multiple model steps

5 Appendix

For the synchronous SPI transmission with the RT Box model step size case, a more advanced demo isprovided. Fig. 8 depicts the setup and pin connection for this scenario.

RT Box

AO-0

AGND

DI-1 (SPI RX)

DO-0 (SPI CLK)

DO-3 (SPI CS)

EVAL-AD7980-PMDZ (16-bit ADC)

Vin+

Vin- SDO

SCK

CNV

SDI

+Vcc

Figure 8: Pin connection between the RT Box and the external ADC board for the advanced SPI demo

The RT Box works as the SPI Master and generates a sinusoidal analog signal between 0.5 V and4.5 V at 50 Hz. The 16-bit ADC evaluation board (EVAL-AD7980-PMDZ) converts this analog signalinto digital values and works as the SPI Slave to send the converted data to the RT Box SPI interface.

Note that in this demo the RT Box SPI CS signal is used as the CNV (conversion start) signal of theADC and the ADC SDI pin is tied up to the supply voltage. Please see section “3-WIRE CS MODEWITHOUT BUSY INDICATOR” in [1]. In case of using two AD7980 devices together, one might needspecific timing patterns of CNV, and CS1 CS2 for SDI pin of each ADC. In this case, duty cycle andcarrier phase shift of the PWMs synchronized with the SPI transmission sample time can be properlyadjusted to achieve the desired signals.

The RT Box subsystem circuit schematic is shown in Fig. 9. Scope “Ref/RX Overview” shows the com-parison between the analog reference signal sent out from the RT Box and received SPI data after ex-

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SPI interface loop-back demo on a single RT Box

ternal ADC conversion.

Once the model is uploaded onto the RT Box and the external mode is enabled, the real-time simula-tion results can be observed as shown in Fig. 10.

SPIMaster

v

SPIMaster

Ref/RXOverview

PWMOut

PWMOut0.5

AnalogOut

AnalogOut

u/(2^16)*5

SineWave

RX

RX

RX

Ref

Ref

Figure 9: Subsystem circuit schematic for the advanced SPI demo on the RT Box

ExternalADCsampleddigitaldata(16-bit)

Digitaldataconvertedtoanalogvalue

Validport

×1e4

0

2

4

6

Voltag

e(V)

2

4

×1e-2Time(s)

0.0 0.5 1.0 1.50.0

0.5

1.0

1.5

Receivedvalue

AnalogreferenceReceivedvalue

SPIMaster:v

Figure 10: Real-time simulation result on PLECS Scope of the advanced SPI demo

References

[1] Analog Devices AD7980 datasheet [Online]. Available: https://www.analog.com/media/en/technical-documentation/data-sheets/AD7980.pdf.

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Revision History:

RT Box Target Support Package 2.1.1 First release

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RT Box Demo Model

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