SONICS, INC.

Drew Wingard

2440 West El Camino Real, Suite 620Mountain View, California 94040650-938-2500 Fax 650-938-2577

http://www.sonicsinc.com

Sonics SOC IntegrationSonics SOC IntegrationArchitectureArchitecture

SONICS, INC.SONICS, INC.

(Systems-ON-ICS)

P1500 Presentation 99/1/28 2SONICS, INC.SONICS, INC.

OverviewOverview

� Background� Architecture Overview� Implementation� Summary


SOC Data Flow

DSPCPUDMA A

C MEM I O O

SOC Applications and Data FlowSOC Applications and Data Flow

APPLICATION AREA

DIGITAL CAMERA

COLOR PRINTERS

NEXT GENERATION STB

NETWORK SWITCHING

SOHO MULTIMEDIA

XDSL INTERFACE

DIGITAL TELEVISION

DIGITAL VIDEO SERVER

WORLD PHONE


Characteristics:� Wide performance

range

� Increasing real-timemultimedia/networkingtraffic

� Shared memoryrequirements

� Complex interactions

� Challenging Design

System-on-a-Chip CommunicationsSystem-on-a-Chip Communications

PCI

IP Core Communications Bandwidth

DSP

ATM

CPU

3D

Video/2D

LAN

4M 16M 64M 256M 1G 4G 16G 64G 256GBandwidth (bits/sec)

P1394

Real-Time

Performance-Driven


Conventional ApproachConventional Approach

SOC Design Requirements� New design for each system� Match system design cycle

System

SOC

� Hit cost/performance goals

DMA CPU DSP

A

B

Bridge

C I O O

Design Time


Highly configurable communication structurewith tools that simplify making complex & highperformance IP blocks successfully inter-operatein an SOC.

Value Proposition• SonicsIA cuts design time by 50%

• SonicsIA increases value (productivity) ofresources (people, IP, tools)

Sonics Integration Architecture (SonicsIA)Sonics Integration Architecture (SonicsIA)


ComparisonComparison

Conventional Sonics IntegrationArchitecture

DMA CPU DSP

A

B

Bridge

C I O O Sonics ModuleInterface

PeripheralBus

SystemBus

CustomInterfaces

DSPCPUDMA A

C B I O O

Sonics Silicon Backplane

Allows unification of allon-chip communication


SonicsIASonicsIAAspects*Aspects*

� Tunable CommunicationsSubsystems– Silicon BackplaneTM

– Logic BackplaneTM

� Configurable IP CoreInterface– Sonics Module Interface

� Design Software– SonicsIA Compilers– SonicsIA Workbenches

* Patent Pending

DSPCPUDMA A

C MEM I O

Sonics Module Interface

Initiator Module

Target Module

Logic Backplane Bridge

Silicon Backplane


Bus Bandwidth RequirementsBus Bandwidth Requirements

� Must satisfy sum ofsustained BW

� Total bus BW >peak BW of any IP Core

� Bandwidth mismatchbetween Bus and IPCores

� Need de-coupled Busperformance

SOC Data Flow

DSPCPUDMA A

C MEM I O O

< 10 Mbits/sec

< 100 Mbits/sec

> 100 Mbits/sec


Computer Bus ApproachComputer Bus Approach

IPCore

IPCore

��

�

IPCore

IPCore

��

�

ComputerBus

Transmit FIFO Receive FIFO

Time

Data

Arbiter Address


Communication Bus ApproachCommunication Bus Approach

IPCore

IPCore

��

�

IPCore

IPCore

��

�

CommunicationsBus

Transmit FIFO Receive FIFO

Time

Data

TDMA TDMA


From Communications� Efficient BW De-coupling� Guaranteed BW & Latency� Side-band Signaling

Integration Architecture FeaturesIntegration Architecture Features

From Computing� Address-based Selection� Write and Read Transfers� Pipelining

DSPCPUDMA A

C MEM I O

Integration Architecture


Guaranteed Bandwidth ArbitrationGuaranteed Bandwidth Arbitration

� Independent arbitration for every cycle� Two phases

– Distributed TDMA– Round robin

� Gives SOC designer fine control oversystem bandwidth

CurrentSlot

Arbitration

Command


Guaranteed LatencyGuaranteed Latency

� Fixed latency between command/address anddata/response phases

� Matches pipelined CPU model– High performance access to on-chip resources

� Allows routing of pipelined data through Backplane

� Latency is re-programmable in software� Variable-latency IP Cores do not tie up the

Backplane


Memory-Mapped Address SpaceMemory-Mapped Address Space

� IP Cores accessed only via Read / Write commands� Interface Modules decode addresses for IP Core

selection� Interface Module address match logic features:

– Variable match width– Multiple match regions– Positive / Negative decoding– Subtractive decoding

� Module Configuration Registers– Access re-programmable / hardwired Backplane features– IP Core device control registers


Pipeline DiagramPipeline Diagram

Cycle 1 2 3 4 5 6 7 8

Arbitration

Command WR WR

Address A1 A2

Data D1 D2

Response


Integrated Signaling MechanismIntegrated Signaling Mechanism

� Dedicated Backplane wires (Flags ) support:

– Bus-style Out-of-Band Signaling (Interrupts)

– Point-to-Point Communications (Flow control)

– Dynamic point-to-point (Retry mechanism)

� Integral part of Integration Architecture– Same design flow, timing, flexibility as address/data part


Logic Backplane

Silicon Backplane

Off-Chip Extension: Logic BackplaneOff-Chip Extension: Logic Backplane

CPU-Based ASSP

ASSP

PLD


Target Module Block DiagramTarget Module Block Diagram

Silicon Backplane Interface

Sonics Module Interface

AddressDecoder

CLOCK

ConfigurationRegisters

Address/DataFlow

Synchronizer (Optional)÷÷÷÷

Clock

Address /Control

Data


Sonics Module Interface: BasicsSonics Module Interface: Basics

Signal Driver Width CommentsClock Any 1 Driven by Master, Slave, or otherCmd Master ≤ 3 Idle, Read, Write + extensionsAddr Master Varies Req. Address; VC specs widthDataOut Master Varies Write Data; VC specs widthReqAccept Slave 1 Slave accepts requestResp Slave ≤ 3 Response to prior requestDataIn Slave Varies Read Data; valid based on RespRespAccept Master 1 Master accepts response

Simple Synchronous Read/Write Protocolwith Variable Widths and Flow Control


VSIA CorrespondenceVSIA Correspondence

Silicon BackplaneProtocol

Physical Bus

TransactionProtocol

Bus TransferProtocol

Sonics ModuleInterface

VSIA On-chipBus Model

SonicsIntegration

Architecture

PhysicalBus

VirtualComponent

Interface

VirtualComponent


Bandwidth EngineeringBandwidth Engineering

Define System SpecificationsDefine System Specifications

Partition SystemPartition System

Analyze PerformanceAnalyze Performance

Select / DesignIP Cores

Select / DesignIP Cores

Simulate / Integrate SOCSimulate / Integrate SOC

SonicsIACompilers

SonicsIACompilers

System Bandwidth &Latency Constraints

IP Core

Requirements

IP Cores Silicon Backplane


Validation / TestValidation / Test

� Silicon Backplane is highlyvisible for test– All subsystems communicate

through Backplane

� Test Interfaces:– Logic Backplane: 100’s MB/s– Snooping Module: Scan-based

� Each subsystem can betested/validated stand-alone

TestVectors

TestVectors

LogicBackplane


Silicon Backplane Performance RoadmapSilicon Backplane Performance Roadmap

0

1000

2000

3000

4000

5000

MBytesper

second

Silicon Backplane Bandwidth Range

HardFirmSoft

0.35µµµµm 0.25µµµµm 0.18µµµµm

Version

Soft and Firm versions should satisfy 90% of SOC applications


SummarySummary

DMA CPU DSP

A

B

Bridge

C I O O Sonics ModuleInterface

PeripheralBus

SystemBus

CustomInterfaces

DSPCPUDMA A

C B I O O

Sonics Silicon Backplane

SonicsIA Benefits� Simplified Design� Guaranteed Performance� Reduced Iteration Cost� Higher IP Library Value� Increased Flexibility

� On Time!� On Spec!

� On Budget!

SONICS, INC.

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