Sonali Manual_2nd August 2007

Maharashtra Academy of Engineering, Alandi DEL Manual

EXPERIMENT No: 1

Title: T.T.L Characteristics (Study and Write up only).

Relevant Theory:

Transistor–Transistor Logic (TTL) is a class of digital circuits built from bipolar junction transistors (BJT), and resistors. It is called transistor–transistor logic because both the logic gating function (e.g., AND) and the amplifying function are performed by transistors (contrast this with RTL and DTL). It is notable for being a widespread integrated circuit (IC) family used in many applications such as computers, industrial controls, test equipment and instrumentation, consumer electronics, synthesizers, etc. Because of the wide use of this logic family, signal inputs and outputs of electronic equipment may be called "TTL" inputs or outputs, signifying compatibility with the voltage levels used.

Comparison with other logic families

Generally, TTL devices consume more power than an equivalent CMOS device at rest, but power consumption does not increase with clock speed as rapidly as for CMOS devices. Compared to contemporary ECL circuits, TTL uses less power and has easier design rules, but is typically slower; designers can combine ECL and TTL devices in the same system to achieve best overall performance and economy. TTL was less sensitive to damage from electrostatic discharge than early CMOS devices.

Due to the output structure of TTL devices, the output impedance is asymmetrical between the high and low state, making them unsuitable for driving transmission lines. This is usually solved by buffering the outputs with special line driver devices where signals need to be sent through cables. ECL, by virtue of its symmetric output structure, doesn't have this drawback.

Several manufacturers now supply CMOS logic equivalents with TTL compatible input and output levels, usually bearing part numbers similar to the equivalent TTL component and with the same pin-out diagrams.

Now-a-days digital integrated circuits are most commonly used in modern digital systems. The most of the digital circuits are constructed in single chip, which are referred to as Integrated Circuits (IC).

A group of compatible ICs with the same logic levels and supply voltages for performing various logic functions have been fabricated using a specific circuit configuration, which is referred to as a Logic Family.

There are two types of Logic Families, which are as follows –

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1) Bipolar Logic Family2) Unipolar Logic Family

Bipolar Logic Families: - The main elements of a bipolar IC are resistors, diodes (which are also capacitors) and transistors. Basically there are two types of operations in bipolar ICs:

a) Saturated, andb) Non-saturated

The saturated bipolar logic families are: Resistor-transistor logic (RTL) Direct-coupled transistor logic (DCTL) Integrated-injection logic (I2L) Diode-transistor logic (DTL) High-threshold logic (HTL) and Transistor-transistor logic (TTL)

The non-saturated bipolar logic families are: Schottky TTL, and Emitter-coupled logic (ECL)

Unipolar Logic Families: - MOS devices are unipolar devices and only MOSFETs are employed in MOS logic circuits. The MOS logic families are:

a) PMOSb) NMOS, andc) CMOS

Characteristics of Digital ICs: We know that there are various logic families. The selection of logical families for the application is based on its characteristics, and hence it is necessary to study the characteristics of digital ICs. The various parameters of digital ICs used to compare their performance are:1. Speed of operation2. Power dissipation3. Figure of merit4. Fan-out5. Fan-in

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6. Current and voltage parameters7. Noise immunity8. Operating temperature range9. Power supply requirements10. Propagation Delay11. Current Sinking12. Current Sinking13. Loading Factor

Speed of operation: It is one of the important parameters of digital ICs. Speed of operation of digital ICs should be high. The speed of a digital circuit is specified in terms of the propagation delay time. The input and output waveforms of a logic gate are shown in Fig.1.1.

50% Input

Output50%

Fig.1.1 Input and Output waveforms to define propagation delay time

The propagation delay time of the logic gate is the average of propagation delay time from high state to low state and propagation delay time from low to high state.

The delay times are measured between 50 percent voltage levels of input and output waveforms. There are two delay times:tPHL: It is the delay time measured, when output changes from high to low state.

tPLH: It is the delay time measured, when output changes from low to high state.

The propagation delay between input and output should be as minimum as possible so that the operating speed of IC is high.

Power Dissipation: We know that every electronic circuit requires amount of electric power. Power dissipation is the amount of power dissipated in an IC. It is determined by the current ICC, that it draws from the VCC supply, and is given by VCC X ICC. ICC is the average value of ICC(0) and ICC(1). This power is specified in milliwatts.

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TpHL TpLH


Figure of Merit: The figure of merit of a digital IC is defined as the product of speed and power. The speed is specified in terms of propagation delay time expressed in nanoseconds.

Figure of merit = propagation delay time (ns) X power (mW)

It is specified in pico joules (ns X mW = pJ)A low value of speed-power product is desirable. In a digital circuit, if it is desired to have high speed, i.e. low propagation delay, then there is a corresponding increase in the power dissipation and vice-versa.

Fan-Out: This is the number of similar gates, which can be driven by a gate. High fan-out is advantageous because it reduces the need for additional drivers to drive more gates. Consider the Fig. 1.2.

N numberof loadgates

Fig. 1.2

The driver gate drives the N gate (N is fan-out). If more than one N gates are connected to a load, the current supply by the driver gate is not sufficient to drive the gates or the current sink by the driver gate is more than the rating of the driver gate and gate may be damaged.Using the fan-out of a logic family we can calculate the current component.

Fan-out = minimum of { }

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Fan-In: Number of inputs are connected to gate, which is known as fan-in of the gate. For two inputs gate, fan-in is two and for four inputs gate, fan-in is four.

Current and Voltage Parameters: The following currents and voltages are specified which are very useful in the design of digital systems.High-level input voltage, VIH: This is the minimum input voltage, which is recognized by the gate as logic 1.Low-level input voltage, VIL: This is the maximum input voltage, which is recognized by the gate as logic 0.High-level output voltage, VOH: This is the minimum voltage available at the output corresponding to logic 1.Low-level output voltage, VOL: This is the maximum voltage available at the output corresponding to logic 0.High-level input current, IIH: This is the minimum current, which must be supplied by a driving source corresponding to 1 level voltage.Low-level input current, IIL: This is the minimum current, which must be supplied by a driving source corresponding to 0 level voltage.High-level output current, IOH: This is the maximum current, which the gate can sink in 1 level.Low-level output current, IOL: This is the maximum current, which the gate can sink in 0 level.High-level supply current, ICC (1): This is the supply current when the output of the gate is at logic 1.Low-level supply current, ICC (0): This is the supply current when the output of the gate is at logic 0.The current directions are illustrated in Fig. 1.3.

Fig. 1.3 A gate with current directions marked

Noise Immunity: The circuit’s ability to tolerate noise signals without causing spurious changes in the output voltage is called as Noise Immunity.

To avoid noise problem voltage level VIH(min) is kept a few fractions of voltages below VOH(min) and voltage level VIL(max) is kept above VOL(max) at the design time.

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IIL

IIH

IoL

IoH


Fig. 1.4 Voltage Levels and Noise Margins in ICs

Noise Margin: A quantitative measure of noise immunity is known as noise margin.

* DC Noise Margin:1. Low-level noise margin (NML)- The difference between VIL and VOL i.e. VIL -

VOL is known as low-level noise margin.

NML = VIL - VOL = 0.8 - 0.4 = 400mV2. High-level noise margin (NMH)- The difference between VOH and VIH i.e. VOH –

VIH is known as high-level noise margin.NMH = VOH – VIH = 2.4 – 2 = 400mV

Operating Temperature: The temperature range in which an IC functions properly must be known. The accepted temperature ranges are: 0 to +70o C for consumer and industrial applications and -55o C to +125o C for military purposes.

Power Supply Requirements: The supply voltage (s) and the amount of power required by an IC are important characteristics required to choose the proper power supply.

Propagation Delay :- It is time required by gate to give output when input is applied. Always in ns.

Current Sinking :- The current supply by driver gate to load gate is called as sinking current.

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VOH

VIH

VOL

VILVNL

VNH


When driver gate output is low, then the EB junction of loaded gate become forward bias, and the VCC of load gate passes current through T3 of driver gate this called as sink current.

Current Sourcing :- Source current is a current supply by driver gate to load gate.

When driver gate output is high the current is supplied to the load gate is a sourcing current.

Standard TTL logic levels

Operating conditions: V CC 4.75 V min. to 5.25 V max.74XX chips

PARAMETER CONDITIONS MIN MAX UNITS

Logic 1input voltage

VCC = min 2.0 -- V

Logic 0input voltage

VCC = min -- 0.8 V

Logic 1output voltage

VCC = min - - Iout = -0.4 mA

2.4 -- V

Logic 0output voltage

VCC = min - - Iout = 16 mA

-- 0.4 V

Logic 1input current

VCC = min - - Vin = 2.4 V

-- 0.04 mA


V CC = min - - Vin = 5.5 V

-- 1 mA


VCC = min - - V in = 0.4 V

-- - 1.6 mA

What does it all mean?

VOH Min = Output voltage high minimum with up to 0.4 mA load A good chip is

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guaranteed to output a minimum of 2.4 V logic high up to 0.4 mA

VOL Max = Output voltage low maximum with up to 16 mA load A good chip is guaranteed to output a maximum of 0.4 volts up to 16 mA

VIH Min = Input voltage high minimum 2.0 V A good chip will recognize 2.0 V or greater as a logic high and draw no more than 0.04 mA input current.

VIL Min = Input voltage low maximum 0.8 V A good chip will recognize 0.8 V or less as a logic low and draw no more than 1.6 mA input current.

Fan outFor a logic high, a good chip will source 0.4 mA and maintain a minimum of 2.4 VFor a logic high, the input will draw no more than 0.04 mAThis means that a high output of a good chip will drive 10 inputs high.

For a logic low, a good chip will sink 16 mA and hold the voltage at 0.4 V maximum.For a logic low, the input will draw no more than 1.6 mAThis means that a low output of a good chip will drive 10 inputs low.

This is what is meant by a Fan Out of 10.Any Standard TTL chip that does not meet these specifications is defective and should be replaced.

Noise MarginNotice the 400 mV difference between the specified output voltage of a TTL chip and the input voltage required to recognize a logic level. This 400 mV difference provides a margin such that noise added to the signal does not cause errors. An output voltage with up to 400 mV peak of noise added will still provide a valid logic level to the input of the next stage.

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7400 series TTL IC's: 7400...7449

7400Quad 2-input NAND gates.

+---+--+---+ +---+---*---+ __ 1A |1 +--+ 14| VCC | A | B |/Y | /Y = AB 1B |2 13| 4B +===+===*===+/1Y |3 12| 4A | 0 | 0 | 1 | 2A |4 7400 11| /4Y | 0 | 1 | 1 | 2B |5 10| 3B | 1 | 0 | 1 |/2Y |6 9| 3A | 1 | 1 | 0 |GND |7 8| /3Y +---+---*---+ +----------+

Positive Logic

__Y = AB

Equivalent Chips

SN5400 (J) SN54H00 (J) SN54L00 (J) SN54LS00 (J,W) SN54S00 (J,W) SN7400 (J,N) SN74H00 (J,N)

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SN74L00 (J,N) SN74LS00 (J,N) SN47S00 (J,N)

7401Quad 2-input open-collector NAND gates. +---+--+---+ +---+---*---+ __/1Y |1 +--+ 14| VCC | A | B |/Y | /Y = AB 1A |2 13| /4Y +===+===*===+ 1B |3 12| 4B | 0 | 0 | Z |/2Y |4 7401 11| 4A | 0 | 1 | Z | 2A |5 10| /3Y | 1 | 0 | Z | 2B |6 9| 3B | 1 | 1 | 0 |GND |7 8| 3A +---+---*---+ +----------+

7402Quad 2-input NOR gates. +---+--+---+ +---+---*---+ ___/1Y |1 +--+ 14| VCC | A | B |/Y | /Y = A+B 1A |2 13| /4Y +===+===*===+ 1B |3 12| 4B | 0 | 0 | 1 |/2Y |4 7402 11| 4A | 0 | 1 | 0 | 2A |5 10| /3Y | 1 | 0 | 0 | 2B |6 9| 3B | 1 | 1 | 0 |GND |7 8| 3A +---+---*---+ +----------+

7403Quad 2-input open-collector NAND gates. +---+--+---+ +---+---*---+ __ 1A |1 +--+ 14| VCC | A | B |/Y | /Y = AB 1B |2 13| 4B +===+===*===+/1Y |3 12| 4A | 0 | 0 | Z | 2A |4 7403 11| /4Y | 0 | 1 | Z | 2B |5 10| 3B | 1 | 0 | Z |/2Y |6 9| 3A | 1 | 1 | 0 |GND |7 8| /3Y +---+---*---+ +----------+

7404Hex inverters.

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+---+--+---+ +---*---+ _ 1A |1 +--+ 14| VCC | A |/Y | /Y = A/1Y |2 13| 6A +===*===+ 2A |3 12| /6Y | 0 | 1 |/2Y |4 7404 11| 5A | 1 | 0 | 3A |5 10| /5Y +---*---+/3Y |6 9| 4AGND |7 8| /4Y +----------+

Positive Logic

_Y = A

Equivalent Chips

SN5404 (J) SN54H04 (J) SN54L04 (J) SN54LS04 (J,W) SN54S04 (J,W) SN7404 (J,N) SN74H04 (J,N) SN74L04 (J,N) SN74LS04 (J,N) SN47S04 (J,N)

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7405Hex open-collector inverters. +---+--+---+ +---*---+ _ 1A |1 +--+ 14| VCC | A |/Y | /Y = A/1Y |2 13| 6A +===*===+ 2A |3 12| /6Y | 0 | Z |/2Y |4 7405 11| 5A | 1 | 0 | 3A |5 10| /5Y +---*---+/3Y |6 9| 4AGND |7 8| /4Y +----------+

7406Hex open-collector high-voltage inverters. Maximum output voltage is 30V. +---+--+---+ +---*---+ _ 1A |1 +--+ 14| VCC | A |/Y | /Y = A/1Y |2 13| 6A +===*===+ 2A |3 12| /6Y | 0 | Z |/2Y |4 7406 11| 5A | 1 | 0 | 3A |5 10| /5Y +---*---+/3Y |6 9| 4AGND |7 8| /4Y +----------+

7407Hex open-collector high-voltage buffers. Maximum output voltage is 30V. +---+--+---+ +---*---+ 1A |1 +--+ 14| VCC | A | Y | Y = A 1Y |2 13| 6A +===*===+ 2A |3 12| 6Y | 0 | 0 | 2Y |4 7407 11| 5A | 1 | Z | 3A |5 10| 5Y +---*---+ 3Y |6 9| 4AGND |7 8| 4Y +----------+

7408Quad 2-input AND gates.

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+---+--+---+ +---+---*---+ 1A |1 +--+ 14| VCC | A | B | Y | Y = AB 1B |2 13| 4B +===+===*===+ 1Y |3 12| 4A | 0 | 0 | 0 | 2A |4 7408 11| 4Y | 0 | 1 | 0 | 2B |5 10| 3B | 1 | 0 | 0 | 2Y |6 9| 3A | 1 | 1 | 1 |GND |7 8| 3Y +---+---*---+ +----------+

Positive Logic

Y = AB

7409Quad 2-input open-collector AND gates. +---+--+---+ +---+---*---+ 1A |1 +--+ 14| VCC | A | B | Y | Y = AB 1B |2 13| 4B +===+===*===+ 1Y |3 12| 4A | 0 | 0 | 0 | 2A |4 7409 11| 4Y | 0 | 1 | 0 | 2B |5 10| 3B | 1 | 0 | 0 | 2Y |6 9| 3A | 1 | 1 | Z |GND |7 8| 3Y +---+---*---+ +----------+

7410Triple 3-input NAND gates.

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+---+--+---+ +---+---+---*---+ ___ 1A |1 +--+ 14| VCC | A | B | C |/Y | /Y = ABC 1B |2 13| 1C +===+===+===*===+ 2A |3 12| /1Y | 0 | X | X | 1 | 2B |4 7410 11| 3C | 1 | 0 | X | 1 | 2C |5 10| 3B | 1 | 1 | 0 | 1 |/2Y |6 9| 3A | 1 | 1 | 1 | 0 |GND |7 8| /3Y +---+---+---*---+ +----------+

Positive Logic

___Y = ABC

7411Triple 3-input AND gates. +---+--+---+ +---+---+---*---+ 1A |1 +--+ 14| VCC | A | B | C | Y | Y = ABC 1B |2 13| 1C +===+===+===*===+ 2A |3 12| 1Y | 0 | X | X | 0 | 2B |4 7411 11| 3C | 1 | 0 | X | 0 | 2C |5 10| 3B | 1 | 1 | 0 | 0 | 2Y |6 9| 3A | 1 | 1 | 1 | 1 |GND |7 8| 3Y +---+---+---*---+ +----------+

7412Triple 3-input open-collector NAND gates.

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+---+--+---+ +---+---+---*---+ ___ 1A |1 +--+ 14| VCC | A | B | C |/Y | /Y = ABC 1B |2 13| 1C +===+===+===*===+ 2A |3 12| /1Y | 0 | X | X | Z | 2B |4 7410 11| 3C | 1 | 0 | X | Z | 2C |5 10| 3B | 1 | 1 | 0 | Z |/2Y |6 9| 3A | 1 | 1 | 1 | 0 |GND |7 8| /3Y +---+---+---*---+ +----------+

7413Dual 4-input NAND gates with schmitt-trigger inputs. 0.8V typical input hysteresis at VCC=+5V. +---+--+---+ +---+---+---+---*---+ ____ 1A |1 +--+ 14| VCC | A | B | C | D |/Y | /Y = ABCD 1B |2 13| 2D +===+===+===+===*===+ |3 12| 2C | 0 | X | X | X | 1 | 1C |4 7413 11| | 1 | 0 | X | X | 1 | 1D |5 10| 2B | 1 | 1 | 0 | X | 1 |/1Y |6 9| 2A | 1 | 1 | 1 | 0 | 1 |GND |7 8| /2Y | 1 | 1 | 1 | 1 | 0 | +----------+ +---+---+---+---*---+

7414Hex inverters with schmitt-trigger inputs. 0.8V typical input hysteresis at VCC=+5V. +---+--+---+ +---*---+ _ 1A |1 +--+ 14| VCC | A |/Y | /Y = A/1Y |2 13| 6A +===*===+ 2A |3 12| /6Y | 0 | 1 |/2Y |4 7414 11| 5A | 1 | 0 | 3A |5 10| /5Y +---*---+/3Y |6 9| 4AGND |7 8| /4Y +----------+

7415Triple 3-input open-collector AND gates. +---+--+---+ +---+---+---*---+ 1A |1 +--+ 14| VCC | A | B | C | Y | Y = ABC 1B |2 13| 1C +===+===+===*===+ 2A |3 12| 1Y | 0 | X | X | 0 | 2B |4 7415 11| 3C | 1 | 0 | X | 0 | 2C |5 10| 3B | 1 | 1 | 0 | 0 | 2Y |6 9| 3A | 1 | 1 | 1 | Z |GND |7 8| 3Y +---+---+---*---+ +----------+

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7416Hex open-collector high-voltage inverters. Maximum output voltage is 15V. +---+--+---+ +---*---+ _ 1A |1 +--+ 14| VCC | A |/Y | /Y = A/1Y |2 13| 6A +===*===+ 2A |3 12| /6Y | 0 | Z |/2Y |4 7416 11| 5A | 1 | 0 | 3A |5 10| /5Y +---*---+/3Y |6 9| 4AGND |7 8| /4Y +----------+

7417Hex open-collector high-voltage buffers. Maximum output voltage is 15V. +---+--+---+ +---*---+ 1A |1 +--+ 14| VCC | A | Y | Y = A 1Y |2 13| 6A +===*===+ 2A |3 12| 6Y | 0 | 0 | 2Y |4 7417 11| 5A | 1 | Z | 3A |5 10| 5Y +---*---+ 3Y |6 9| 4AGND |7 8| 4Y +----------+

7418Dual 4-input NAND gates with schmitt-trigger inputs. 0.8V typical input hysteresis at VCC=+5V. +---+--+---+ +---+---+---+---*---+ ____ 1A |1 +--+ 14| VCC | A | B | C | D |/Y | /Y = ABCD 1B |2 13| 2D +===+===+===+===*===+ |3 12| 2C | 0 | X | X | X | 1 | 1C |4 7418 11| | 1 | 0 | X | X | 1 | 1D |5 10| 2B | 1 | 1 | 0 | X | 1 |/1Y |6 9| 2A | 1 | 1 | 1 | 0 | 1 |GND |7 8| /2Y | 1 | 1 | 1 | 1 | 0 | +----------+ +---+---+---+---*---+

7419Hex inverters with schmitt-trigger line-receiver inputs. 0.8V typical input hysteresis at VCC=+5V. +---+--+---+ +---*---+ _ 1A |1 +--+ 14| VCC | A |/Y | /Y = A/1Y |2 13| 6A +===*===+ 2A |3 12| /6Y | 0 | 1 |/2Y |4 7414 11| 5A | 1 | 0 | 3A |5 10| /5Y +---*---+/3Y |6 9| 4AGND |7 8| /4Y

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+----------+

7420Dual 4-input NAND gates. +---+--+---+ +---+---+---+---*---+ ____ 1A |1 +--+ 14| VCC | A | B | C | D |/Y | /Y = ABCD 1B |2 13| 2D +===+===+===+===*===+ |3 12| 2C | 0 | X | X | X | 1 | 1C |4 7420 11| | 1 | 0 | X | X | 1 | 1D |5 10| 2B | 1 | 1 | 0 | X | 1 |/1Y |6 9| 2A | 1 | 1 | 1 | 0 | 1 |GND |7 8| /2Y | 1 | 1 | 1 | 1 | 0 | +----------+ +---+---+---+---*---+

7421Dual 4-input AND gates. +---+--+---+ +---+---+---+---*---+ 1A |1 +--+ 14| VCC | A | B | C | D | Y | Y = ABCD 1B |2 13| 2D +===+===+===+===*===+ |3 12| 2C | 0 | X | X | X | 0 | 1C |4 7421 11| | 1 | 0 | X | X | 0 | 1D |5 10| 2B | 1 | 1 | 0 | X | 0 | 1Y |6 9| 2A | 1 | 1 | 1 | 0 | 0 |GND |7 8| 2Y | 1 | 1 | 1 | 1 | 1 | +----------+ +---+---+---+---*---+

7422Dual 4-input open-collector NAND gates. +---+--+---+ +---+---+---+---*---+ ____ 1A |1 +--+ 14| VCC | A | B | C | D |/Y | /Y = ABCD 1B |2 13| 2D +===+===+===+===*===+ |3 12| 2C | 0 | X | X | X | Z | 1C |4 7422 11| | 1 | 0 | X | X | Z | 1D |5 10| 2B | 1 | 1 | 0 | X | Z |/1Y |6 9| 2A | 1 | 1 | 1 | 0 | Z |GND |7 8| /2Y | 1 | 1 | 1 | 1 | 0 | +----------+ +---+---+---+---*---+

7424Quad 2-input NAND gates with schmitt-trigger line-receiver inputs. 0.8V typical input hysteresis at VCC=+5V. +---+--+---+ +---+---*---+ __ 1A |1 +--+ 14| VCC | A | B |/Y | /Y = AB 1B |2 13| 4B +===+===*===+/1Y |3 12| 4A | 0 | 0 | 1 | 2A |4 7424 11| /4Y | 0 | 1 | 1 | 2B |5 10| 3B | 1 | 0 | 1 |/2Y |6 9| 3A | 1 | 1 | 0 |GND |7 8| /3Y +---+---*---+ +----------+

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7425Dual 4-input NOR gates with enable input. +---+--+---+ __________ 1A |1 +--+ 14| VCC Y = G(A+B+C+D) 1B |2 13| 2D 1G |3 12| 2C 1C |4 7425 11| 2G 1D |5 10| 2B/1Y |6 9| 2AGND |7 8| /2Y +----------+

7426Quad 2-input open-collector high-voltage NAND gates. Maximum output voltage is 15V. +---+--+---+ +---+---*---+ __ 1A |1 +--+ 14| VCC | A | B |/Y | /Y = AB 1B |2 13| 4B +===+===*===+/1Y |3 12| 4A | 0 | 0 | Z | 2A |4 7426 11| /4Y | 0 | 1 | Z | 2B |5 10| 3B | 1 | 0 | Z |/2Y |6 9| 3A | 1 | 1 | 0 |GND |7 8| /3Y +---+---*---+ +----------+

7427Triple 3-input NOR gates. +---+--+---+ +---+---+---*---+ _____ 1A |1 +--+ 14| VCC | A | B | C |/Y | /Y = A+B+C 1B |2 13| 1C +===+===+===*===+ 2A |3 12| /1Y | 0 | 0 | 0 | 1 | 2B |4 7427 11| 3C | 0 | 0 | 1 | 0 | 2C |5 10| 3B | 0 | 1 | X | 0 |/2Y |6 9| 3A | 1 | X | X | 0 |GND |7 8| /3Y +---+---+---*---+ +----------+

7428Quad 2-input NOR gates with buffered outputs. +---+--+---+ +---+---*---+ ___/1Y |1 +--+ 14| VCC | A | B |/Y | /Y = A+B 1A |2 13| /4Y +===+===*===+ 1B |3 12| 4B | 0 | 0 | 1 |/2Y |4 7428 11| 4A | 0 | 1 | 0 | 2A |5 10| /3Y | 1 | 0 | 0 | 2B |6 9| 3B | 1 | 1 | 0 |GND |7 8| 3A +---+---*---+ +----------+

74308-input NAND gate.

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+---+--+---+ ________ A |1 +--+ 14| VCC /Y = ABCDEFGH B |2 13| C |3 12| H D |4 7430 11| G E |5 10| F |6 9|GND |7 8| /Y +----------+

Positive Logic

________Y = ABCDEFGH

7431Hex delay elements. Typical delays are 27.5ns (1,6), 46.5ns (2,5), 6ns (3,4). Improved output currents IoH=-1.2mA, IoL=24mA for gates 3 and 4. +---+--+---+ _ _____ 1A |1 +--+ 16| VCC /1Y=1A /4Y=4A.4B/1Y |2 15| 6A 2A |3 14| /6Y 2Y=2A 5Y=5A 2Y |4 13| 5A _____ _ 3A |5 7431 12| 5Y /3Y=3A.3B /6Y=6A 3B |6 11| 4B/3Y |7 10| 4AGND |8 9| /4Y +----------+

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7432Quad 2-input OR gates.

+---+--+---+ +---+---*---+ 1A |1 +--+ 14| VCC | A | B | Y | Y = A+B 1B |2 13| 4B +===+===*===+ 1Y |3 12| 4A | 0 | 0 | 0 | 2A |4 7432 11| 4Y | 0 | 1 | 1 | 2B |5 10| 3B | 1 | 0 | 1 | 2Y |6 9| 3A | 1 | 1 | 1 |GND |7 8| 3Y +---+---*---+ +----------+

Positive Logic

Y = A+B

7433Quad 2-input open-collector NOR gates. +---+--+---+ +---+---*---+ ___/1Y |1 +--+ 14| VCC | A | B |/Y | /Y = A+B 1A |2 13| /4Y +===+===*===+ 1B |3 12| 4B | 0 | 0 | Z |/2Y |4 7433 11| 4A | 0 | 1 | 0 | 2A |5 10| /3Y | 1 | 0 | 0 | 2B |6 9| 3B | 1 | 1 | 0 |GND |7 8| 3A +---+---*---+ +----------+

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7437Quad 2-input NAND gates with buffered output. +---+--+---+ +---+---*---+ __ 1A |1 +--+ 14| VCC | A | B |/Y | /Y = AB 1B |2 13| 4B +===+===*===+/1Y |3 12| 4A | 0 | 0 | 1 | 2A |4 7437 11| /4Y | 0 | 1 | 1 | 2B |5 10| 3B | 1 | 0 | 1 |/2Y |6 9| 3A | 1 | 1 | 0 |GND |7 8| /3Y +---+---*---+ +----------+

7438Quad 2-input open-collector NAND gates with buffered output. +---+--+---+ +---+---*---+ __ 1A |1 +--+ 14| VCC | A | B |/Y | /Y = AB 1B |2 13| 4B +===+===*===+/1Y |3 12| 4A | 0 | 0 | Z | 2A |4 7438 11| /4Y | 0 | 1 | Z | 2B |5 10| 3B | 1 | 0 | Z |/2Y |6 9| 3A | 1 | 1 | 0 |GND |7 8| /3Y +---+---*---+ +----------+

7440Dual 4-input NAND gates with buffered output. +---+--+---+ +---+---+---+---*---+ ____ 1A |1 +--+ 14| VCC | A | B | C | D |/Y | /Y = ABCD 1B |2 13| 2D +===+===+===+===*===+ |3 12| 2C | 0 | X | X | X | 1 | 1C |4 7440 11| | 1 | 0 | X | X | 1 | 1D |5 10| 2B | 1 | 1 | 0 | X | 1 |/1Y |6 9| 2A | 1 | 1 | 1 | 0 | 1 |GND |7 8| /2Y | 1 | 1 | 1 | 1 | 0 | +----------+ +---+---+---+---*---+

74421-of-10 inverting decoder/demultiplexer. +---+--+---+ +---+---+---+---*---+---+---+---+/Y0 |1 +--+ 16| VCC | S3| S2| S1| S0|/Y0|/Y1|...|/Y9|/Y1 |2 15| S0 +===+===+===+===*===+===+===+===+/Y2 |3 14| S1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 |/Y3 |4 13| S2 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 |/Y4 |5 7442 12| S3 | . | . | . | . | 1 | 1 | . | 1 |/Y5 |6 11| /Y9 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |/Y6 |7 10| /Y8 | 1 | 0 | 1 | X | 1 | 1 | 1 | 1 |GND |8 9| /Y7 | 1 | 1 | X | X | 1 | 1 | 1 | 1 | +----------+ +---+---+---+---*---+---+---+---+

21


7446, 7447Open-collector BCD to 7-segment decoder/common-anode LED driver with ripple blank input and output. 7446 has 30V outputs, 7447 has 15V outputs. +---+--+---+ A1 |1 +--+ 16| VCC A2 |2 15| /YF /LT |3 14| /YG/RBO |4 13| /YA/RBI |5 7447 12| /YB A3 |6 11| /YC A0 |7 10| /YD GND |8 9| /YE +----------+

7448BCD to 7-segment decoder/common-cathode LED driver with ripple blank input and output. +---+--+---+ A1 |1 +--+ 16| VCC A2 |2 15| YF /LT |3 14| YG/RBO |4 13| YA/RBI |5 7448 12| YB A3 |6 11| YC A0 |7 10| YD GND |8 9| YE +----------+

Conclusion:TTL logic family characteristics and ICs are thoroughly studied.

22


EXPERIMENT No: 2

Title: Code converters, e.g. Excess-3 to BCD and vice versa.

AIM: - To study following code converters and verify the truth table.a) Binary to Grayb) Gray to Binaryc) Excess 3 to BCDd) BCD to Excess 3

APARATUS: - 1) Digital Trainer kit 2) Connecting wires 3) ICs-- 7404,7486,7408,7432.

THEORY: -

A) Binary to Gray:- Any Binary no. converted into Gray code using following method. For example: - Binary ---- 1 0 0 1 (add)

1 1 0 1 B) Gray to Binary :- Any Gray no. converted into Binary code using following method .

For Example :- Gray ---- 1 1 0 1

1 0 0 1 C) BCD to Excess 3 :- Add 3 to each digit of BCD no. which is to be converted into Excess 3. For Example :- BCD ---- 0 1 1 0

+ 0 0 1 1

1 0 0 1

D) Excess 3 to BCD :-

23


Subtract 3 from the given no. to get BCD no. For Example: - XS3 ---- 1 0 0 1

- 0 0 1 1

0 1 1 0

DESIGN: -

a) Convert 4 bit Binary code into Gray code.1) Truth table.

Binary Inputs Gray OutputsB3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 10 0 1 1 0 0 1 00 1 0 0 0 1 1 00 1 0 1 0 1 1 10 1 1 0 0 1 0 10 1 1 1 0 1 0 01 0 0 0 1 1 0 01 0 0 1 1 1 0 11 0 1 0 1 1 1 11 0 1 1 1 1 1 01 1 0 0 1 0 1 01 1 0 1 1 0 1 11 1 1 0 1 0 0 11 1 1 1 1 0 0 0

2) K-Map :- For G3

24


B1B0 B3B2 00 01 11 10 00

01 11 10

G3 = B3

For G2

B1B0 B3B2 00 01 11 10 00

01 11 10

G2 = B3B2 + B3 B2 = B3 B2 For G1

B1B0 B3B2 00 01 11 10 00

01 11 10

G1 = B2 B1 + B2 B1 = B2 B1

For G0

B1B0 B3B2 00 01 11 10 00

01 11 10

___ ___

0 0 0 00 0 0 01 1 1 11 1 1 1

0 0 0 01 1 1 10 0 0 01 1 1 1

0 0 1 11 1 0 01 1 0 00 0 1 1

0 1 0 10 1 0 10 1 0 10 1 0 1

25


G0 = B1 B0 + B1 B0

b) Convert 4 bit Gray code into Binary code. 3) Truth table.

Gray Inputs Binary OutputsG3 G2 G1 G0 B3 B2 B1 B00 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 1 0 0 1 00 0 1 0 0 0 1 10 1 1 0 0 1 0 00 1 1 1 0 1 0 10 1 0 1 0 1 1 00 1 0 0 0 1 1 11 1 0 0 1 0 0 01 1 0 1 1 0 0 11 1 1 1 1 0 1 01 1 1 0 1 0 1 11 0 1 0 1 1 0 01 0 1 1 1 1 0 11 0 0 1 1 1 1 01 0 0 0 1 1 1 1

4) K-Map: - For B3

G3G2 G1G0 00 01 11 10 00

01 11 10

B3 = G3

For B2

G3G2 G1G0 00 01 11 10 00

01 11 10

B2 = G3 G2 + G3 G2 = G3 G2

0 0 1 10 0 1 10 0 1 10 0 1 1

0 1 0 10 1 0 10 1 0 10 1 0 1

26


For B1

G3G2 G1G0 00 01 11 10 00

01 11 10

__ B1 = G1(G2 G3) + G1 G2 G3 + G1 G2 G3 For B0

G3G2 G1G0 00 01 11 10 00

01 11 10

B0 =

c) Convert BCD to Excess – 3 code. a. Truth table.

Decimal Digit

BCD Code Excess – 3 CodeB3 B2 B1 B0 E3 E2 E1 E0

0123456789

0000000011

0000111100

0011001100

0101010101

0000011111

0111100001

1001100110

1010101010

b. K-Map: - For E3

B3B2

0 1 0 10 1 0 11 0 1 01 0 1 0

0 1 0 11 0 1 00 1 0 11 0 1 0

27


B1B0 00 01 11 10 00

01 11 10

E3 = B3 + B2B0 + B2B1

For E2

B3B2 B1B0 00 01 11 10 00

01 11 10

E2 = B2B0 + B2B1 + B2B1B0

For E1

B3B2 B1B0 00 01 11 10 00

01 11 10

E1 = B1B0 + B1B0

For E0

B3B2 B1B0 00 01 11 10 00

01 11 10

E0 = B0

d) Convert Excess – 3 to BCD. c. Truth table.

Excess – 3 Code BCD Code

0 0 X 10 1 X 10 1 X X0 1 X X

0 1 X 01 0 X 11 0 X X1 0 X X

1 1 X 10 0 X 01 1 X X0 0 X X

1 1 X 10 0 X 00 0 X X1 1 X X

28


Decimal Digit

E3 E2 E1 E0 B3 B2 B1 B0

0123456789

0000011111

0111100001

1001100110

1010101010

0000000011

0000111100

0011001100

0101010101

d. K-Map: - For B3

E3E2 E1E0 00 01 11 10 00

01 11 10

B3 = E3E2 + E3E1E0

For B2

E3E2 E1E0 00 01 11 10 00

01 11 10

B2 = E2E1 + E2E1E0 +E3E1E0

For B1

E3E2 E1E0 00 01 11 10 00

01

X 0 1 0X 0 X 00 0 X 1X 0 X 0

0 1 X 01 0 X 11 0 X X1 0 X X

1 1 X 10 0 X 01 1 X X0 0 X X 29


11 10

B1 = E1E0 + E1E0

For B0

E3E2 E1E0 00 01 11 10 00

01 11 10

B0 = E0

Testing:

1. Make the connections as shown in Fig.2. Switch ON the supply and verify the truth table.

Conclusion:Code converters studied successfully.

EXPERIMENT No: 3

Title: Multiplexers: Applications like Realization of Boolean expression using Multiplexer.

1 1 X 10 0 X 00 0 X X1 1 X X

30


Aim :- Study of MUX.a) Verification of functionality of Mux IC.b) Realization of Boolean expression using Mux.

Theory :- Multiplexer is a combinational logic circuit with multiple input,

single output and select lines to select particular input and applied it at output. For N input mux M select inputs are required where N = 2M

Fig 3.1 N input Multiplexer Block diagram

When E (Enable ) input is active low. Depending upon digital code applied at the select inputs, one out of N data inputs is get selected at output. Enable input is also used for cascading of Mux.

31

N:1Mux

E

Select inputs

Y

Y

Io

I1

I2

In

8:1Mux

E

Y

Y

Io

I1

I2

I7


Fig 3.2 8:1 Multiplexer Block diagram

Truth Table

Select InputsEnable Y(output)S2 S1 S0

0 0 0 0 I00 0 1 0 I10 1 0 0 I20 1 1 0 I31 0 0 0 I41 0 1 0 I51 1 0 0 I61 1 1 0 I7

Types of Designing Boolean Expression using Mux:

1) LSB Method2) MSB Method

Circuit Diagram :- 4:1 Mux

32

S0 S1 S2LSB MSB

S1 S0 Enable

I0

I1

I2

I3

Y


Fig 3.3 4:1 Mux

A) According to truth table verify the IC 74151

B) Implement the following Boolean function using MUX. Use LSB Method1) Step I :- Designing Y(A,B,C,D)= ∑ m(1,3,4,11,12,13,14,15)

INPUT OUTPUT

33


A B C D YI/P OF MUX

0 0 0 0 0D0 0 0 1 1

0 0 1 0 0D0 0 1 1 1

0 1 0 0 1D0 1 0 1 0

0 1 1 0 000 1 1 1 0

1 0 0 0 001 0 0 1 0

1 0 1 0 0D1 0 1 1 1

1 1 0 0 111 1 0 1 1

1 1 1 0 111 1 1 1 1

Representation of input line in terms of variable D

Select InputsYS2 S1 S0

0 0 0 D0 0 1 D0 1 0 D0 1 1 01 0 0 01 0 1 D1 1 0 11 1 1 1

3) Step-IILogical Diagram :-

34

VCC GND

I0

I1

I2

I3 IC 74151

I4 8:1 MUX

I5

I6

I7

E S0 S1 S2

Y

Y


Fig 3.4 IC 74151 Pin Diagram

Testing:

1. Make the connection according to circuit diagram2. Connect Vcc & GND to IC. 3. verify the functionality of given function according to truth table.

Conclusion:Multiplexer applications successfully implemented.

EXPERIMENT No: 4

Title: Demultiplexers: Application like Realization of ROM using Demultiplexer.

35


Aim :- Study of DEMUX.c) Verification of functionality of DEMux IC.d) Realization of 4*4 ROM using Demux.

Theory :- Demultiplexer is a combinational logic circuit with sigle input, multiple outputs and select lines to select particular output and applied input at selected output. For N output demux M select inputs are required where N = 2M

Fig 4.1 N output Demultiplexer Block diagramWhen E (Enable ) input is active low. Depending upon digital code applied at the select inputs, one out of N data outputs is get selected and input data get applied at that output. Enable input is also used for cascading of Demux.

36

Select inputs

1 : 8Demux

E

Do

D1

D2

Dn

Data input

1 : 8Demux

E

S0 S1 S2

Do

D1

D2

D7

Data input


Fig 4.2 Block Diagram of 1 : 8 Demux

Function table :-For active low output :-

Select Inputs Enable OutputsS2 S1 S0 Y0 Y1 Y2 Y3 Y4 Y5 Y Y70 0 0 0 1 0 0 0 0 0 0 00 0 1 0 0 1 0 0 0 0 0 00 1 0 0 0 0 1 0 0 0 0 00 1 1 0 0 0 0 1 0 0 0 01 0 0 0 0 0 0 0 1 0 0 01 0 1 0 0 0 0 0 0 1 0 01 1 0 0 0 0 0 0 0 0 1 01 1 1 0 0 0 0 0 0 0 0 1

37

S1 S0 Enable

Data Input

Y0

Y1

Y2

Y3


Fig 4.3 Circuit Diagram of 1:4 Demux

Realization of 4*4 ROM using DEMUX

D0 (P, Q, R) = ∑ m (2, 3) D1 (P, Q, R) = ∑ m (1, 2) D2 (P, Q, R) = ∑ m (0, 2,3) D3 (P, Q, R) = ∑ m (1, 2, 3)

Select lines Data in bits DataS0 S1 S2 D0 D1 D2 D30 0 0 0 0 1 0 20 0 1 0 1 0 1 50 1 0 1 1 1 1 F

38


0 1 1 1 0 1 1 B

Fig 4.4 Logic Diagram for given function.

Testing:Verify the functiontable by connecting input and output according to pin

diagram.1) Realization of 4*4 ROM : Make the connection according to logic

diagram 2) Connect Vcc & GND connection 3) verify the output data shown in truth table.

39

VCC GND D0 D1

D2

1: 8 D3 Demux D4 D5

En1 D6

En2 D7

En3

D0

D1

D2

D2

Data line

Vcc

S0 S1 S2


Conclusion:Demultiplexer applications successfully studied.

EXPERIMENT No: 5

Title: Write BCD adder / subtractor using 4 bit binary adder 7483.

AIM: - Design and Implement 4 bit BCD Adder using IC 7483.

40


APPARATUS: - Digital Trainer kit. Connecting wires, IC 7483, 7408, 7432.

THEORY: BCD adder is combinational logic circuit, which performs the addition of two BCD digits and produces the sum in BCD forms. BCD is four-bit binary coded decimal number; BCD addition can be performed using the binary addition. The result of binary adder may be valid or invalid BCD. If result is invalid, BCD can be converted into valid BCD by adding 0110 to the result as shown below.

In this practical 4 bit binary adder is used as a BCD adder. So for valid BCD addition 3 cases are checked.

Case I :- Result is less than 9 and carry zero.Case II :- Result is less than 9 and carry is one.Case III :- Result is greater than 9 and carry is zero.

Example for above conditions :-

Case I :- Result is less than 9 and carry zero.

4 + 3 = 7 0 1 0 0 + 0 0 1 1 0 1 1 1 Result is valid

Case II :- Result is less than 9 and carry is one.

8 + 8 = 16 1 0 0 0 + 1 0 0 0 1 0 0 0 0 Result is invalid

41


To make invalid result valid add 6 in the result.

1 0 0 0 0 + 0 1 1 0

10 1 1 0 Valid result

Case III :- Result is greater than 9 and carry is zero.

8 + 5 = 13 1 0 0 0 + 0 1 0 1 1 1 0 1 Result is invalid To make invalid result valid add 6 in the result.

1 1 0 1 + 0 1 1 0

1 0 0 1 1 Valid result

Truth Table for detecting invalid result:-The result of addition is valid upto 9 because for 4 bit 1 to 9 is

valid range for BCD code. The result above 9 is invalid this invalid result is detected by generation of carry. So above 9 number upto 15 the carry output considered as 1 and below 9 it is 0 as shown in table below.

S3 S2 S1 S0 Y0 0 0 0 00 0 0 1 00 0 1 0 0o. 0 1 1 0

42


0 1 0 0 00 1 0 1 00 1 1 0 00 1 1 1 01 0 0 0 01 0 0 1 01 0 1 0 11 0 1 1 11 1 0 0 11 1 0 1 11 1 1 0 11 1 1 1 1

K- Map for carry out Y.

S1S0 00 01 11 10 S3 S2 00 01

11

10

Y = S1 S3 + S3 S2 S3 (S1 + S2)

Logical Diagram :-

00 0 0

0 0 0 0

1 1 1 1

0 0 1 1

43

B3 B2 B1 B0 A3 A2 A1 A0

4 Bit Binary Adder IC 7483 CinCout S3 S2 S1 S0

B3 B2 B1 B0 A3 A2 A1 A0

Cout 4 Bit Binary Adder IC 7483 Cin S3 S2 S1 S0

ignore Final valid Result unit’s digitTen’s Digit


Fig 5.1 4-Bit Binary adder using IC 7483

Testing:

1) Make connection as shown in fig.2) Check the output for 3 cases mentioned aboved.

44


Conclusion:BCD adder and subtractor successfully implemented.

EXPERIMENT No: 6

Title: Parity generator / detector.

45


Aim To study Parity Generator And checker and to Verify Even parity and odd parity

Apparatus : - Digital Trainer kit, Connecting wires, IC 74180

Theory :-Parity bit is an extra bit included with Binary information to detect the errors during transmission of binary information. In binary communication, extra bit is added in binary message such that total number of ones in the massage can be either odd or even. The combinational circuit, which generates the parity bit, is known as parity generator.At receiving end, a combinational circuit is used to check the parity of receiving information, and determines whether the error is included in the massage or not. This combinational circuit is known a parity checker.

IC 74180

IC 74180 is nine input parity generator / checker . It can used as a parity generator as well as parity checker. It has eight parity inputs A to H and two cascading inputs. It has two outputs, Even and Odd.

Fig 6.1 Logic symbol of IC 74180 is shown in fig.

Parity Inputs

Outputs

Cascading Inputs

The truth table of 74180 is given below

Parity Input

Cascading Inputs Outputs

Even Odd Even Odd

Even 1 0 1 0Odd 1 0 0 1

46

A

B C Σ Even

D

E IC

F 74180 G

H Σ Odd

Even


Even 0 1 0 1Odd 0 1 1 0

X 1 1 0 0

From the truth table of IC 74180, it is found that.

Parity input + Cascading inputs = OutputsEven + Even = EvenOdd + Odd = EvenOdd + Even = OddEven + Odd = Odd

It is important to note that when cascading inputs are logic ‘1’ , then outputs are logic ‘0; and when both cascading inputs are logic ‘0’,then output are logic 1.

Problem statement:Design a 9 bit even parity checker using IC 74180 and suitable gate

I

Fig 6.2 Problem: Design 9-Bit Odd parity generator using IC 74180

IC 74180 is a 9-bit parity generator. It has 8 parity inputs, two cascading inputs and two outputs. It generates parity bit according to the 8 inputs messages.The logic diagram of 9-bit parity generator is shown below:

47

A

B C Σ Even

D

E IC

F 74180 G

H Σ Odd

Even

A

B

C

D Σ Even

E

F

G Σ Odd

H

I

Logic 1


Fig 6.3 9-bit parity generator

Testing:

Make appropriate connections and check the output.

Conclusion:

Parity generation and detection successfully implemented.

EXPERIMENT No: 7

Title: To Study various types of Flip flops.

Aim :- Implementation of T and D flip-flop using M/S JK flip-flop

Apparatus : - Digital Trainer kit, Connecting wires, IC 7476, IC 7474, IC 7473.

48


Theory :- Fundamental building block of sequential circuits is flip-flop. Flip-flop is a 1-bit storage element. It is edge triggered device.

(a) +ve edge triggered (b) -ve edge triggered

Types of flip-flops:

SR Flip-Flop:

Fig 7.1 Symbol of SR F/F Fig 7.2 Internal Diagram

49

FLIP-FLOPS

AsynchronousOutput change as soon as input applied changes the state

SynchronousOutput change in synchronism with the clock pulses

1. SR FLIP-FLOP2. JK FLIP-FLOP3. M/S JK FLIP-FLOP4. T FLIP-FLOP 5. D FLIP-FLOP

Q

Q

Q

S

CLK

R

S Q

CLK

R Q

Pr

Cr


TRUTH TABLE OF SR FLIP-FLOP LIMITATION OF SR FLIP-FLOP:

In SR F/F, when S=R=1, the output Q and Q are

same.Logically it is not possible. Such state is

refered as forbidden state.

JK Flip-Flop:

Fig 7.3 Symbol of JK F/F Fig 7.4 Internal Diagram

S R Pr Cr QnX X 0 1 1X X 1 0 00 0 1 1 Qn0 1 1 1 01 0 1 1 11 1 1 1 ?

50

J Q

CLK

K Q

Pr

Cr

Q

Q

Q

J

CLK

K

Pr

Cr


TRUTH TABLE OF SR FLIP-FLOP LIMITATION OF JK FLIP-FLOP

In JK flip-flop when J=K=1, it acts as toggle switch,In presence of clock the output toggles and at the

end of clock we can not predict what will be Q and Q. this is called as race around condition.

Fig 7.5MS JK Flip-Flop:

Fig 7.6 Internal Diagram

J K Pr Cr Qn+1

X X 0 1 1X X 1 0 00 0 1 1 Qn

0 1 1 1 01 0 1 1 1

1 1 1 1 Qn

51

Pr

Q

Q

Q

J

CLK

K

Q

Q

Q

J

CLK

K

Cr

J Q

CLK

K Q

Pr

Cr

J Q

CLK

K Q

Pr

Cr


(B) Implementation of T and D flip-flop using M/S JK flip-flop

Implementation of T Flip-flop using MS JK F/F

The T flip-flop is obtained from JK flip-flop by shorting J & K inputs

Fig 7.7 Implementation of D Flip-flop using MS JK F/F

The D flip-flop is obtained from JK flip-flop by complementing the J & K inputs.

Fig 7.8 Block Diagram of D Flip Flop Procedure:

Make the connections according to pin diagram.

1. Apply the clock input.2. Apply different combinations of the inputs.3. Verify the truth table4. Build T and D flip-flops from the MS JK flip-flop.

Input

T

Output

Qn+1

0 Qn

1 Qn

Input

D

Output

Qn

0 01 1

52

Cr

J Q

CLK

K Q

PrT

J Q

CLK

K Q

Pr

Cr

D


Testing:

NA

Conclusion:Various types of Flip-flops successfully implemented.

53


EXPERIMENT No: 8

Title: Write an ALP in 8086 to multiply two numbers entered from Keyboard .

Relevant Theory:

Consider how we normally multiply numbers:123x 26449273802460032472Binary multiplication is similar. (Note that the product of two 4-bit numbers is potentially an 8-bit number).Multiplicand 1011Multiplier x 01100000 Note that each of these lines10110 here is either zero or just a101100 shifted venison of the0000000 multiplicand.Product 1000010

Note that in binary multiplication, the processes involves shifting the multiplicand, and addingthe shifted multiplicand or zero. Each bit of the multiplier determines whether a 0 is added or ashifter version of the multiplicand (0 implies zero added, 1 implies shifted multiplicand added).Thus, we can infer a basic shift-and-add algorithm to implement unsigned binary multiplication.

Fig 8.1 4Bit Mutiplier using Full adders /Rippel carry adders

54


Fig 8.2 8Bit Shift register

Testing:

NA

Conclusion:4-bit multiplication and division is studied.

55


EXPERIMENT No: 9

Title: Ripple counter using flip-flops.

Aim: To study the 3 bit asynchronous up/down counter using JK flip-flop

Apparatus: Digital Trainer Kit, IC 7476, IC 7408, IC 7432.

Theory:

In asynchronous counter commonly called ripple counter, the first flip-flop is clocked by the external clock pulse & then each successive flip-flop is clocked by the Q or /Q output the previous flip-flop. Therefore in an asynchronous counter the flip-flop are not clocked simultaneously. The input of MSJK is connected to VCC because when both inputs are one output is toggled. As MSJK is negative edge triggered at each high to low transition the next flip-flop is triggered. On this basis the design is done for MOD-8 counter.

Up Counter down Counter

Counter States

CountQA QB QC

0 0 0 01 0 0 12 0 1 03 0 1 14 1 0 05 1 0 16 1 1 07 1 1 1

Counter States

CountQA QB QC

7 1 1 16 1 1 05 1 0 14 1 0 03 0 1 12 0 1 01 0 0 10 0 0 0

56


Logic diagram:Fig 9.1 3 Bit Asynchronous Up Counter

Fig 9.2 3 Bit Asynchronous Down Counter

J Q

K Q

J Q

K Q

J Q

K Q

QC QB QA

QC QB Q A

J Q

K Q

J Q

K Q

J Q

K Q

57


Fig 9.3 3 Bit Asynchronous Up/Down Counter

Testing:

1. Make the connections as show In fig.2. Make connection for Asynchronous up counter..3. Make connection for Asynchronous down counter..4. Make connection for Asynchronous up/down counter..5. Verify the counter operation in different mode.

Conclusion:Ripple counter is successfully implemented.

58

QC QB QA

J Q

K Q

J Q

K Q

J Q

K Q


EXPERIMENT No: 10

Title: Sequence generator using JK flip-flop

Aim : Design & implement Sequence Generator using JK flip-flop

Apparatus : Digital Trainer Kit, IC 7476, IC 7432

Theory :- A Sequence Circuit, Which generates a prescribed sequence of bits in synchronism with a clock, is referred to as sequence generator. In synchronous or clocked flip-flops are used as memory elements, which change their individual states in synchronism with the periodic clock signal. Therefore, the change in states of flip-flops & change in states of the entire circuit occur at the transition of the clock signal.

Fig 10.1 Generalized Block diagram for sequence generator

Excitation table of JK flip-flop

Present state

Next state Jn Kn

0 0 0 X0 1 1 X1 0 X 11 1 X 0

Next state decoder

F F1

F F2

F Fn

59


Problem statement :- Design sequence generator to go through the following states by using J K flip-flop

Solution :- Excitation Table.

Present states Next state A B C

QA QB QC QA+1 QB+1 QC+1 JA KA JB KB JC KC

0 0 0 0 0 1 0 X 0 X 1 X0 0 1 0 1 1 0 X 1 X X 00 1 0 X X X X X X X X X0 1 1 1 0 0 1 X X 1 X 11 0 0 1 1 0 X 0 1 X 0 X1 0 1 X X X X X X X X X1 1 0 0 0 0 X 1 X 1 0 X1 1 1 X X X X X X X X X

K Map :-

For JA For KA

QBQC QBQC

QA 00 01 11 10 QA 00 01 11 10 0 0 0 1 X 0 X X X X 1 X X X X 1 0 X X 1

JA = QB KA = QB

For JB For KB QBQC QBQC

QA 00 01 11 10 QA 00 01 11 10 0 0 1 X X 0 X X 1 X 1 1 X X X 1 X X X 1 JB = QA+QC KB = 1

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0

16

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For JC For KC

QBQC QBQC

QA 00 01 11 10 QA 00 01 11 10 0 1 X X X 0 X 0 1 X 1 0 X X 0 1 X X X X

JC = QA KC = QB Fig 10.2 Connection Diagram:-

Testing:1) Design a logic circuit to generate given logic sequence.2) Connect circuits as per logic diagram 3) Apply clock inputs & verify logic sequence

Conclusion: Sequence generator is implemented successfully.

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J Q C

K Q

J Q B

K Q

J Q A

K Qvcc

QC QB QA

PR

CLR CLK


EXPERIMENT No: 11

Title: Up-down counter using JK flip-flop.

Aim : To study the 3 bit synchronous up/down counter using JK flip-flop

Apparatus: Digital Trainer Kit, IC 7476, IC 7408, IC 7432.

Theory : In synchronous counter, the clock pulse is given simultaneously to all the flip-flops. Transition occurs at output with synchronous of clock inputs.

The Basic idea of construction is to keep the J&K inputs, of each flip-flop high, such that the flip-flop will toggle with any clock negative going at its clock input. The clock is applied directly to flip-flop A. Since the JK flip-flop used responds to a negative transition at the clock inputs & toggles when both the J&K input are high. Whenever A is high And gate is enabled & clock pulse is passed through the gate to the next stage B. For the 3-bit synchronous counter we used 3 flip-flop stages.

UP COUNTER :- In the count-up mode, B is the required to change state each time A is high & clk goes low. Whenever count-up line & A are both high, the output of gate is X1 is high. Whenever either input Z1 is high, the output is high. Therefore the J&K inputs to flip-flop B are high whenever both count-up modes a clock negative going will toggle B, Each time A is high. Thus UP-COUNTING operation is done

DOWN COUNTER :- In the count down mode B must change state each time A is high & the clock goes low . the output of gate Y1 is high & thus the J & k inputs to flip-flop B are high. Whenever A & count-down are high. Thus in the count down mode, B changes state every time A is high & the clock goes low 7 to 0

Problem Statement: - The 3-bit binary Up/Down synchronous counter with a direction control M. Use J-K Flip-flop.

Excitation Table :- The designing is given in excitation table. For M = 0, it acts as an Up counter and for M =1 as an Down counter. The number of flip-flops required is 3. The inputs of flip-flops are determined by using excitation table.

Present State Next State J K0 0 0 X0 1 1 X1 0 X 11 1 X 0

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Control input M

Present State Next State Input for Flip-flopQC QB QA QC+1 QB+1 QA+1 JC KC JB KB JA KA

0 0 0 0 0 0 1 0 X 0 X 1 X0 0 0 1 0 1 0 0 X 1 X X 10 0 1 0 0 1 1 0 X X 0 1 X0 0 1 1 1 0 0 1 X X 1 X 10 1 0 0 1 0 1 X 0 0 X 1 X0 1 0 1 1 1 0 X 0 1 X X 10 1 1 0 1 1 1 X 0 X 0 1 X0 1 1 1 0 0 0 X 1 X 1 X 11 1 1 1 1 1 0 X 0 1 X 1 X1 1 1 0 1 0 1 X 0 X 0 X 11 1 0 1 1 0 0 X 0 X 1 1 X1 1 0 0 0 1 1 X 1 0 X X 11 0 1 1 0 1 0 0 X 1 X 1 X1 0 1 0 0 0 1 0 X X 0 X 11 0 0 1 0 0 0 0 X X 1 1 X1 0 0 0 1 1 1 1 X 1 X X 1

K MAP- JA

QBQA MQC 00 01 11 10 00

01 11

10 JA = 1JA

QBQA MQC 00 01 11 10 00

01 11

10 KA = 1

1 X X 1

1 X X 1

1 X X 1

1 X X 1

X 1 1 X

X 1 1 X

X 1 1 X

X 1 1 X

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JB QBQA MQC 00 01 11 10 00

01 11

10 JB = M QA + M QA

KB QBQA MQC 00 01 11 10 00

01 11

10 JB = M QA + M QA

JC QBQA MQC 00 01 11 10 00

01 11

10 JB = M QA QB + M QA QBKC

QBQA MQC 00 01 11 10 00

0 1 X X

0 1 X X

1 X 0 X

1 X 0 X

X X 1 0

X X 1 0

X 0 X 1

X 0 X 1

0 0 1 0

X X X X

X X X X

1 0 0 0

X X X X

0 0 1 0

1 0 0 0

X X X X64


01 11

10 JB = M QA QB + M QA QB

Fig 11.1 Logical Diagram of Up down counter using JK Flip Flop

Testing:

1) Connect the circuit as shown 2) Connect DC power supply & provide clock signal 3) Connect Up select line to logic high to verify the truth table of up counter4) counter down select line to logic high to verify the troth table of down counter

Conclusion:Up and down counters are successfully implemented.

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J Q

AK Q

J Q

BK Q

J Q

CK Q

M PR

CLR M

CLK

VCC

QA QB QC


EXPERIMENT No: 12

Title: Modulo N counter using 7490 & 74190 (N>10).

Aim :- To study Decade Binary Counter IC 7490A) Design Mod 6 using 7490 CounterB) Design Mod 20 using 7490 Counter

Apparatus :- Digital Trainer Kit, IC7490, Connecting wires.

Theory :- IC 7490 is a decade binary counter . It consist of Four master slave flip-flops & additional gating to provide a divide by two counter & a three stage binary counter for Which the count cycle length is divide by five .

Since the output from the divide by two sections is not internally connected to the succeeding stage, for counting further up to 10 states connect the MOD 2 output to the input of MOD 5counter.

In fig 2 flip-flops (FFA) operates as a mod 2 counter where as the combination flip-flop i.e. FFB, FFC, FFD Form Counter. There are two RESET i/p i.e. R0, R1 & two SET inputs S0, S1.

Fig 12.1 Internal Diagram of IC 7490

Reset Input Output

Fff1fff

R(0) R(1) S(0) S(1)

Clk A

Clk B

MOD - 5MOD – 2

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LSB QA QB QC QD MSB

Vcc

GND


Ro(1) Ro(2) Rg(1) Rg(2) QD QC QB QA

H H L X L L L LH H X L L L L LX X H H H L L HX L X L COUNTL X L X COUNTL X X L COUNTX L L X COUNT

Design Statement: Design MOD 6 counter using IC 7490.Theoretical Method :-

Truth table of MOD 6 Counter

K- MAP for Reset input:-

QBQA QDQC 00 01 11 10 00

01 11

10

Reset = QD + (QC QB)

Clock count states QD QC QB QA Reset input

0 0 0 0 0 01 0 0 0 1 02 0 0 1 0 03 0 0 1 1 04 0 1 0 0 05 0 1 0 1 06 0 1 1 0 17 0 1 1 1 18 1 0 0 0 19 1 0 0 1 1

0 0 0 0

0 0 1 1

X X X X

1 1 X X

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Fig 12.2 Logical Diagram for MOD – 6 counter

Design Statement : Design MOD 20 counter using IC 7490 Logical Method :-

MOD 20 COUNTER: - We know that One IC can work as mod-10 BCD counter. Therefore we need two ICs. The counter will go through 0-19 & should be reset on state 20 i.e.

QD QC QB QA QD QC QB QA 0 0 1 0 0 0 0 0

7490(1) 7490(2)The diagram of divide by 20 counters using IC 7490 is shown in fig.

Fig 12.3 divide by 20 counters using IC 7490

5 Vcc 10 GND S(1) S(2)

IC 7490

Ro(2)

QA QB QC QD Ro(1)

Clk A

Clk B

S0 S1 R0 R1A IC7490(1)B QA QB QC QD

S0 S1 R0 R1

A IC7490(2)B QA QB QC QD

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Testing:

1) Firstly check the regular decade binary counting operation for MOD-2 by connecting external clock to clock A .

2) Then check MOD-5 by connecting external clock to clock B. 3) Make the connection for MOD-6 counter as shown in diagram & verify the truth table 4) Make the connection for MOD-20 counter as shown in diagram &

verify the operation.

Conclusion: Mod-N counter is successfully implemented.

EXPERIMENT No: 13

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Title: Pseudo random number generator using 74194

Aim :- To study pseudo random number generator using IC 74194.

Equipment :- Logic board with IC sockets & LEDs ,IC74194, IC 7486.

Theory :- IC 74194 : Universal Shift Register

We know that a register may operate in any of the mode .like SISO,PISO,PIPO, or Bi-directional.

IC 74194 has 4 parallel data i/p’s (D0-D3) & S0 & S1 are the control i/p’s. When S0 & S1 are high, data appearing on D0-D3 i/p’s is transferred to the Q0-Q3 o/ps respectively. Following the next low to high transition of the clock shift right is accomplished by setting S1 S0 = 0 1., & serial data is entered at the shift right serial i/p DSR. Shift Left is accomplished by setting S1 S0 = 1 0, & serial data is entered at the shift left serial i/p ,DSL. CP(clock pulse) is Positive edge triggered.

Pseudo Random Number Generator Using IC 74194Another important application of a shift register is the pseudo random generator .it is used for the generating the random sequences. The PBRS generator consists of a flip flop & a combinational circuit for providing a suitable feedback.

Operation Mode

I/P'S O/P'S

CP /MR S1 S0 DSR DSL Dn Q0 Q1 Q2 Q3

Reset(clear) X 0 X X X X X 0 0 0 0

Shift Left

1 1 0 X 0 X Q1 Q2 Q3 0

1 1 0 X 1 X Q1 Q2 Q3 1

Shift Right

1 0 1 0 X X 0 Q0 Q1 Q2

1 0 1 1 X X 1 Q0 Q1 Q2

Parallel Load 1 1 1 X X Dn D0 D1 D2 D3

Hold X 1 0 0 X X X Q0 Q1 Q2 Q3

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Q3 Q2 Q1 Q0 = 0 0 1 1.Clock Pulse Number Shift Register EX-OR Gate PBRS Sequence

Q3 Q2 Q1 Q0 Q3 Q2 Q3

0 0 0 1 1 000 0

1 0 1 1 0 0 0

2 1 1 0 1 0 1

3 1 0 1 0 0 1

4 0 1 0 1 0 0

5 1 0 1 1 00 1

6 0 1 1 1 0 0

7 1 1 1 1 0 1

8 1 1 1 0 0 1

9 1 1 0 0 0 1

10 1 0 0 0 0 1

11 0 0 0 1 000 0

12 0 0 1 0 000 0

13 0 1 0 0 0 0

14 1 0 0 1 0 1

15 0 0 1 1 000 0

16 0 1 1 0 0 0

17 1 1 0 1 0 1

The PBRS generator cannot generate a truly random sequence because this structure is a deterministic structure. This is reason why the sequence repeats itself.The maximum length of sequence will be 2 m-1. This is because the state 0 0 0 . . . . . .0 must be excluded.

Binary sequence of Q3.

Length of PBRS :- 2m-1

For m = 4 :- 24-1 =15.PBRS sequence repeats itself after every 15 clock pulse. The logical diagram for the above designing is as given below.

Fig 13.1 Logical Diagram of 74194 As a PBRS Generator PBRS Sequence

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0 0 1 1 0 1 0 1 1 1 1 0 0 0


5VVCC Q0 Q1 Q2 Q3 CP S1 S0

MR DSR D0 D1 D2 D3 DSL GND

Application of PBRS. Since the sequence produced is random, PBRS generator is also called as Pseudo

Noise Generator. This noise can be used to test the noise immunity of the system under test.

PBRS Generator is an important part of data encryption system. Such a system is required to protect the data from data hackers.

Testing:

1) Adjust data o/p of Q3 Q2 Q1 Q0 = 0 0 1 1. using parallel load operation mode.2) Connect EX-OR gate o/p to DSR pin of IC 74194 & i/p for EX-OR is Q2 & Q3.3) Apply clock pulse to pin 11 of IC 74194 & check PRB sequence at Q3 o/p pin –12 of IC 74194.

Conclusion: Pseudo random generator successfully implemented.

EXPERIMENT No: 14

Title: Implementation of combinational logic using PALs

Relevant Theory:

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16 15 14 13 12 11 10 9

IC 74194

1 2 3 4 5 6 7 8


The term Programmable Array Logic (PAL) is used to describe a family of programmable logic device semiconductors used to implement logic functions in digital circuits introduced by Monolithic Memories, Inc. (MMI) in mid 1978.

PAL devices consisted of a small PROM (programmable read-only memory) core and additional output logic used to implement particular desired logic functions with few components.

Using specialized machines, PAL devices were "field-programmable". Each PAL device was "one-time programmable" (OTP), meaning that it could not be updated and reused after its initial programming. (MMI also offered a similar family called HAL, or "hard array logic", which were like PAL devices except that they were mask-programmed at the factory.)

Fig 14.1 PAL Architecture

PAL architecture

The programmable elements (shown as a fuse) connect both the true and complemented inputs to the AND gates. These AND gates, also known as product terms, are ORed together to form a sum-of-products logic array.

The PAL architecture consists of two main components: a logic plane and output logic macrocells.

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http://en.wikipedia.org/wiki/Image:Programmable_Logic_Device.jpg

http://en.wikipedia.org/wiki/Image:Programmable_Logic_Device.jpg


Programmable logic plane

The programmable logic plane is a programmable read-only memory (PROM) array that allows the signals present on the devices pins (or the logical complements of those signals) to be routed to an output logic macrocell.

PAL devices have arrays of transistor cells arranged in a "fixed-OR, programmable-AND" plane used to implement "sum-of-products" binary logic equations for each of the outputs in terms of the inputs and either synchronous or asynchronous feedback from the outputs.

Output logic

The early 20-pin PALs had 10 inputs and 8 outputs. The outputs were active low and could be registered or combinational. Members of the PAL family were available with various output structures called "output logic macrocells" orOLMCs. Prior to the introduction of the "V" (for "variable") series, the types of OLMCs available in each PAL were fixed at the time of manufacture. (The PAL16L8 had 8 combinational outputs and the PAL16R8 had 8 registered outputs. The PAL16R6 had 6 registered and 2 combinational while the PAL16R4 had 4 of each.) Each output could have up to 8 product terms (effectively AND gates), however the combinational outputs used one of the terms to control a bidirectional output buffer. There were other combinations that have fewer outputs with more product term per output and were available with active high outputs. The 16X8 family or registered devices had an XOR gate before the register. There were also similar 24-pin versions of these PALs.

AMD 22V10 Output Macrocell

This fixed output structure often frustrated designers attempting to optimize the utility of PAL devices because output structures of different types were often required by their applications. (For example, one could not get 5 registered outputs with 3 active high combinational outputs.) So, in 1983 AMD (source needed) introduced the 22V10, a 24 pin device with 10 output logic macrocells. Each macrocell could be configured by the user to be combinational or registered, active high or active low. The number of product term allocated to an output varied from 8 to 16. This one device could replace all of the

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http://en.wikipedia.org/w/index.php?title=OLMC&action=edit

http://en.wikipedia.org/w/index.php?title=Output_logic_macrocell&action=edit

http://en.wikipedia.org/w/index.php?title=Sum-of-products&action=edit

http://en.wikipedia.org/wiki/Image:AMD_22V10_Macrocell.jpg

http://en.wikipedia.org/wiki/Image:AMD_22V10_Macrocell.jpg


24 pin fixed function PAL devices. Members of the PAL "V" ("variable") series included the PAL16V8, PAL20V8 and PAL22V10.

PAL 16R4 Block Diagram

AMD 22V10 Block Diagram

Testing:

Build 2-bit counter using PAL.

Conclusion:

PAL is used to successfully implement the counter.

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http://en.wikipedia.org/wiki/Image:PAL_Block_Diagram.jpg

http://en.wikipedia.org/wiki/Image:22V10_Block_Diagram.jpg


EXPERIMENT No: 15

Title: Pspice modeling

Relevant Theory:

PSpice is a SPICE analog circuit simulation software that runs on personal computers, hence the first letter "P" in its name. It was developed by MicroSim and used in electronic design automation. MicroSim was bought by OrCAD and now belongs to Cadence Design Systems.

PSpice is the first version of UC Berlekey SPICE available on a PC, having been released in January 1984 to run on the original IBM PC. This initial version ran from two 360KB floppy disks and later included a very capable waveform viewer and analyser program - Probe. Subsequent versions improved in performance and moved to DEC/VAX minicomputers, Sun workstations, the Apple Macintosh, and the Microsoft Windows platform.

PSPICE Help:

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Design Analysis/ Implementation Logic:

Sample Codes:

* Resistive Circuit

R1 1 2 5OhmR2 2 3 10OhmR3 2 0 20Vapp 1 0 5VIapp 0 3 1

.options numdgt=8

.op*.probe.end

* Function Generators and Phase measurements

R1 1 2 1250C 2 0 0.22uvi 1 0 sin(0 2 500 0 0 0)

.tran .01ms 5ms 0ms 0.01ms

.probe

.end

* Spice As A Curve Tracer* Plot of iC versus Vce

vCE 1 0 DC 0ViB 0 2 DC 1u

* Note the current direction. The current is* injected into the base for an NPN transistor.* The base node is numbered as 2.

* Q<name> means a bipolar junction transistor (BJT)

Q1 1 2 0 my_npn_tran* | | | * | | | * Collector | |* Base |* Emitter

.model my_npn_tran npn(Is=1.8104e-15 bf=100 Vaf=35)

* Note: Is is the scale current, bf is the beta* (the common-emitter-current gain).

* Vaf is the Early voltage. Run pSpice twice, first with Vaf=35* and a second time after deleteing Vaf=35 from the model * parameter. Vaf then assumes the default value of infinity.

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* Study the difference.

* Vary the Vce from 0 to 10.* Draw 10 curves -- each for a fixed value of the base* current iB. The lowest curve is for 1uA and the highest* curve is for 10uA and the increament is 1uA.

.dc vCE 0 10 0.1 iB 1u 10u 1u

* When you use probe, add the trace of IC(Q1) to view the * output characteristics. You may want to change the Y-axis* Setting (look under Plot menu) from 0 to 1.5mA (click on User * Defined).

.probe

.end

Testing:Test the transistor characteristics curve given above. Design a CMOS inverter and check the output.

Conclusion:

Pspice is used to probe into the digital circuits successfully.

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Sonali Manual_2nd August 2007

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