SOI SPECIFIC ANALOG TECHNIQUESFOR LOW-NOISE, HIGH-TEMPERATURE

OR ULTRA-LOW POWER CIRCUITS

Promoteurs: Prof. J.-P. ColingeProf. D. Flandre

Jury: Dr. J.-P. EggermontProf. A. KaiserProf. P. Sobieski (président)Prof. M. Verleysen

Vincent Dessard

II) SOI n-MOSFETs low-frequency noise study

III) Fully differential preamplifier for instrumentation

SOI SPECIFIC ANALOG TECHNIQUES FOR LOW-NOISE, HIGH-TEMPERATURE OR ULTRA-LOW POWER CIRCUITS

I) A new class of ultra-low power (ULP) analog basic blocks

Content of the thesis:

A new class of ULP analog basic blocks

Introduction- SOI vs. Bulk technology- Why ULP ?- How to achieve ULP ?

Main- New ULP principle & technological considerations- 3 ULP basic blocks and their applications

Conclusions

Outline of presentation:

SOI vs. Bulk technology

SOI vs. Bulk technology:

Vin VoutCMOS Inverter case

Vin

0VVout

P-substrate

N+N+

5V

P+P+

N-Well

Well leakagecurrent

Drain leakagecurrent

Vin

0VVout

P-substrate

N+N+

5V

P+P+

N-Well

Well leakagecurrent

Drain leakagecurrent

Vin

0VVout

P-substrate

N+N+

5V

P+P+

N-Well

Bulk

Drain leakagecurrent

Well leakagecurrent

N+ N+ P+ P+

0V 5VVout

Vin

Buried oxide

P-substrate

N+ N+ P+ P+

0V 5VVout

Vin

Buried oxide

P-substrate

N+ N+ P+ P+

0V 5VVout

Vin

Buried oxide

P-substrateSOI

N+ N+P2P+ P+P1

Standard UCL FD-SOI process

Why ULP ?

Why ULP ?

How to achieve ULP ?

How ?(can’t obtain such current with resistor !)

Use of self biased multi-thresholdvoltage CMOSFET basic cells

How to achieve ULP ?

ULP ? P=U.I

Dynamic range constraints

Difficult to U

I (pA…nA…)

New ULP principle & technological considerations

More Vth without process change ? …

ID [A] logscale

Vgs [V]-2 -1.5 -1 -0.5 0 0.5 1

10-5

10-6

10-7

10-10

10-9

10-8

10-11

10-12

N+ N+P2

P+ P+P1

NP2N

Standard UCL SOI CMOSFETs Id-Vgs characteristics (Vbs=0V, 20°C, Vds=1V, W/L=1/3)

PP1P

Vth PP1PVth NP2N

N+ N+P1 P+ P+P2

N+ N+P1+P2 P+ P+P1+P2

N+ N+I P+ P+I

NP1N PP2P

NP12N PP12P

NIN PIP

(NNN) (PNP)(intrinsic)

Idea: Permute/Add/Remove channel doping by intelligent use of existing masks.

N+ N+P2 P+ P+P1NP2N(Standard)

n-MOSFET p-MOSFET

PP1P(Standard)

More Vth without process change ? …

ID [A] logscale

Vgs [V]-2 -1.5 -1 -0.5 0 0.5 1

10-5

10-6

10-7

10-10

10-9

10-8

10-11

10-12

PNP

PIP

PP1P

PP2P

NNN NIN

NP1NNP2N

NP12N

PP12P

Use of self biased multi-thresholdvoltage CMOSFET basic cells

3 ULP basic blocks and their applications

Self biased

Basic cell architecture (#1) :

n- & p-MOS have:-same VGS and VBS

-same I

ID [A] logscale

Vgs [V]

-2 -1.5 -1 -0.5 0 0.5 1

10-5

10-6

10-7

10-10

10-9

10-8

10-11

10-12

PIP

NIN

ID [A] logscale

Vgs [V]

-2 -1.5 -1 -0.5 0 0.5 1-2 -1.5 -1 -0.5 0 0.5 1

10-5

10-6

10-7

10-10

10-9

10-8

10-11

10-12

10-5

10-6

10-7

10-10

10-9

10-8

10-11

10-12

PIP

NIN

20°C

VG0

T° dependence: UCL FD-SOI intrinsic n & p-MOSFETsDrain current [A] (logscale)

Gate voltage [V]

PIP NIN

VG0 weakly sensitive to T° !

Ibias exponentially with T°

VSVG

VDn

VDp

NIN

PIP

VSVG

VDn

VDp

NIN

PIP

0.466

0.468

0.47

0.472

0.474

0.476

0.478

50 100 150 200 250 300

Vref = Vout

T [°C]

[V]

0.466

0.468

0.47

0.472

0.474

0.476

0.478

0.480

50 100 150 200 250 300

Vref = Vout (VG=0V)

T [°C]

[V]

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07Consumption [A]

Max. sensitivity 200ppm/°C

Application: voltage reference/ level shifter

VS1

Vdd

NIN (20/20)

PIP (20/20)

VS2

Vdd

NP1N (20/20)

PP1P (20/20)

Comparison with a standard voltage reference generatorbased on a bandgap cell[*].

[*]: Hiten’99, S.Adriaensen

0.385mm²0.002mm²Active chip area

100ppm/°C200ppm/°COutput drift

3V ±160mV0.47V (NIN-PIP)Output voltage

200µA1p…20nA (300°C)Current consumpt.

4...5V>0.6VVdd-Vss

25…300°C25…300°COperating T°

BandgapULP volt. ref

0.385mm²0.002mm²Active chip area

100ppm/°C200ppm/°COutput drift

3V ±160mV0.47V (NIN-PIP)Output voltage

200µA1p…20nA (300°C)Current consumpt.

4...5V>0.6VVdd-Vss

25…300°C25…300°COperating T°

BandgapULP volt. ref [*]

die

Generalized basic cell (#2): (differential CMOS transconductance)

T

GpGn

nU

VV

S eI 2.

VGn

VGp

VSV S

I0

V S

T

NP

nU

VVD

e

I

1

VN VP

T

NP

nU

VVD

e

I

1

VG0

2GnGp

CM

VVV

V G p = V C M V G n = V C M

V G ( V B = V S = 0 V )

L o g ( I D )

2GnGp

CM

VVV

V G p = V C M V G n = V C M

V G ( V B = V S = 0 V )

L o g ( I D )VGp<VCM VGn>VCMVGp<VCM VGn>VCM

VGp>VCM VGn<VCMVGp>VCM VGn<VCM

Application: OTA

IBias

gm

Design constraints:

L

bias

TT C

I

nUf

2

1(… few Hz … & T° dependent)fT:

20 2

11

2

1MEA

TV V

nUA

DC gain: (… 40dB …)

I n t e g r a t e d l o w - f r e q u e n c y f i l t e r c h a l l e n g e :

C m a x 1 0 p F

C

gmf C 2

1 H z 03.060 DI

VpAgm

I D 2 p A

I n t e g r a t e d l o w - f r e q u e n c y f i l t e r c h a l l e n g e :

C m a x 1 0 p F

C

gmf C 2

1 H z 03.060 DI

VpAgm

I D 2 p A

Application: Low-frequency gm-C filter (biomedical).

-

+ -

+

Vref

Vin

Vout

BP, 1Hz:

Noisy VDD1.5V

VDD’1.34V

Vin Vout

P1

P2

P2

P2P2

P2

P2

P2

I

I

I

I

I

I

10pF

1.25pF

Noisy VDD1.5V

VDD’1.34V

Vin Vout

P1

P2

P2

P2P2

P2

P2

P2

I

I

I

I

I

I

10pF

1.25pF

1.5pA

-80

-60

-40

-20

0

0.01 0.1 1 10 100 1k 10k 100k-80

-60

-40

-20

0

0.01 0.1 1 10 100 1k 10k 100kf

][dBV

V

in

out

1Hz

Simulation

Comparison with a standard gm-C 6th order 2.4Hz LP filter[*]

[*]: IEEE Trans. On Circuits & Systems-II. Dec. 2000, p1391

LP[*]ULP BP

~1mm²~0.1mm²Active area

3V1.5V…Vdd-Vss

10µW~10pWPow. Consumpt.

-65dB<<-60dBPSRR

<-60dB/HD3@Vin=0.1V

~50µV~50µVIntegr. Noise

2.4 Hz…few Hz…Bandwidth

62Filter order

LP[*]ULP BP

~1mm²~0.1mm²Active area

3V1.5V…Vdd-Vss

10µW~10pWPow. Consumpt.

-65dB<<-60dBPSRR

<-60dB/HD3@Vin=0.1V

~50µV~50µVIntegr. Noise

2.4 Hz…few Hz…Bandwidth

62Filter orderNumber of poles

Basic cell (#3): ULP Diode

VD

ID

Standard MOS diode

PN junction diode

IS

Solution:ULP diode

…

« MOS » leakage

« MOS-Diode » leakage

Log(ID)

VDS

VDS= VGS

VGS

VD>VDsat

VGS

SDDS

VGS=0

« MOS » leakage

« MOS-Diode » leakage

Log(ID)

VDS

VDS= VGS

VGS

VD>VDsat

VGS

VD>VDsat

VGS

SDDS

VGS=0

DS

VGS=0Problem: Large reverse leakage current for low Vth !

IS

Basic cell (#3): ULP Diode

Basic cell (#2)

VS

VGn

VDn

VDp

VGp

VS

VGn

VDn

VDp

VGp

VS

VGn

VDn

VDp

VGp

junction diode

‘IS’ definition:

ISp

ISn

Log|ID| [A]

IS=10-10

IS=10-11

IS=10-12

IS=10-13

Standard MOS diode

IS

VD

VD [V]

ID

Log|ID| [A]

ISn=10-10

I Sp=10-7

I Sp=10-10

I Sp=10-13

ULP MOS diode

ISpISnISpISn

VD

VD [V]

ID

Basic cell (#3): ULP diode measurements

Linear scale

Application: memory cell (SRAM, flip-flop)

Standard SRAM principle:

Application: memory cell (SRAM, flip-flop)

VDD

Word line

C

D1

D2

Vram

ID2

ID1

ID1-ID2

VDD

Vram[V]

ID1-ID2 [A]

5

0 1 2 3 4

k

k

VDD

2VDD

Vram[V]

ID1-ID2 [A]

5

0 1 2 3 4

k

k

VDD

2VDD

2

ISn=10-6A

ISp=ISn.10k

T=300K

w.i. modelISn=10-6A

ISp=ISn.10k

T=300K

w.i. modelISn=10-6A

ISp=ISn.10k

T=300K

w.i. model

VDD/4

VDD/4

Application: SRAM

Static consumption over T°:

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

-1 -0.5 0 0.5 1 1.5

Vin

Id [A] logscale

100°C150°C

200°C

250°C

25°C

Vin

VDD

ID

Ileak

Reverse ULP diodeV’in > 0

Id

-V’in /2

Ileak

Inverter

0

VDD

ID0V

1 Mb SRAM

10

10

10

10

10

-3

-2

-1

0

1

Stan

dby

Pow

er (W

) @

5 V

3503002502001501005010

10

10

10

10

-2

-1

0

1

2

Temperature (°C)

Sta

ndb

y C

urr

ent (

mA

)

Bulk PD SOI

FD SOI ?

(64kbits SRAM)

[Honeywell, 3rd High Temperature Electronics Conf., June 96, p.XI-3][Honeywell, 3rd High Temperature Electronics Conf., June 96, p.XI-3]

Applications: SRAM

Static consumption over T°:

ULP FD SOI ?

Basic blocks summary

Basic blocks and applications summary:

VSVG

VDn

VDp

-voltage reference -current source (fct T°)

(#1)

- OTA- low frequency filter

VS

VGn

VGp

- differential gm- rail-to-rail OTA

(#2)

- comparator (hysteresis)

VK

VA

- charge pump- memory cell

(#3)

- More complete experimental circuits validation.

Future researches…

- New applications (not only for ULP !): oscillator, DTMOS, ESD, charge pump (Rload), low level battery detector, …

Conclusions

Conclusions:

- An original concept of ULP basic blocks has been presented. (patent pending)

- Very efficient for low-frequency fixed temperature applications (biomedical).

- Use of standard SOI process (only optimal use of masks).

- Still working at high temperature.

Few pW at 20°C !!!

- Most basic analog functions can be implemented:-voltage reference-OTA-filter-memory cell (SRAM, …)-charge pump-comparator-…

- High temperature SRAM with low static consumption can be expected.