Software-defined Radio using Software-defined Radio using XilinxXilinx

Anton S. Rodriguez, Michael C. Mensinger, Jr.Anton S. Rodriguez, Michael C. Mensinger, Jr.

Advisors:Advisors:Dr. In Soo Ahn and Dr. Yufeng LuDr. In Soo Ahn and Dr. Yufeng Lu

Department of Electrical and Computer EngineeringDepartment of Electrical and Computer EngineeringBradley University, Peoria IL 61625Bradley University, Peoria IL 61625

OutlineOutline MotivationMotivation Project GoalsProject Goals EquipmentEquipment QPSK TheoryQPSK Theory BackgroundBackground

System Block DiagramSystem Block Diagram RequirementsRequirements ResultsResults ConclusionsConclusions ReferencesReferences

MotivationMotivation A Software-defined Radio A Software-defined Radio

(SDR) provides a versatile (SDR) provides a versatile wireless communication wireless communication solution for a wide range solution for a wide range of applications.of applications.

Applications:Applications:• Cell phonesCell phones• Military radiosMilitary radios• GPSGPS• Wi-FiWi-Fi

The SDR can be easily The SDR can be easily modified to the operating modified to the operating needs of individual needs of individual applications.applications.

Lower costsLower costs• No expensive No expensive

equipmentequipment• No need to replace No need to replace

hardwarehardware

Project OverviewProject Overview The objective of this The objective of this

project is to design a project is to design a communication radio communication radio system on an FPGA board. system on an FPGA board.

QPSK modulation scheme QPSK modulation scheme is used.is used.

The main focus is on the The main focus is on the carrier synchronization carrier synchronization and phase ambiguity and phase ambiguity correction from the correction from the received data.received data.

A Simulink model of the A Simulink model of the entire system is designed entire system is designed and then implemented on and then implemented on the SignalWave Virtex-II the SignalWave Virtex-II FPGA board .FPGA board .

Project GoalsProject Goals Gain an in-depth Gain an in-depth

understanding about the understanding about the FPGA implementation of FPGA implementation of carrier synchronization.carrier synchronization.

Achieve fast acquisition of Achieve fast acquisition of carrier synchronization.carrier synchronization.

Construct a working Construct a working Simulink model.Simulink model.

Implement the Simulink Implement the Simulink model on an FPGA board.model on an FPGA board.

Correct the phase Correct the phase ambiguity present in the ambiguity present in the recovered data.recovered data.

EquipmentEquipment Virtex 4 FPGAVirtex 4 FPGA

Xilinx - ISE 9.2 CompilerXilinx - ISE 9.2 Compiler

SignalWave Virtex-II SignalWave Virtex-II

FPGAFPGA

QPSKQPSK SignalSignal RepresentationRepresentation

2 bits2 bits

s(t) = I(t)*cos(2s(t) = I(t)*cos(2ππffoot) – Q(t)*sin(2t) – Q(t)*sin(2 π πffoot)t)

= A*cos(2= A*cos(2ππffoot + t + θθ(t)) (t))

I

Q

θ(t) I(t) Q(t)

π/4 1 1

3π/4 -1 1

5π/4 -1 -1

7π/4 1 -1

BackgroundBackground Previous QPSK ProjectPrevious QPSK Project

Objectives:Objectives:• Make this system wirelessMake this system wireless• Overcome the following communication problems:Overcome the following communication problems:

Multi-path effectMulti-path effect Carrier synchronizationCarrier synchronization Phase ambiguityPhase ambiguity

Wired Channel

Digital Data(Receiver)

Digital Data(Transmitter)

Multi-pathMulti-path EffectEffect Random process.

A number of different paths may be traveled.

Constructive/destructive interference.

A B

α1*x(t-τ1)

α2*x(t-τ2)

α3*x(t-τ3)

Carrier SynchronizationCarrier Synchronization Wireless communication introduces distortion due to Wireless communication introduces distortion due to

channel imperfections.channel imperfections.

The carrier signals must be synchronized to decode data The carrier signals must be synchronized to decode data correctly correctly

for both I & Q channels.for both I & Q channels.

Phase AmbiguityPhase Ambiguity Typical problem in QPSK Typical problem in QPSK

systems.systems.

Due to the nature of Due to the nature of phase-locking phase-locking characteristics, a static characteristics, a static phase error is introduced.phase error is introduced.

II

QQ

Transmitted and decoded in-phase Transmitted and decoded in-phase datadata

OutlineOutline MotivationMotivation Project GoalsProject Goals Equipment Equipment QPSK TheoryQPSK Theory BackgroundBackground

System Block DiagramSystem Block Diagram RequirementsRequirements ResultsResults ConclusionsConclusions ReferencesReferences

System Block DiagramSystem Block Diagram(Simulink Model)(Simulink Model)

ChannelChannel

BasebandBaseband SignalSignal ShapingShaping Raised-cosine filtering

Reduces inter-symbol interference (ISI)

Interpolator/Decimator

InterpolatorInterpolator

DecimatorDecimator

System Block DiagramSystem Block Diagram(Simulink Model)(Simulink Model)

ChannelChannel

Phase-Locked LoopPhase-Locked Loop

DDS

-sin(Өon+Ф)

cos(Өon+Ф)

FIRLPF

FIRLPF

r(n)

Loop Filter

X(n)I(n)

Y(n)Q(n)

Y(n)*I(n) - X(n)*Q(n)

Corrected SignalCorrected Signal

+

-

(Carrier Recovery)(Carrier Recovery)

Functional RequirementsFunctional Requirements System clock = 50 MHzSystem clock = 50 MHz

Carrier signal frequency = 12.5 MHzCarrier signal frequency = 12.5 MHz• Data rate = 12.5 MbpsData rate = 12.5 Mbps

The frequency offset tolerance is 1 kHz.The frequency offset tolerance is 1 kHz.

(Carrier Synchronization)(Carrier Synchronization)ResultsResults

QPSK signalQPSK signal I & Q waveformsI & Q waveforms

ResultsResults(Phase Ambiguity)(Phase Ambiguity)

Transmitted Transmitted ImageImage

Received ImageReceived Image

ResultsResults Differential codingDifferential coding

(Phase Ambiguity Correction)(Phase Ambiguity Correction)

ChannelChannel

ResultsResults(No Phase Ambiguity / Color)(No Phase Ambiguity / Color)

Transmitted Transmitted ImageImage

Received ImageReceived Image

ResultsResults(Preserved data / Color)(Preserved data / Color)

ConclusionsConclusions QPSK wireless communication system is designedQPSK wireless communication system is designed

• Simulink model is constructedSimulink model is constructed• Carrier synchronization is achieved using digital PLLCarrier synchronization is achieved using digital PLL• Phase ambiguity is resolved using differential codingPhase ambiguity is resolved using differential coding• Tested whole system with real dataTested whole system with real data• Hardware implementationHardware implementation

Demonstrated the configurability of a software-defined radioDemonstrated the configurability of a software-defined radio• Expandable to MPSK, MQAM and other modulation schemesExpandable to MPSK, MQAM and other modulation schemes

Future WorkFuture Work Symbol timingSymbol timing

Error correcting capabilitiesError correcting capabilities

Implement other modulation schemesImplement other modulation schemes• 8PSK8PSK• 16PSK16PSK• and so on…and so on…

AcknowledgementsAcknowledgements Dr. Yufeng LuDr. Yufeng Lu

Dr. In Soo AhnDr. In Soo Ahn

Senior Project Support fromSenior Project Support from• Department of Electrical and Computer EngineeringDepartment of Electrical and Computer Engineering

Bradley University, Peoria IL 61625Bradley University, Peoria IL 61625

Questions?Questions?

Thank you

Thank you

ReferencesReferences Chris Dick, Fred Harris, and Michael Rice, Chris Dick, Fred Harris, and Michael Rice, FPGA Implementation of FPGA Implementation of

Carrier Carrier Synchronization for QAM ReceiversSynchronization for QAM Receivers, Journal of VLSI , Journal of VLSI Signal Signal Processing, Copyright © 2004 Kluwer Academic Publishers, Processing, Copyright © 2004 Kluwer Academic Publishers,

Netherlands.Netherlands.

Stephens, Donald R. Stephens, Donald R. Phase-locked loops for wireless Phase-locked loops for wireless communications digital communications digital and analog implementationand analog implementation. Boston: . Boston: Kluwer Academic, 1998.Kluwer Academic, 1998.

Vinod Kumar Venkat Reddy Gari, “Vinod Kumar Venkat Reddy Gari, “FPGA-based QPSK transceiver FPGA-based QPSK transceiver design”design”, Technical Report, Department of Electrical and , Technical Report, Department of Electrical and Computer Engineering, Bradley University, November 2008.Computer Engineering, Bradley University, November 2008.

Altera Corporation, "PLL & Clocking Glossary," Altera, 1995-2010. Altera Corporation, "PLL & Clocking Glossary," Altera, 1995-2010. [Online]. Available: http://www.altera.com. [Accessed: May [Online]. Available: http://www.altera.com. [Accessed: May

1, 1, 2010].2010].