Soft-Switching SEPIC Converter With Ripple-Freet

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 6, JUNE 2012 2879

Soft-Switching SEPIC Converter With Ripple-FreeInput Current

Hyun-Lark Do

Abstract—A soft-switching single-ended primary inductor con-verter (SEPIC) is presented in this paper. An auxiliary switch anda clamp capacitor are connected. A coupled inductor and an aux-iliary inductor are utilized to obtain ripple-free input current andachieve zero-voltage-switching (ZVS) operation of the main andauxiliary switches. The voltage multiplier technique and activeclamp technique are applied to the conventional SEPIC converterto increase the voltage gain, reduce the voltage stresses of the powerswitches and diode. Moreover, by utilizing the resonance betweenthe resonant inductor and the capacitor in the voltage multipliercircuit, the zero-current-switching operation of the output diode isachieved and its reverse-recovery loss is significantly reduced. Theproposed converter achieves high efficiency due to soft-switchingcommutations of the power semiconductor devices. The presentedtheoretical analysis is verified by a prototype of 100 kHz and 80 Wconverter. Also, the measured efficiency of the proposed converterhas reached a value of 94.8% at the maximum output power.

Index Terms—SEPIC converter, voltage multiplier, zero-current-switching (ZCS), zero-voltage-switching (ZVS).

I. INTRODUCTION

S EPIC converters have been adopted for many applicationssuch as power factor correction [1]–[5], photovoltaic sys-

tem [6], [7], and LED lighting [8]–[11]. However, it has severaldrawbacks. Its two major drawbacks are high voltage stressesof power semiconductor devices and low efficiency due to hard-switching operation of the power switches. Especially in high-voltage applications, higher voltage rated power semiconductordevices should be used. When the voltage rating is higher, theRds(on) of power MOSFETs is higher. So, it causes higher con-duction loss at the same level current. Therefore, if the voltagestress is reduced at the same level current, the overall efficiencycan be improved. To reduce the voltage stress and increasethe voltage gain, voltage multiplier techniques are proposedin [1], [12]–[15].

In order to reduce the volume and weight of the con-verter, soft-switching techniques such as zero-voltage-switching(ZVS) and zero-current-switching (ZCS) are necessary. High-frequency operation of dc–dc converters allows reduction of

Manuscript received May 28, 2011; revised September 13, 2011; acceptedNovember 3, 2011. Date of current version March 16, 2012. Recommended forpublication by Associate Editor Y.-F. Liu.

The author is with the Department of Electronic and Information Engineering,Seoul National University of Science and Technology, Seoul 139-743, Korea(e-mail: hldo@ seoultech.ac.kr).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2011.2175408

the volume and weight of their magnetic components. How-ever, switching losses and electromagnetic interference noisesare significant in high-frequency operation. Therefore, varioussoft-switching techniques have been introduced. Among them,the active clamp technique is often used to limit the voltagespike effectively, achieve soft-switching operation, and increasethe system efficiency [16]–[21].

SEPIC converters can have a low input current ripple, whichis one of the advantages of SEPIC converters. However, a bulkinductor should be used to minimize the current ripple. Inputcurrent ripple becomes one of important requirements due tothe wide use of low voltage sources such as batteries, supercapacitors, and fuel cells. It is because large ripple current mayshorten the lifetimes of those input sources [22]–[24].

In [25], a ZCS PWM SEPIC Converter was proposed. Twoswitches can operate with soft switching. However, three powerdiodes and three separate inductors are utilized. The voltagestress of the power switches is the sum of the input voltageand the output voltage which is equal to that in the conven-tional SEPIC converter. In [26], a resonant step up/down con-verter was proposed. Sort-switching operation is achieved. Twopower switches and two magnetic components are required.However, it has a pulsating input current and an additional filterstage is required in the input stage to suppress the input cur-rent ripple. Therefore, the number of magnetic components canbe increased. In [27], a bidirectional ZVS PWM SEPIC/ZETAconverter was proposed. Two main switches can operate withsoft switching. However, a bidirectional switch consisting oftwo power MOSFETs is required. Many switches are requiredand also complex driving circuits for them are required. More-over, the voltage stress of the switches is equal to that in theconventional SEPIC converter. In addition, a snubber circuit isrequired to suppress the parasitic voltage ringings across thebidirectional switches.

A soft-switching SEPIC converter with ripple-free input cur-rent is proposed. An auxiliary switch and a clamp capacitor areadded to the conventional SEPIC converter. A coupled inductorand an auxiliary inductor are utilized to obtain ripple-free inputcurrent and achieve ZVS operation of the main and auxiliaryswitches. The voltage stresses of the power switches and diodeare reduced by half by utilizing the voltage multiplier technique.Moreover, the reverse-recovery loss of the output diode is sig-nificantly reduced due to the resonance between the resonantinductor and the capacitor in the multiplier circuit. The pro-posed converter achieves high efficiency due to soft-switchingcharacteristics of power semiconductor devices. The theoreti-cal analysis is verified by an 80-W experimental prototype with48–200 V conversion.

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2880 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 6, JUNE 2012

Fig. 1. SEPIC converters. (a) Conventional SEPIC converter. (b) Ripple-freeSEPIC converter with a loosely coupled inductor. (c) Ripple-free SEPIC con-verter with a tightly coupled inductor.

II. ANALYSIS OF THE PROPOSED ZVS RESONANT

SEPIC CONVERTER

The conventional SEPIC converters are shown in Fig. 1. Theseparate inductor version is shown in Fig. 1(a) and the coupledinductor version is shown in Fig. 1(b). In the coupled inductorversion, a loosely coupled inductor Lc is used instead of twoseparate inductors L1 and L2 . Llk1 and Llk2 imply the leakageinductances of the coupled inductor. The coupled inductor ver-sion has advantages such as single magnetic component anda ripple-free input current. The ripple-free condition is relatedwith the magnetizing inductance, the turn ratio, and the leakageinductance Lk 2 of the coupled inductor. However, the leakageinductance is hard to control in mass production. Fortunately, theleakage inductance Lk 1 is not related with the ripple-free con-dition. Therefore, a tightly coupled inductor can be used withan additional inductor La instead of Lk 2 as shown in Fig. 1(c).

The circuit diagram of the proposed soft-switching SEPICconverter with a ripple-free input current is shown in Fig. 2. Inthe proposed converter, the resonant inductor Lr and the activeclamp cell consisting of the auxiliary switch Sa and the clampcapacitor Cc are added to the conventional SEPIC convertershown in Fig. 1(c). The equivalent circuit of the proposed con-

Fig. 2. Proposed soft-switching ripple-free SEPIC converter.

Fig. 3. Equivalent circuit of the proposed converter.

verter is shown in Fig. 3. The coupled inductor Lc is modeled asthe magnetizing inductance Lm and an ideal transformer with aturn ratio of 1:n. The diodes Da and Dm are the intrinsic bodydiodes of the auxiliary switch Sa and the main switch Sm . Thecapacitors Ca and Cm are their parasitic output capacitances.Key waveforms of the proposed converter are shown in Fig. 4.The switches Sa and Sm are operated asymmetrically and theduty ratio D is based on the main switch Sm . The operation of theproposed converter in one switching period Ts can be dividedinto five modes as shown in Fig. 5. To simplify the steady-stateanalysis, it is assumed that those capacitors C1 , Cc , and Co havelarge values and the voltage ripples across them can be ignored.

Prior to mode 1, the auxiliary switch Sa is conducting. Themagnetizing inductance current iLm is approaching to its min-imum value ILm 2 and the auxiliary inductor current iLa is ap-proaching to its maximum value ILa 1 . And the output diode isnot conducting.

Mode 1 [t0 , t1]: At t0 , the auxiliary switch Sa is turned OFF.Then, the energy stored in the magnetic components such as Lm ,Lr , and La starts to charge Ca and discharge Cm . Therefore, thevoltage vSa across the auxiliary switch Sa starts to rise fromzero and the voltage vSm across the main switch Sm starts tofall from VC c . Since the capacitors Ca and Cm are very small, the

DO: SOFT-SWITCHING SEPIC CONVERTER WITH RIPPLE-FREE INPUT CURRENT 2881

Fig. 4. Key waveforms of the proposed converter.

transition time interval Tt1 is very short and it can be simplifiedas follows:

Tt1 =(Ca + Cm ) VC c

(1 − n)ILa1 − ILm2. (1)

Since the transition interval Tt1 is very short, all the currentsflowing through the magnetic components are considered con-stant during this mode.

Mode 2 [t1 , t2]: At t1 , the voltage vSm arrives at zero. Then,the body diode Dm is turned ON. After that, the gate signal isapplied to the switch Sm and the channel of Sm takes over thecurrent flowing through Dm . Since the voltage vSm is clampedas zero with turn-on of Dm before the switch Sm is turned

ON, zero-voltage turn-on of Sm is achieved. In this mode, theinput voltage Vin is applied to Lm and the current iLm increaseslinearly from its minimum value ILm 2 as follows:

iLm (t) = ILm2 +Vin

Lm(t − t1) . (2)

Since the voltage vs at the secondary side of the cou-pled inductor Lc is nVin , the voltage vLa across La is−(VC c−nVin−VC 1)La /(La+Lr ). Therefore, the secondary cur-rent is decreases linearly from its maximum value ILa 1as follows:

is(t) = ILa1 −VC c − nVin − VC 1

La + Lr(t − t1) . (3)


Fig. 5. Operating Modes.

The input current iin is the sum of ip and iLm and given by

iin (t) = iLm (t) + ip(t) = ILm2 + nILa1

+[

Vin

Lm− n (VC c − nVin − VC 1)

La + Lr

](t − t1) . (4)

The main switch current iSm in this mode can be derived by

iSm (t) = iLm (t) − (1 − n)is(t) = − [(1 − n)ILa1 − ILm2 ]

+[

Vin

Lm+

(1 − n) (VC c − nVin − VC 1)La + Lr

](t − t1) .

(5)

At the end of this mode, the current iLm arrives at its maximumvalue ILm 1 and the minimum value ILa 2 .

Mode 3 [t2 , t3]: The main switch Sm is turned OFF at t2 .Then, the voltage vSm increases from zero and the voltage vSa

decreases from VC c at the same time due to the energy stored inthe magnetic components. With the same assumption as in mode

1, the transition time interval Tt2 can be simplified as follows:

Tt2 =(Ca + Cm ) VC c

ILm1 − (1 − n)ILa2. (6)

Tt2 is also negligible. All the currents are assumed constantduring Tt2 .

Mode 4 [t3 , t4]: At t3 , the voltage vSa arrives at zero. Then,the body diode Da is turned ON. After that, the gate signal isapplied to the switch Sa and the channel of Sa takes over thecurrent flowing through Da . Since the voltage vSa is clampedas zero before the switch Sa is turned ON, zero-voltage turn-on of Sa is achieved. In this mode, the voltage vp across Lm

is−(VC c−Vin ) and the current iLm decreases linearly from itsmaximum value ILm 1 as follows:

iLm (t) = ILm1 −VC c − Vin

Lm(t − t3) . (7)

With the turn-on of Sa , the output diode Do starts to conduct.Then the resonance between the resonant inductor Lr and thecapacitor C1 occurs. Since the voltage across the inductor La

is Vo+nVin−(1+n)VC c , the current is increases linearly in this


mode as follows:

is(t) = ILa2 +Vo + nVin − (1 + n)VC c

La(t − t3) . (8)

The input current in this mode is given by

iin(t) = ILm1 + nILa2

−[VC c − Vin

Lm− n (Vo + nVin − (1 + n)VC c)

La

](t − t3) .

(9)

The current iC 1 is given by

iC 1(t)=Vo − VC 1 − VC c

Zrsin ωr (t−t3) − ILa2 cos ωr (t−t3)

(10)where the resonant frequency ωr and the impedance Z of theresonant tank are

ωr =1√

LrC1(11)

Zr =√

Lr

C1. (12)

In this mode, the output diode current iDo and the switch currentiS 1 can be written by

iDo(t) = −is(t) − iC 1(t) (13)

iSa(t) = −iin(t) − iC 1(t). (14)

Mode 5 [t4 , t5]: At t4 , the output diode current iDo de-creases to zero and the zero-current turn OFF of the diodeDo is achieved. Since the current changing rate of Do is con-trolled by a resonant manner, its reverse-recovery problem issignificantly alleviated. Since the voltage across the inductorLa is (VC 1−nVC c+nVin )La /(La+Lr ), the current is increaseslinearly in this mode as follows:

is(t) = is(t4) +VC 1 − nVC c + nVin

La + Lr(t − t4) . (15)

At the end of this mode, iLm arrives at its minimum values ILm 2and maximum value ILa 1 .

III. DESIGN PARAMETERS

A. VC c and VC 1

Since the average voltage across Lm should be zero under asteady state, the clamp capacitor voltage VC c is obtained by

VC c =Vin

1 − D. (16)

Also, the average voltages across the inductors Lr and La shouldbe zero. Therefore, the voltage VC 1 is obtained by

VC 1 = VC c − Vin =D

1 − DVin . (17)

Fig. 6. Voltage gain.

B. Voltage Gain

By applying the volt-second balance law to the voltage acrossthe inductor La , the following relation is obtained:

− La

La + Lr(VC c − nVin − VC 1) DTs

+ (Vo − VC c − n(VC c − Vin)) d2Ts

+La

La + Lr(VC 1 − n(VC c − Vin)) (1 − D − d2) Ts = 0.

(18)

From (16) to (18), the voltage gain M of the proposed con-verter can be obtained by

M =Vo

Vin=

11 − D

·(

1 + nD +(1 − n)DLa

La + Lr

)≈ 1 + D

1 − D.

(19)The voltage gain of (19) is plotted and compared with otherconverters in Fig. 6.

C. Input Current Ripple

In mode 2, the input current iin is given by (4). From (16) and(17), the ripple component of iin can be removed by satisfyingthe following condition:

La + Lr = n(1 − n)Lm . (20)

Under the condition of (20), the input current iin is constant asILm 2 + nILa 1 . In mode 4, the input current iin is given by (9).Similarly, from (16), (17), and (19), its ripple component can beremoved by satisfying the same condition of (20). In this mode,the input current iin is constant as ILm 1 + nILa 2 . From (19),it can be seen that the inductor current iLa has the same slopeboth in mode 4 and 5. Therefore, the input current iin does notchange in mode 5.


From (2), ILm 1−ILm 2 is obtained by

ILm1 − ILm2 =Vin

LmDTs. (21)

Similarly, ILa 1−ILa 2 is obtained from (3) as follows:

ILa1 − ILa2 =VC c − nVin − VC 1

La + LrDTs. (22)

With the condition of (20), the following relation can be easilyderived from (16), (17), (21), and (22):

ILm2 + nILa1 = ILm1 + nILa2 . (23)

Therefore, the ripple component of the input current iin can beremoved under the condition of (20).

D. Minimum and Maximum Values of iLm and is

From Fig. 3, is = iC 1 + iDo . Since the average capacitorcurrent should be zero under a steady state, the average valueiC 1,avg of the capacitor current iC 1 is zero. And the average out-put diode current iDo,avg is equal to the average output currentIo . Therefore, the following relation can be obtained from thewaveform of the secondary current is in Fig. 4:

ILa1 + ILa2 = −2Io . (24)

From (16), (17), (20), (22), and (24), the maximum and min-imum values of is are derived by

ILa1 =(1 − n) VinDTs

2 (La + Lr )− Io (25)

ILa2 = − (1 − n) VinDTs

2 (La + Lr )− Io . (26)

Similarly, from Fig. 3, the input current iin is the sum of ip andiLm . Since the average current is,avg is−Io , the average primarycurrent ip ,avg is equal to−nIo . Therefore, the following relationcan be obtained from the waveform of the magnetizing currentiLm in Fig. 4:

ILm1 + ILm2 = 2(

Po

ηVin+ nIo

)(27)

where η is the efficiency and Po is the output power. From (21)and (27), the maximum and minimum values of iLm are derivedby

ILm1 =Po

ηVin+ nIo +

VinDTs

2Lm(28)

ILm2 =Po

ηVin+ nIo −

VinDTs

2Lm. (29)

E. ZVS Condition

From Fig. 4, the ZVS condition for Sa is given by

ILm1 − (1 − n)ILa2 > 0. (30)

Since ILm 1 is always positive from (28) and ILa 2 is alwaysnegative from (26) for n < 1, the condition of (30) is alwayssatisfied for n < 1. Therefore, the ZVS of Sa is always achieved.

Similarly, for the ZVS of Sm , the following condition should besatisfied

−ILm2 + (1 − n)ILa1 > 0. (31)

From (19), (25), and (29), the inequality (31) is rewritten by

Lm <VinDTs

2n (M/η + 1) Io. (32)

F. ZCS Condition

From (8), (10), and (13), the output diode current reset timingratio d2 can be obtained by solving the following equation:

− ILa2 −Vo + nVin − (1 + n)VC c

Lad2Ts

− Vo − VC 1 − VC c

Zrsin ωrd2Ts + ILa2 cos ωrd2Ts = 0.

(33)

To obtain ZCS of the output diode, the following conditionshould be satisfied

d2 < 1 − D. (34)

G. Voltage Stresses of the Power Switches and Output Diode

From Fig. 2, it can be seen that the voltages across the mainand auxiliary switches are confined to the clamp capacitor volt-age VC c . By using (16) and (19), the voltage VC c can be rewrittenas (Vin+Vo )/2. Since the voltage stress of the power semicon-ductor devices in the conventional SEPIC converters shown inFig. 1 is Vin + Vo , the voltage stress in the proposed converteris reduced by half. In the proposed converter, the voltage stressof the output diode is also reduced by half. In mode 2, thevoltage vLa is −(VC c−nVin−VC 1)La /(La+Lr ). Therefore, themaximum voltage vDo,max across the output diode is given by

vDo,max = Vo +(1 − n)VinLa

La + Lr+ nVin − VC c. (35)

For La >> Lr , it can be easily seen that vDo,max is (Vin+Vo )/2,which is half of that in the conventional SEPIC converters.

IV. EXPERIMENTAL RESULTS

To verify the steady-state performance and the theoreticalanalysis of the proposed soft-switching SEPIC converter withripple-free input current, a laboratory prototype is implementedand tested with the following specification.

1) Input voltage Vin = 48 V.2) Output voltage Vo = 200 V.3) Switching frequency fs = 100 kHz.4) Output power Po = 80 W.The control circuit was implemented with a constant-

frequency pulse width modulation controller KA7552 fromFairchild. The required voltage gain M is 4.17. From (19), theduty cycle D is calculated as 0.613. The turn ratio n of thecoupled inductor is selected as 0.25. The ZVS condition of (32)


Fig. 7. Experimental waveforms of iin , is , and vS m .

Fig. 8. Experimental waveforms of iD o , iC 1 , and vS m .

gives Lm < 272 μH with an assumption of h = 0.95. The magne-tizing inductance Lm is selected as 190 μH. Then, the conditionfor ripple-free input current of (20) gives La + Lr = 35.6 μH.Then, the values of the inductors La and Lr are selected as34.5 and 1.1 μH, respectively. The value of Cr is selected as1 μF to meet the condition of (34). The values of the capac-itors Cc and Co are selected as 6.6 and 100 μF, respectively.

Fig. 7 shows the experimental waveforms of iin , is , and vSm

under various load conditions. Regardless of load condition, theproposed converter shows almost ripple-free input current. InFig. 7, the main switch voltage vSm is well clamped as around124 V, which agrees with the theoretical analysis. Fig. 8 showsthe experimental waveforms of iDo , iC 1 , and vSm . It can beeseen that the resonance between Lr and C1 occurs and the res-onant current flows through the output diode during turn-off ofSm . The experimental results are in good agreement with thetheoretical analysis. Fig. 9 shows the soft-switching waveformsof Do , Sm , and Sa . Fig. 9(a) shows the ZCS operation of Do . Theresonance between C1 and Lr ends before the turn-on of Sm .Since the voltage vDo is maintained as zero after the current iDo

arrives at zero, the turn-off loss of the output diode is seen to bealmost zero and the ZCS operation of Do is achieved. Also, thereverse recovery of the output diode is significantly alleviated.Fig. 9(b) shows the soft-switching waveforms of Sm . It is ob-served that the gate pulses are driving the main switch Sm , onlyafter the switch voltage vSm has reached zero. It indicates thezero voltage turn-on of Sm . Similarly, the auxiliary switch Sa isturned ON at zero voltage as shown in Fig. 9(c). Fig. 10 showsthe measured efficiency of the proposed converter and it is com-pared with that of the conventional SEPIC converter in Fig. 1(a).The proposed converter exhibits an efficiency of 94.8% at fullload condition. The proposed converter shows higher efficiencythan the conventional SEPIC converter due to its soft-switchingcharacteristic of power switches Sm and Sa and the output diode


Fig. 9. Soft-switching waveforms Do , Sm , and Sa .

Do . At light load, the proposed converter shows lower efficiency.It is mainly because the secondary current is increases the con-duction loss and it makes up a significant portion of the power

Fig. 10. Measured efficiency.

loss at light load. As shown in Fig. 7, the current is is large evenat light load. It is one of the major drawbacks of the proposedconverter.

V. CONCLUSION

The operation principle, theoretical analysis, and the imple-mentation of a soft-switching SEPIC converter with ripple-freeinput current are presented in this paper. In the proposed con-verter, the coupled inductor with an auxiliary inductor is usedto provide ripple-free input current and achieve ZVS operationof main and auxiliary switches. The advantages of the proposedconverter are low voltage stresses, low switching losses, ripple-free input current, alleviated reverse-recovery problem of theoutput diode, and high efficiency. The design consideration ofthe proposed converter is included. The experimental resultsbased on a prototype are presented for validation.

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[27] I.-D. Kim, S.-H. Paeng, J.-W. Ahn, E.-C. Nho, and J.-S. Ko, “New bidi-rectional ZVS PWM Sepic/Zeta DC–DC converter,” in Proc. IEEE Int.Symp. Ind. Electron. (ISIE), 2007, pp. 555–560.

Hyun-Lark Do received the B.S. degree fromHanyang University, Seoul, Korea, in 1999, and theM.S. and Ph.D. degrees in electronic and electricalengineering from the Pohang University of Scienceand Technology, Pohang, Korea, in 2002 and 2005,respectively.

From 2005 to 2008, he was a Senior Research En-gineer with the PDP Research Laboratory, LG Elec-tronics, Inc., Gumi, Korea. Since 2008, he has beenwith the Department of Electronic and InformationEngineering, Seoul National University of Science

and Technology, Seoul, Korea, where he is currently a Professor. His researchinterests include the modeling, design, and control of power converters, soft-switching power converters, resonant converters, power factor correction cir-cuits, driving circuits for plasma display panels.

Soft-Switching SEPIC Converter With Ripple-Freet

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