SoCKs Flow: Here, There, and Back Again
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Transcript of SoCKs Flow: Here, There, and Back Again
SoCKs Flow: Here, There, and Back Again
Apala Guha, Jerry Qi, Mateja Putic, Adam Cabe
12/13/06ECE 686: SoC Design
SoCKs Hardware / Software co-design env.
Leon SPARC Core AMBA bus Custom Logic
Compile software that uses custom logic
HDL, test benches, and C compiler provided
Our Contribution to SoCKs Added and verified wishbone core Simulating verilog netlist Synthesis
Both front and back end Complete in TSMC .18 library
Design for test Inserted scan chain
Design for Test
Adam Cabe
Contributions I/O Pad Insertion Scan Chain Insertion Memory Generation
Pads and Library Decided on TSMC .18 um for pads TSMC library also provides scan
flops This is an Artisan lib – No physical
view This library also allowed for easy
porting of the generic memory The generic library is similar to TSMC
Pads Modified HDL files to match the .lib file
This was a manual change to the HDL Also removed one entire file from synth.
Needed to add VDD, VSS, corner, and scan pads to the top verilog netlist Cannot synthesize pads with no output
Pads (cont.) Compiled the .io file for Encounter
.io file necessary for proper pad placement
Orient: R0
Pad: RingInst/pad42EM_A_21 N
Orient: R0
Pad: RingInst/PCur NE
Orient: R270
Pad: RingInst/PVdd2 E
Orient: R270
Pad: RingInst/PVss2 E
Scan Chain Scan Chain – Provides ability to
test sequential logic Functions like a shift register in the
design Uses existing registers as the shifter
regs. Not straightforward to implement
using RTL compliler
1) Synthesize top level HDL without scan
2) Insert necessary I/O into designa) VDD, VSS, Corners, Scan Enable, etc
3) Re-synthesize this new verilog netlista) This synthesis will insert scan chains
4) Output proper scan.def file for Encounter
Scan Chain Procedure
Scan Details Define the Scan and Test enable
signals Define specific chains or let
RTL compiler auto create chains DFT rule check
Determines whether flops are scan ready – generally not
This command fixes errors? – Yes fix_dft_violations -async_set_reset -test_mode TM
Scan Details (cont) Can define details of scan chain
Max length, min number (for auto-gen.) … For TSMC, maps all flops as scan flops
Need to tell RTL compiler to reroute the scan and test enable signals to these flops
Synthesize design Final scan connecting
Scan Output Only 2 outputs
Top level, scan inserted, netlist .def file containing scan chain details
- AutoChain_17_seg1_CLK_rising
+ START PIN DFT_sdi_17 + FLOATING CoreInst/leon1/mcore0/ioport0/r_reg[iconf][0][isel][1] ( IN SI ) ( OUT Q ) CoreInst/leon1/mcore0/ioport0/r_reg[iconf][0][isel][2] ( IN SI ) ( OUT Q ) CoreInst/leon1/mcore0/ioport0/r_reg[iconf][0][isel][3] ( IN SI ) ( OUT Q ) CoreInst/leon1/mcore0/ioport0/r_reg[iconf][0][isel][4] ( IN SI ) ( OUT Q ) CoreInst/leon1/mcore0/ioport0/r_reg[iconf][0][pol] ( IN SI ) ( OUT Q ) CoreInst/leon1/mcore0/ioport0/r_reg[iconf][1][edge] ( IN SI ) ( OUT Q ) …
Scan Chain in Encounter Imported top netlist and .def file
Post-Place Post-CTS
Scan Chain in Encounter Did manually first
Wanted to show scan connections Should also work with Jerry’s .tcl
script
Scan paths after routing ->
Design for Test Problems Cannot selectively scan yet Cannot verify scan chain
ET needs library files in .v form Also means cannot generate test vectors
Have not implemented ConformalLogic Equivalence Checker Lots of manual constraints in the scripts
Memory Generation Using Jerry and Jiajing’s
modified generator Generated memories for SoCKs in
TSMC No wrapper necessary, HDL files
had exactly the correct inputs and outputs Lucky!
Conclusion Implemented front and
back end synthesis Simulated verilog netlists Added and tested wishbone core Implemented scan chain
Thanks!