SoCDesigns –Impact on Verification · TVS Verification Futures Conference November 2013...
Transcript of SoCDesigns –Impact on Verification · TVS Verification Futures Conference November 2013...
TVSVerification Futures Conference
November 2013
SoC Designs – Impact on Verification
Mark Olen
Verification Intrapreneur
Mentor Graphics
www.mentor.com© 2013 Mentor Graphics Corp. Company Confidential
SoC Designs – Impact on VerificationSession Overview
2
� Design Challenges
� Verification Impact
� Technical Advances
� Wrap Up
Mentor Graphics – TVS 2013 Keynote – Mark Olen
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Design and VerificationCurrent Challenges and Future Outlook
3 Mentor Graphics – TVS 2013 Keynote – Mark Olen
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Design and VerificationWe are Living in an SoC World
2007 ITRS
4 Mentor Graphics – TVS 2013 Keynote – Mark Olen
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Design Challenges: SoCs Change EverythingParallel Processing Required for End Product Performance
� Market— Embedded Processing
� Challenges— Multiple Embedded Cores— Re-use of IP Blocks— Distributed design teams
5 Mentor Graphics – TVS 2013 Keynote – Mark Olen
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Design Challenges: SoCs Change EverythingSystem Architectures to Reduce Power Consumption
� Market— Mobile Applications
� Challenges— Multiple Embedded Cores— Re-use of IP Blocks— Distributed design teams— Heterogeneous Processors— Complex Interconnect— Shared Memory
6 Mentor Graphics – TVS 2013 Keynote – Mark Olen
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Design Challenges: SoCs Change EverythingCache Coherent Architectures to Increase System Level Performance
� Market— Enterprise Computing
� Challenges— Multiple Embedded Cores— Re-use of IP Blocks— Distributed design teams— Heterogeneous Processors— Complex Interconnect— Shared Memory— Network on Chip— Multi-level Caching
7 Mentor Graphics – TVS 2013 Keynote – Mark Olen
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Design Challenges: SoCs Change EverythingToday’s FPGAs are also SoCs
� Market— FPGA Applications
� Challenges— Same as SoCs
8 Mentor Graphics – TVS 2013 Keynote – Mark Olen
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The Historical Design GapAddressed with Reuse
DesignProductivityGap
Silicon Density DoublesEvery 18 Months
Design ProductivityDoubles Every 39 Months
Capacity
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41%
33%
13% 13%
28%
35%
22%
15%
0%
10%
20%
30%
40%
NEW LOGIC REUSED LOGIC(Developed in-
house)
PURCHASED IP ANALOG, RFAND/OR MIXED
SIGNAL
2007
2012
Design Reuse
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Verification InvestmentConsumes Majority of Project Time
0%
5%
10%
15%
20%
25%
1%-20% 21%-30% 31%-40% 41%-50% 51%-60% 61%-70% 71%-80% >80%
Non-FPGA Study Participants
Time (Percent)
Total Project Time Spent in Verification
2007
2010
2012
2007: Mean 49%2010: Mean 56%2012: Mean 56%
Wilson Research Group and Mentor Graphics, 2012 Functional Verification Study
Mentor Graphics – TVS 2013 Keynote – Mark Olen10
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54%
2007
46%
2007
47%
2012
53%
2012
Doing Design Doing Verification
Design Engineer Project Time2007 - 2012
Designers’ Time InvestmentDoing More and More Verification
Source: Wilson Research Group and Mentor Graphics, 2012 Functional Verification Study
Mentor Graphics – TVS 2013 Keynote – Mark Olen11
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0
20
40
60
80
100
2007 2012 2017 2022 2027 2032 2037
At this rate…In 25 years, ALLof a designer’s time will be devoted to verification
Project Time 2007 - 2037
Design
Verification
Time Design Engineers Spends Doing:
Time (Percent)
Designers’ Time InvestmentDoing More and More Verification
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More and More Verification Engineers Mean peak number of design vs. verification engineers
7.8 8.1 8.5
4.8
7.68.4
2007 2010 2012
~ 1-to-1 ratio of peak design and verification
engineers
Verification Engineers
Design Engineers
Mentor Graphics – TVS 2013 Keynote – Mark Olen13
Source: Wilson Research Group and Mentor Graphics.
www.mentor.com© 2013 Mentor Graphics Corp. Company Confidential
Today’s Gap is in VerificationNew Technologies Augment Improved Performance
"If I had asked people what they wanted, they would have said faster horses.”
-Henry Ford
Capacity
Design Productivity
VerificationProductivity
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SoC Designs – Impact on VerificationSession Overview
Mentor Graphics – TVS 2013 Keynote – Mark Olen15
� Design Challenges
� Verification Impact
� Technical Advances
� Wrap Up
www.mentor.com© 2013 Mentor Graphics Corp. Company Confidential
Verification ImpactSoCs Change Everything
� Market Place
� Language Standardization
� Process Standardization
� Emulation is Mandatory
� Formal is mandatory
� Low Power Verification required
� Data is exploding
� Entire process much be managed
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Verification Market According to EDACOverall Verification Market Grew by 38%
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0
100
200
300
400
500
600
700
800
900
1000
2010 2012
380430
190
365130
170
Millions ($)
Formal 31% Growth
Emulation 94% Growth
Simulation 13% Growth
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Factors in Market GrowthStandards Enable Technical Advances
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� Standards Foster Innovation— Level the competitive landscape— Channel resources in the right
direction
� Necessity Drives Adoption— Users are moving to Formal and
Emulation because they have to— New innovations make them easier
to use
0%
20%
40%
60%
VHDL Verilog Synopsys Vera System C SystemVerilog Specman e C/C++ OTHERTestbench
Languages Used for Verification (testbenches)
2007
2010
2012
0%
10%
20%
30%
40%
AccelleraUVM
OVM MentorAVM
SynopsysVMM
SynopsysRVM
CadenceeRM
CadenceURM
Other
Testbench Methodologies and Base-Class Libraries
2010
IEEE Std 1801™-2009
UPFUCIS
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Verification Impact: ProcessStandardization of the SoC Verification Process
Ten years ago IC/ASIC verification was partitioned into two main steps:
IntegrationVerification
Block-LevelVerification
Block Full Chip
Mentor Graphics – TVS 2013 Keynote – Mark Olen19
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Verification Impact: ProcessStandardization of the SoC Verification Process
Mentor Graphics – TVS 2013 Keynote – Mark Olen
� IP Challenges— Protocol Compliance— Block Level Functionality
� Subsystem Challenges— Connectivity— Functional Performance
� SoC Challenges— Registers and Memory Mapping— Clock Domain Management
� System Challenges— HW/SW Interaction— Low Power Optimization
Block-LevelVerification
InterconnectVerification
IntegrationVerification
Application/SW
Verification
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Verification Impact: EmulationEmulation is becoming mandatory for System Level Verification
� SoC capacity and performance requirements exploding
� SoC verification requires real SW with HW
� Power management implemented in SW and HW— Critical to verify together
� Verification must flow smoothlyfrom Subsystem to SoC SoC
CPU
Arbiter
Fabric
UART
Slave IF
GPIO
Slave IF
PCI
Express
PHY
Fabric
Software
Memory
Master IF
Display
Processor
PHY
Slave IF
SATA
PHY
Slave IF
Ethernet
PHY
Slave IF
USB
PHY
SlaveIFMaster IF
CPU
Master IF
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Verification Impact: Low PowerLow Power Verification required below 65mn
� Active Power Management — The application and control of power reduction techniques
to minimize power consumption, especially static leakage
� Becoming important at 90nm
� Necessary below 65nm
Mentor Graphics – TVS 2013 Keynote – Mark Olen22
0
50
100
150
200
250
.25µ .18µ 130nm 90nm 65nm
Active PowerLeakage
Total Chip Power (w
)
50%
55%
60%
65%
70%
>=130nm
90nm 65nm 45nm <=32nm
59%60%
58%
65%
70%% Using Active Power Mgmtfor Non-FPGA Designs
Wilson Research Group and Mentor Graphics 2010 Functional Verification Study, Used with permission
www.mentor.com© 2013 Mentor Graphics Corp. Company Confidential
Verification Impact: FormalFormal - It’s not Just for Experts Anymore
FormalPropertyChecking
FullyAutomaticFormal
AutomatedApplications
Automatic
Manual
FormalExperts
Everyone
1990s Today2000s
Mentor Graphics – TVS 2013 Keynote – Mark Olen23
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Verification Impact: DataManaging Verification Data is a Growing Challenge
� Data Explodes Exponentiallyin Proportion to Design Size— 100’s to 1000’s of Mbytes— Multiple teams— Multiple engines— Multiple processes
� Requires Intelligent Handlingand Lossless Reduction
� No Measurement Equatesto No Improvement
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Verification Impact: ProcessEntire process must be managed and optimized
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� Schedule, Quality,Resources, Costs
� Data, Process, and Tools
� Capacity, Throughput,Turn-around
Analyze
Refine
Verify
Build
TestPlan
Design Spec
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SoC Designs – Impact on VerificationSession Overview
Mentor Graphics – TVS 2013 Keynote – Mark Olen26
� Design Challenges
� Verification Impact
� Technical Advances
� Wrap Up
www.mentor.com© 2013 Mentor Graphics Corp. Company Confidential
Mentor Graphics SolutionClosing the Verification Gap
Commonality Across Engines
Automation & Innovation
Methodology & Expertise
Mentor Graphics – TVS 2013 Keynote – Mark Olen27
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Closing the Verification GapCommon Everything Across Simulation, Emulation, and Formal Engines
Simulation EmulationFormal
Unified High Performance Debug
Unified High Performance Coverage and Analysis
Low power flow that scales with full UPF
Reusable testbenches & environments with Mentor VIP
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Verification PerformancePure Simulation Speed & Complementary Technologies
� Simulation Speed
— Constant Single-Core Speed Up
— Leading-Edge Multi-Core Technology
� Complementary Technologies
— Testbench Automation
— Automated Formal
— Verification Management
— Regression Optimization
� Emulation Acceleration
— Commonality Across Engines
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Debug ProductivityPerformance, Standards & Abstraction
� Debug Challenges
— Performance & Capacity
— TLM, RTL, & GLS
— Simulation & Emulation
� Standards Support
— SystemVerilog, SystemC, & VHDL
— UVM Methodology
— UPF for Low Power
� Multi-Abstraction
— IP Block Protocol Level
— Interconnect Subsystem Level
— Full HW/SW System Level
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Verification IP Re-UseBroad Library of Verification IP Components
� AMBA – (CHI, ACE, AXI4, AXI3, AHB, APB)
� Ethernet – (100G, 40G, 10G, 1G, 100MB, 10MB)
� MIPI – (CSI-2, DigRFv4, DSI, LLI, LLI2, M-PHY)
� PCI Express - (PIPE, 3.0, 2.0, 1.1)
� USB - (OTG, 3.0, 2.0, 1.1)
� Memories - (DDR2, DDR3, LPDDR2, LPDDR3)
� Display - (HDMI 2.0/1.4)
� SAS – (SPL 3, 2.1, 2.0)
� Other – (I2C, I2S, JTAG, Smart Card,
SPI4.2, SPI, UART)
Mentor Graphics – TVS 2013 Keynote – Mark Olen31
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Verification IP Re-UseAutomation and Innovation
� UVM Methodology
� Test Planning
� Automated Stimulus
� Compliance Checking
� Protocol Coverage
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Verification IP Re-UseCommonality Across Engines
� Simulation
— Full Functional Verification
— Powerful Protocol Debug
� Formal
— Clock Domains
— Low Power
� Emulation
— Virtual Devices
— Supports ICE
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Intelligent Testbench AutomationStandard UVM Foundation
� UVM Methodology
— Sequence Generation
— Stimulus & Coverage
� Standard Verification IP
— Drivers/Monitors
— Advanced Debugging
� Intelligent TestbenchAutomation
— Accelerated Coverage
— Rapid Test Expansion
Mentor Graphics – TVS 2013 Keynote – Mark Olen34
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Intelligent Testbench AutomationAutomation and Innovation for Multiple Design Applications
Industry
Storage &
Networking
Design
AXI Bus Bridge
Verification
VCS
SystemVerilog
Time
1
Week
Current Results
170 X faster
Ultra Results
Wireless
Networking
Ethernet 802.11
Device
VCS
NTB35
Hours
Basestation
Telecom
Proprietary Interface
Module for a Router
NC Sim
Specman e
not
avail
Consumer
Electronics
Error Checking and
Correcting Module
NC Sim
Specman e
1
Day
Office
Products
Printer Image
Processor
Questa
SystemVerilog
3
Days
36 hours on 6 CPUs8 weeks on 6 CPUs
100% coverage60% coverage
196,000 tests26,315,000 tests
100% coverage79% coverage
37 X faster
118 minutes>18 hours
100% coverage100% coverage
9.5 X faster
75,000 vectors825,000 vectors
100% coverage100% coverage
10 X faster
48 CPU hours3175 CPU hours
97% coverage95% coverage
66 X faster
+ 40% coverage
+ 2 % coverage
+ 21% coverage
Equal coverage
Equal coverage
����
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==
==
==
==
==
Benefits
Switching
Subsystems
Multiple Master
AXI Bus Fabric
Questa
Directed Tests
2
Days
400,000 tests10,000 tests 40 X more tests���� ==
Wireless
TelecomInterrupt Controller
VCS
Vera and SV
6
Days
45 minutes3 days
100% coverage100% coverage
27 X faster
Equal coverage���� ==
ProcessorsMulti-Core Memory
Sub-system
Questa
SystemVerilog
1
Day
30 minutes5 hours
100% coverage100% coverage
10 X faster
Equal coverage���� ==
170 X faster
37 X faster
9.5 X faster
10 X faster
66 X faster
+ 40% coverage
+ 21% coverage
40 X more tests
27 X faster
10 X faster
Mentor Graphics – TVS 2013 Keynote – Mark Olen35
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Intelligent Testbench AutomationCommonality Across Engines Extends to System Level
� Current System Level Verification
— All or Nothing Methodology
— Manual Test Programs Difficult to Write
— HW/SW Coverification Difficult to Debug
� Intelligent Testbench Automation
— Embedded C Test Programs
— Run on Simulator or Emulator
� System Level Benefits
— Find Bugs Earlier
— Easier to Debug
Intelligent
Embedded
Test
Programs
Write Manual
Test Program
Simulation
Boot OS
Or
Load SW
Drivers
Emulation
Mentor Graphics – TVS 2013 Keynote – Mark Olen36
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Interconnect Subsystem VerificationFunctionality, Performance, and Coherency
� Standard Methodology
— UVM VIP Library
— Configurable Interconnect Testbenches
— Automatic Traffic Generation
� Innovation and Automation
— Functionality Visualizations
— Performance Charts
— Coherency Coverage Analysis
� Commonality Across Engines
— Supports both Simulation & Emulation
— Connectivity via Automated Formal
Mentor Graphics – TVS 2013 Keynote – Mark Olen37
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Formal AutomationComplements Simulation and Emulation
� Property Checking
— Protocols
— Control Logic
� Automated Applications
— Connectivity
— Register Mapping
� Fully Automatic
— Clock Domains
— Code Coverage
— Auto Checking
— Assertion Generation
PropertyChecking
Automated Applications
Fully Automatic
AdvancedUsage
FormalAutomation
Mentor Graphics – TVS 2013 Keynote – Mark Olen38
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Formal AutomationAutomation and Innovation used by Industry Leaders
� Semiconductor ICs
— Top 20 Suppliers
— 17 use Questa Formal
— (iSuppli 4/13)
� Fabless IC Companies
— Top 20 Suppliers
— 19 use Questa Formal
— (IC Insights 3/13)
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Low Power MethodologyLow Power Methodology and Automation
� UPF layers additional hardwareon your design
� Must ensure all tests work in all power state configurations
� Requires verification planning
� Power control needs to be encapsulated for reuse
States
Elements Off PwrOn Init Alert DispOn Import Display Generate Export DispOff
PCU OFF ON ON ON ON ON ON ON ON ON
CPU OFF ON ON ON sleep ON ON ON ON OFF
ROM OFF ON ON ON sleep ON ON ON ON OFF
RAM OFF ON ON sleep sleep ON ON ON ON sleep
Ctrl Intf OFF OFF ON ON ON ON ON ON ON ON
Data Intf OFF OFF OFF OFF OFF ON OFF OFF ON OFF
Video SS OFF OFF sleep <prev> ON <prev> ON <prev> <prev> sleep
FPU OFF OFF OFF OFF OFF OFF OFF ON OFF OFF
JPEG OFF OFF OFF OFF OFF OFF OFF OFF ON OFF
Component Power States
Mentor Graphics – TVS 2013 Keynote – Mark Olen40
PMBProcCore
RAM
Power Domain 1 Power Domain 2
Power Domain 3 Power Domain 4
Iso_en
01100100
1100
000011
1.0 V 0.8 V
IEEE Std 1801™-2009
UPF
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Power Aware SimulationFastest, Most Comprehensive UPF-based LP Verification
� IEEE Std 1801-2009 UPF support
� High performance native UPF
� Visualization of power management
� Comprehensive reporting
� Automatic power aware checks
� Power state coverage data collection
� Power state and transition display
41
Enables early verification of power architecture
with RTL and Gate-Level power aware simulation
Mentor Graphics – TVS 2013 Keynote – Mark Olen
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Verification ManagementBuilt on UCIS Standard – Supports Multiple Engines
� Accellera Sub-Committee
— Unified Coverage Interoperability Standard
— User and Vendor Community
� Industry Goal
— Interoperability Opportunities
— Standard Coverage Models
— Standard Exchange Format
� Mentor Graphics UCDB API
— Developed and Donated by MGC
— Selected and Adopted by Accellera
— Now the Basis for Standard
Mentor Graphics – TVS 2013 Keynote – Mark Olen42
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Regression ManagementAutomation and Innovation Optimizes Production Testing
� Current Regression Management
— Internally Developed Scripts
— Expensive to Create
— Difficult to Maintain
� Verification Run Management
— Scalable Solution
— Simple to Implement
— Easy to Maintain
� Production Testing Benefits
— Faster Throughput
— Shorter Turn Around Time
Mentor Graphics – TVS 2013 Keynote – Mark Olen43
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Verification ManagementAutomation and Innovation Optimizes Production Testing
Industry Sub process Current Results Questa VM Results BenefitsProductivity
Semiconductor Merge of all coverage from all tests 70 minutes55 hours 47 X faster�� ==Turn-around
Wireless Results Analysis Queries 15 minutes1 hour 4 X fasterTurn-around �� ==
Automotive
Nightly regression test maximum 320 tests40 tests 8 X more tests
Nightly regression test setup time
Nightly regression addition time
30 minutes 2 minutes 15 X less time
60 minutes 5 minutes 12 X less time
Nightly regression Script Files 10 files 1 file 10 X easier
Nightly regression Results Analysis >1 hour <1 minute 60 X faster
��
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==
==
==
==
==
Throughput
Turn-around
Turn-around
Turn-around
Turn-around
MicroprocessorTest Merge Time 7 hours7 days 24 X faster
Data Storage 10 MB1 GB 100X less memory
��
��
==
==
Turn-around
Capacity
IP Developer
Nightly regression test time 2.5 hours28 hours
20 minutes2 hours
9 X faster
6 X fasterResults and Coverage Analysis
30 seconds15 minutes 30 X fasterRegression file cleanup
��
��
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==
==
==
Throughput
Turn-around
Capacity
47 X faster
4 X faster
8 X more tests
15 X less time
12 X less time
10 X easier
60 X faster
24 X faster
100X less memory
9 X faster
6 X faster
30 X faster
Mentor Graphics – TVS 2013 Keynote – Mark Olen44
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Partnering with CustomersAutomating and Innovating to Solve SoC Verification Problems
Enterprise ComputingEmbedded Processing
FPGAMobile Applications
Mentor Graphics – TVS 2013 Keynote – Mark Olen45
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SoC Designs – Impact on VerificationSession Overview
Mentor Graphics – TVS 2013 Keynote – Mark Olen46
� Design Challenges
� Verification Impact
� Technical Advances
� Wrap Up
www.mentor.com© 2013 Mentor Graphics Corp. Company Confidential
Wrap UpSummary
� SoC’s are Creating Design Complexity and Verification Challenges
� Standards are Enabling Technical Innovation
� Smarter Solutions are Emerging to Close the Verification Gap
Mentor Graphics – TVS 2013 Keynote – Mark Olen47
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Wrap UpHow Do You Learn More?
� Verification Planning
� UVM Methodology and Coverage Cookbooks
� UVM & OVM Basic & Advanced Courses
� Metrics for SoC Verification
� Testbench Acceleration & Co-Emulation
� Intelligent Testbench Automation
� Power Aware Verification
� Assertion-Based Verification, CDC Verification, VHDL 2008, FPGA Verification, AMS etc…
Mentor Graphics – TVS 2013 Keynote – Mark Olen48
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