MULTICHIP MODULE STRUCTURES FOR MINIMISING CROSS-TALK EFFECTS IN HIGH-SPEED APPLICATIONS.

S.Y .Kulkarni Department of Electrical Engg.,

B.V.B.College of Engg. and Tech., Hubli - 580 031 (INDIA)

ABSTRACT

Remarkable progress has been made in electronic

systems while reducing cost and power while simul-

taneously increasing the reliability by attaching un-

packaged ICs directly to a high density-wired sub-

strate. This multichip technology .offers significant

advantages like reduction in interchip wiring length and associated loading effects[l]. Multichip mod-

ules are gaining importance gradually for high-speed applications in satellite communications, LAN and

radio paging networks[2]. The dense interconnec-

tion system and the multilayer nature of the MCM structure introduces limitations on system- per-

formance at high-speed operations, since the nearby conductors develop electromagnetic coupling and develop a voltage called cross-talk voltage. This

voltage has to be controlled for better and proper

functioning of the circuit ahead. This has motiv-

ated this work to develop practical MCM structures

which will result in minimum cross-talk voltages

in the nearby interconnects. In this paper, difler-

ent cross-talk minimisation techniques are presen-

ted with a few numerical examples. The proposed negative shielding concept for multilayered struc-

tures is also presented in this paper.

1 Introduction

Estimation of the cross-talk voltage requires the extraction of the interconnect parameters. At very high speeds interconnects start behaving like a transmission line and hence RLCG distributed

K.V.V.Murthy Department of Electrical Engg., Indian Institute of Technology Bombay - 400 076 (INDIA)

transmission line model has been employed in this work, instead of a simple RC lumped network for characterising a MCM. The parameters for such models are computed using the powerful and ver- satile finite element method (FEM). To improve the accuracy and computation time of FEM, special elements like quarter-point singular elements and quadrangle infinite elements are employed. Quasi- TEM propogation modes are assumed while mak- ing the time-domain analysis of the interconnects. Wave equations are solved using Modal analysk3 techniques to compute near-end and far-end crow. talk voltages, by taking into account the respect- ive terminal network details. A brief theory of the techniques employed to compute cross-talk voltage is presented in the section 2 and different cross- talk minimisation techniques are discussed in the section 3 of this paper. Also, the proposed neg- ative shielding cross-talk minimisation technique is presented in section 3 of this paper.

2 Brief Theory In order to compute the cross-talk voltages at

both the ends of the interconnects, we have em- ployed “Modal analysis Technique”. In this tech-

nique, the Wave equations, given in equations (1) and (2), are solved by employing the technique of computation of eigen-values and eigen-vectors. In this paper, this technique has been presented briefly, towever, detailed discussion of the tech- nique can be obtained from ref.[3].

34

Where [L] and [C] denote the inductance and ca- pacitance matrices of the (N + 1) conductor in- terconnection system. These parameters are com- puted accurately using "Finite element Method". In this method, 2-D Laplace equation has been

solved by employing the variational energy principle with appropriate boundary conditions[4]. The en- ergy functional corresponding to the Laplace equa tion, can be expressed in the form [5]:

(3)

Where [K] is the flux potential matrix whose el+ ments are the functionals involving the "Shape func- tions" of the finite elements.

Solving the eqn.(3) with appropriate boundary conditions gives

[K1'[41 = PI' (4)

This set of linear simultaneous equations is solved by using "Banded Gaussian Elimination technique". The potential values obtained are used to compute the charge (Q) enclosed by the conduct- ors by employing the "Gauss Law". Then one can find the capacitance matrix [C] as follows:

1 Vn) = 0

(5)

Qi

Vj Cij = -l(K, Vz, .... ...., Vj-l,Vj+l, .........

For i=j, Cii is termed aa the self-capacitance and for i # j, C'j is termed aa the mutual capacitance.

The inductance matrix [L] is obtained by em- ploying the properties of quasi-TEM propogation mode[5].

Where, v is the velocity of light and [CO] is the capacitance matrix obtained by treating the dielec-

tric media as air. A lossless line embedded in an inhomogeneoue

dielectric which vary dong the line cross-section, but not along the length of the line, ie a dispersive transmission medium. However, there exista a set conductor voltages and currents for which the pro- pogation is non-dispersive[6]. These set af voltages and currents are called aa eigen-mode voltages and currents; these vectors can be obtained by the rele tion given in eqn.(7).

Where [U] is the identity matrix. In order that eqn.(7) has non-trivial solutions for the line voltages, we must have

(8) 1 l" det I +U1 - MCl I = 0

Eqn.(8),given above is an eigenvalue equation and & is an eigenvalue of the matrix [L][q. Therefore, the voltage vector[Vom]can be considered aa an ei- genvector of the matrix [L][C] corresponding to the eigen value $. Since, the product [L][q is an N x

N matrix, there will be N eigenvaluea and N eigeq- vectors. The net conductor voltages and currents of the interconnects can be computed aa sums of the incident and reflected waves, i.e.,

m

[ ~ ( z , t ) I = [uinc(~, t ) l+ [ u r e j ( ~ , t ) l (9)

or

[ ~ ( t , t ) l = [E,] ([kinc(x,t)l+ [ b e j ( t , t ) l ) (10)

where [E,,] is an NxN matrix whose columns are the

voltage eigen vectors and Kinc(t,t) and (E, t ) are the incident and reflected modal intensities, re- spectively. These modal intensities can be obtained by the following set of relations.

4 35

where, these N x N matrices [T$], [&I, [T?], & [ p y ]

are called as the modal transmission and reflection coefficients. These matrices are defined as

[TF] [J%]-’ {TG] (13)

(14)

[.TI = [EuI-l[7Ll (15)

(16)

[PE1 = [E,]-’ [PG] [E,]

El = [JW1 [PLI C E U I

Using these equations one can carry-out time- domain analysis of the high-speed interconnects by

taking their respective terminal networks into con- sideration. Using the principles of “‘Finite element method”, a computer program VIAFEM has been

developed and using the principles of “Modal ana- lysis technique”, VIAMAT has been developed, loc- ally. These packages can be used as CAD tools to characterise the interconnection network of any high-speed electronic systems.

3 Minimisation Of Crosstalk

W i

The cross-talk minimisation techniques can very well be explained with an example. Consider a

multilayer multiconductor structure shown in Fig. 1.

This interconnection structure has eight conduct- ors arranged in two different ayers. The equi- valent electrical representative model parameters of the structure are computed. accurately using VIAFEM. The cross-talk voltages are computed us-

ing VIAMAT by utilising these model parameters. Table I lists these crosstalk voltages. I t is noted

from these results that the conductors 2 and 5 have developed more crosstalk voltages due to the excit- ation applied to conductor 1. These voltages are more than sufficient to drive the circuit connected to malfunction. Hence, it is urgently required to limit these voltages for better functioning of the cir- cuit.

One of the simple strict the crosstalk effect is to increase the spa- cing between conductors and to reduce the coup- ling length. With the advent of MCM technology,

i t is possible to reduce the coupling length, effect- ively. However, due to very large integration of the devices, the interconnection requirement has become very large , it is very difficult to provide large spaci n interconnects by ~ac-

rificing the interconnection density requirements. 3.1 Ground Shielding Concept

Coupling effects on th of the same plane can b cing the shielding g signal conductors as

voltages computed using VIAMAT for this struc- ture are listed in Table I. I t can be noticed t this method of shielding conductors can mini the crosstalk effect on the conductors of the same layer. Electromagnetic coupling effects still persist for the conductors present in the other layers. Fi shows the potential plot for this structure.

Unlike the single layer structures, structures need special attention to mi crosstalk effects in the conductors present in other layers. Shielding ground planes are introdu between signal planes in Fig.3. The correspo listed in Table I.

is purpose, as shown crosstalk voltages are

Table I : Cross-talk voltages shielding

3.2 Negative Shielding Concept The ground shield

vantages. One of the i the technique is that the potential on a shielding conductor is not zero all along the line even if it

36

* c I I 4

175

Ground

Fig 1. Typical MLMC strucure.

0 - Signal Conductor. = cr3 = 2.7

is grounded on both the ends. This is a disadvant- ages factor of the technique because, these shielding ground conductors can not provide good shielding between signal conductors. The other disadvant- age of the technique is that the launched signal of the active conductor gets degraded in the waveform shape with distortion in its rise and fall times. This has motivated in the present work to look for other crosstalk minimisation techniques. In this section, we have proposed the idea of negative shielding to isolate the signal conductors. Consider, Fig.3 again to study the effects of negative shielding. The con- ductors marked as shl , sh2, ..., sh6, are now main- tained either -0.76V or -1.58V to provide negative shielding. These voltages are chosen specifically to represent logic 1 and logic 0 levels for the ECL ICs. As it is already known, there are many ECL ICs for high speed applications, marketed with MECL trade mark. Hence, while designing MCMs for spe-

cific applications, some MECL IC dices can be in- volved along with TTL/CMOS/BiCMOS IC dices. This need not be the case for MCMs alone. Same technique of designing high speed system, can even be employed for multilayer PCBs and other sys- tems. In such cases, the interconnects meant for MECL IC are drawn adjacent to the interconnects meant for CMOS/TTL/BiCMOS ICs. The logic levels of TTL/BiCMOS/CMOS ICs ca: ;2 either 0 V or 5.0 V corresponding on the logic 0 or 1, re- spectively. In the present study, effect of MECL

interconnects maintained at either logic 0(-1.58V)) or logic 1(-0.76V), on the shielding aspects of other signal conductors is studied, Case 1 : Shielding conductors are maintained at -0.76 V In this case the interconnects meant for ECL ICs are maintained at logic 1 level(-0.76). Also, the reference plane ie placed in between the two sig- nal planes, as shown in Fig.3. The finite element package, VIAFEM, has been employed to obtain the model parameters for this interconnection struc- ture

Assuming that the conductors are formed of Cu metal and all interconnects are drawn to a length of 400 mils, VIAMAT has been employed to find the crosstalk voltages. The conductor, marked 1 in the Fig.3 is made active by applying an exci ts tion pulse of amplitude 5V and a frequency of 150 MHz. Then the crosstalk voltages are computed using VIAMAT. These voltages are listed in Table 11. Case 2 : Shielding conductors are maintained at -1.58 V In this case, the shielding conductors shown in Fig.3 are maintained at -1.58V, which is logic '0' for the MECL ICs. In the similar way as case I, the crosstalk voltages are computed for this structure. These voltages are listed in Table 11. It is noted from these results that this technique of shielding is equally effective as compared to Case I.

From this study of negative shielding, it is ob- served that the shielding effects are possible for both the cases logic levels of ECL interconnects. Table I1 also validates the same.

37

55 t

1 1 0

t 4 lo

Fig 3. Typical MLMC struct.with sh.plane.

- Shielding Conductor. €,.I = f r2 = 2.7

1

Table If : Cross-talk voltages with negative

shielding 1 shielding I ding plane

38e-01 I 38e-01 I 38e-01 V * -076 I V = -158 I

shielding I conds. I With Neg. I With Neg. I With shiel- I

19e-04 19404 34e-05 32e-05 4Oe-05 40e-05 42e-02 4Oe-02

6 07e-03 07e-03 7 02e-03 02e-03 8 17e-04 17e-04

15e-05 32e-09 6Oe-12

00 00 00 00

The potential plot of the structure with negative shielding conductors and a ground plane in between signal planes is given in Fig.4.

I t can be noted from this plot that the signal conductors of CMOS/TTL/BiCMOS, and MECL ICs are completely shielded by themselves. The logic levels of the interconnects meant for MECL ICs control effectively the cross-coupling between conductors of the same layer. The cross coupling between conductors of different layers is minimized by the shielding reference (ground) plane placed between the signal planes.

The advantage of this negative shielding tech- nique, against ground shielding technique, is that it significantly increases the wiring channel cap& city, particularly in the design of very large scale ICs, multiclip modules and high speed wiring board

gets distorted for the case where shielding conduct- ors are maintained at ground potential.

4 Conclusion Accountability of the crosstalk in the design of

very high speed VLSI systems and multichip mod- ules is supremely important. Increased coupling, plus faster device response, greatly increase the possibility that the system operation is degraded by crosstalk. Hence, the minimization technique of crosstalk voltage is a very important step in the routing algorithms. The crosstalk voltage can be minimized by increasing the spacing between con- ductors. One can also employ the technique of the shielding the signal lines either by ground conduct- ors or by negative potential conductors. The ground shielding technique gives rise to the distortion of the waveforms launched at active conductors. However, negative potential shielding method does not affect the shape of the waveform. If the MCM structure is designed in such a way as to include some ECL ICs (which are very common in high speed applicct tions) then these negative shielding conductors can be used as signal conductors for the ECL ICs. This aspect, greatly improves the density of intercon- nections, which is a major problem of concern in the design of high speed systems. A typical high speed, high performance multilayer structure has been proposed along with typical dimensions.

5 References 1. Charles J.Barlett et.al “Multichip packaging

design for VLSI based systems” IEEE trans. on CHMT, Dec.1987,PP 647-652.

2. Edward G.Myszka,et.al,“A multichip package for High-speed logic Die” IEEE Trans. on CHMT, Vol-16,Feb.1993, pp 67-73.

designs. I t is observed in the negative shielding 3. S.Y.Kulkarni and K.V.V.Murthy “Character- technique that the shape of the waveform launched at the near-end of the active conductor is undistor- ted. We can recall that the shape of the waveform

isation of high speed VLSI interconnects used in MCMs” Proc. National Conf. on Commu- nications, Kanpur, 1995, pp 180-188.

38

P.P.Silvester and F.L.Ferrari Finite elements for Electrical Engineers” second edition, Cam- bridge Univ. Press, 1990.

S.Y.Kulkarni, K.D.Pati1 and K.V.V.Murthy, “Transmission line model parameters for very high speed VLSI interconnects used in MCMs using FEM with special elements” Proc. Intl. conference on VLSI Design 1995, PP 260-264.

A.R.Djordjvic et.al, “Time-domain response of multiconductor transmission lines” ProcJEEE, vol-75, No.6, June.1987, pp 743-764.

n e o m L r 0 0 )

-rI Lo S W

0 U * B 4 . e m .- N 0

19 B

e 25 5 0 75 100 125 I50 Distance {Microns)

Fig.2 : Potential plot(without Shielding)