1. 1. Santosh Kumar Verma Assistant Professor Department of CSE- JIIT, Noida
2. 2. Qualcomm Snapdragon Introduction Qualcomm Incorporated is an American global semiconductor company that designs and markets wireless telecommunications products and services. Snapdragon is a family of mobile systems on a chip (SoC) by Qualcomm. Qualcomm considers Snapdragon a "platform" for use in smartphones, tablets, and smartbook devices. The original Snapdragon CPU, dubbed Scorpion is Qualcomm's own design. It has many features similar to those of the ARM Cortex- A8 core and it is based on the ARMv7 instruction set . The successor to Scorpion, found in S4 Snapdragon SoCs, is named Krait and has many similarities with the ARM Cortex-A15 CPU and is also based on the ARMv7 instruction set. The majority of Snapdragon processors contain the circuitry to decode high- definition video (HD) resolution at 720p or 1080p depending on the Snapdragon chip Adreno, the company's proprietary GPU series, integrated into Snapdragon chips is Qualcomm's own design All Snapdragons feature one or more DSPs called Hexagon , The multimedia Hexagons are mostly used for audio encoding/decoding, the newer Snapdragons have a hardware block called Venus for video encoding/decoding.
3. 3. Qualcomm Snapdragon Scorpion (CPU) Scorpion is a central processing unit (CPU) core designed by Qualcomm for use in their Snapdragon mobile systems on chips (SoCs). It is designed in-house, but has many architectural similarities with the ARM Cortex-A8 and Cortex-A9 CPU cores. Krait (CPU) Krait is an ARM-based central processing unit included in Qualcomm Snapdragon S4 and Snapdragon 400/600/800 (Krait 200, Krait 300, Krait 400 and Krait 450) System on chips. It was introduced in 2012 as a successor to the Scorpion CPU and has architectural similarities to ARM Cortex-A15.
4. 4. Qualcomm Snapdragon Scorpion (CPU) 10/12 stage integer pipeline with 2-way decode, 3-way out-of-order speculatively issued superscalar execution . Pipelined VFPv3and 128-bit wide NEON (SIMD) 32 KB + 32 KB L1 cache 256 KB (single-core) or 512 KB (dual- core) L2 cache Single or dual-core configuration 2.1 DMIPS/MHz Krait (CPU) 11 stage integer pipeline with 3-way decode and 4-way out-of-order speculative issue superscalar execution Pipelined VFPv4 and 128-bit wide NEON (SIMD) 4 KB + 4 KB L0 cache 16 KB + 16 KB 4-way set associative L1 cache 1 MB 8-way set associative (dual-core) or 2 MB (quad-core) L2 cache Dual or quad-core configurations
5. 5. Qualcomm Snapdragon Semicondu ctor technology CPU instruction set CPU GPU Utilizing devices 45 nm ARMv7 Up to 1.2 GHz quad-core ARM Cortex-A5 Adreno 203 (FWVGA/F WVGA) HTC Desire 600 28 nm LP ARMv7 Up to 1.5 GHz quad-core Krait Adreno 320 (QXGA/1080 p) at 400 MHz Sony Xperia Z Family : S4
6. 6. Qualcomm Snapdragon 4 KiB + 4 KiB L0 cache, 16 KiB + 16 KiB L1 cache and 2 MiB L2 cache UHD video capture and playback Up to 21 Megapixel, stereoscopic 3D dual image signal processor Adreno 330 GPU USB 2.0 and 3.0 Display controller to support various display color models. There are free Linux drivers Qualcomm's Adreno GPU There are free Linux drivers for the Qualcomm Atheros WNICs LLVM (Low level virtual machine) supports the Qualcomm Hexagon DSP Family : 800 series
7. 7. Qualcomm Snapdragon ARMv8-A (64-bit architecture) Dolby Atmos H.265/HEVC encoding/decoding eMMC 5.0 support Native Bluetooth 4.1 support 14-bit dual-ISP for Camera support up to 55MP Wifi 11ac / 11ad support for triple-band (i.e. IEEE 802.11n, IEEE 802.11ac and IEEE 802.11ad (60 GHz). Family : 810
8. 8. Qualcomm Snapdragon Architecture Family : 810
9. 9. Qualcomm Snapdragon
10. 10. ARM Architecture Introduction ARM is a family of RISC-based microprocessors and microcontrollers designed by ARM Inc., Cambridge, England. The company doesnt make processors but instead designs microprocessor and multicore architectures and licenses them to manufacturers . ARM chips are high-speed processors that are known for their small die size and low power requirements. ARM chips are the processors in Apples popular iPod and iPhone devices, HTC, and Samsung devices. The origins of ARM technology can be traced back to the British-based Acorn Computers company. The Acorn RISC Machine became the Advanced RISC Machine . The company dropped the designation Advanced RISC Machine in the late 1990s. It is now simply known as the ARM architecture.
11. 11. ARM FAMILTY
12. 12. PACKAGE: 16/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package. MEMORY: 40 kB of on-chip static RAM 512 kB of on-chip flash program memory. SPEED: 128 bit wide interface/accelerator enables high speed 60 MHz operation.
13. 13. In-System / In-Application Programming (ISP/IAP) via on- chip boot-loader software. Single flash sector or full chip erase in 400 ms and programming of 256 bytes in 1ms. USB 2.0 Full Speed compliant Device Controller with 2kB of endpoint RAM. In addition, the LPC2146/8 provides 8kB of on-chip RAM accessible to USB by DMA.
14. 14. ADC: Two 10-bit A/D converters(AD0 and AD1) provide a total of 14 analog inputs Conversion times as low as 2.44s per channel. DAC: Single 10-bit D/A converter provides variable analog output.
15. 15. TIMERS: Two 32-bit timers/external event counters PWM unit (six outputs) Watchdog timer RTC: Low power real-time clock with independent power and dedicated 32 kHz clock input.
16. 16. SERIAL INTERFACES: I2C-bus: Two Fast I2C-bus with 400 kbit/s Serial communication: Two UARTs (16C550) SPI (Serial Peripheral Interface) and SSP(Synchronous Serial Port) with buffering and variable data length capabilities FAST GPIO: Up to 45 of 5 V tolerant fast general purpose I/O pins in a tiny LQFP64
17. 17. INTERRUPTS: Vectored interrupt controller with 16 configurable priorities and vector addresses. 9 edge or level sensitive external interrupt pins available. 60 MHz maximum CPU clock available from programmable on-chip PLL with settling time of 100 s.
18. 18. OSCILLATOR: On-chip integrated oscillator operates with an external crystal in range from 1 MHz to 30 MHz and with an external oscillator up to 50 MHz POWER SAVING MODES: Idle mode Power-down mode CPU operating voltage range of 3.0 V to 3.6 V (3.3 V 10 %) with 5 V tolerant I/O pads.
19. 19. Features of LPC2148/ARM7TDMI ROM RAM IO PORTS Timers Serial communication USB RAM 512 KB 32 KB 2(P0,P1) 2(32 bit) 2 UART, 2 I2C, 1 SSP ,1 SPI 2 KB
20. 20. PWM modules ADC Interrupts Package DAC 6 2(14 analog inputs) 16 64 PIN(LQFP) 1
21. 21. Types of buses AMBA Bus Local Bus VPB Bus
22. 22. LPC 2144/6/8 consists 45 GPIO functionality in 2 ports P0 & P1. FUNCTION PIN TYPE & DESCRIPTION D+ 10 INPUT/OUTPUT(USB bidirectional D+ line) D- 11 INPUT/OUTPUT(USB bidirectional D- line) XTAL1 62 XTAL2 61 RTXC1 3 INPUT(Input to the RTC oscillator circuit) RTXC2 5 OUTPUT(output to the RTC oscillator circuit) VSS 6, 18 ,25,42,50 VSSA 52 INPUT(Analog Ground: 0 V reference) VDD 23, 43, 51 (power supply) VDDA 7 INPUT(analog power supply) VREF 63 INPUT(A/D Converter Reference) VBAT 49 INPUT(RTC power supply)
23. 23. Programmers Model
24. 24. Instruction Set
25. 25. 3-Satge Instruction Pipeline
26. 26. Optimal Pipelining
27. 27. Branch Pipeline Example
28. 28. Instruction Set Data Processing Instructions Branch Instructions Load-Store Instructions Software Interrupt Instructions Program Status Register Instructions Loading Constants ARMv5E Extensions Conditional Execution
29. 29. ARM Instruction Set Mnemonics Description ADC add two 32 bit values & carry ADD add two 32 bit values AND logical bitwise AND of two 32 bit values B branch relative +/- 32MB BIC logical bit clear of two 32 bit values BKPT breakpoint instructions BL relative branch with link BLX branch with link and exchange BX branch with exchange CDP CDP2 coprocessor data processing operation CLZ count leading zeroes CMN compare negative two 32-bit values CMP compare two 32 bit values EOR logical EOR of two 32 bit values LDC LDC2 load to coprocessor single or multiple 32 bit values LDC LDC2 load to coprocessor single or multiple 32 bit values LDM load multiple 32 bit words from memory to ARM registers
30. 30. ARM Instruction Set - Contd Mnemonics Description LDR load a single value from a virtual address in memory MCR MCR2 MCRR move to coprocessor from an ARM register to registers MLA multiply & accumulate 32 bit values MOV move a 32 bit value into a register MRC MRC2 MRRC move to ARM register or registers from a coprocessor MRS move to ARM register from a status register (cpsr or spsr) MSR move to a status register (cpsr or spsr) from an ARM register MUL multiply two 32 bit values MVN move the logical NOT of 32 bit value into a register ORR Logical bitwise OR of two 32 bit values PLD preload hint instruction
31. 31. ARM Instruction Set - Contd Mnemonics Description QADD signed saturated 32 bit add QDADD signed saturated double and 32 bit add QDSUB signed saturated double and 32 bit sub. QSUB signed saturated 32 bit subtract RSB reverse subtract of two 32 bit values RSC reverse subtract with carry of two 32 bit integers SBC subtract with carry of two 32 bit values SMLAxy signed multiply accumulate instruction ((16 x 16) + 32 = 32 bit) SMLAL signed multiply accumulate long ((32 x 32) + 64 = 64 bit) SMLALxy signed multiply accumulate long ((32 x 16) + 64 = 64 bit) SMLAWy signed multiply accumulate instruction ((32 x 16) >> 16 +32 = 32 bit)
32. 32. ARM Instruction Set - Contd Mnemonics Description SMULL signed multiply long (32x32 = 64 bit) SMULxy signed multiply instructions (16 x 16 = 32 bit) SMULWy signed multiply instructions (32 x 16) >> 16 = 32 bit) STC STC2 store to memory single or multiple 32 bit values from coprocessor STM store multiple 32 bit registers to memory STR store register to a virtual address in memory SUB subtract two 32 bit values SWI software interrupt SWP swap a word/byte in memory with a register, without interruption TEQ test for equality of two 32 bit values
33. 33. ARM Instruction Set - Contd Mnemonics Description TST test for bits in a 32 bit value UMLAL unsigned multiply accumulate long (32 x 32) + 64 = 64 bit) UMULL unsigned multiply long (32 x 32 = 64 bit) Different ARM architecture revisions support different instructions. ARM instructions process data held in registers and only access memory with load and store instructions. ARM instructions commonly take two or three operands.
34. 34. Barrel Shifter Operations Mne. ShiftDescription Shift amount y LSL logical shift left xLSLy #0-31 or Rs LSR logical shift right xLSRy #1-32 or Rs ASR arith. right shift xASRy #1-32 or Rs ROR rotate right xRORy #1-32 or Rs RRX rotate right extended xRRXy none 031 00000 LSL #5 031 00000 LSR #5 031 11111 1 ASR #5, negativ e operand 031 00000 0 ASR #5, positive operand 0 1 031 ROR #5 031 RRX C C C
35. 35. ARM Architecture
36. 36. ARM Architecture Memory Protection
37. 37. Interfacing ARM with IO Devices LED Interfacing 7 Segment Interfacing
38. 38. Interfacing ARM with IO Devices Stepper Motor Interfacing
39. 39. Interfacing ARM with IO Devices LCD Interfacing
40. 40. http://infocenter.arm.com/help/index.jsp?topic= /com.arm.doc.dui0159b/Chdeeech.html Reference for Mobile Hardware Interfacing with ARM based SoC.
41. 41. References 1. https://developer.qualcomm.com 2. Wikipedia-Qualcomm Snapdragon. 3. Qualcomm Snapdragon Benchmark report. 4. www.qualcomm.com//dsp 5. Dsp, Qualcomn hexagon dsp Lucian Codrescu Sr. Director, Technology Qualcomm Technologies, Inc 6. The ARM Instructions Set ARM University Program v1.0 7. [ARM11] ARM Ltd., ARM Architecture Reference Manual, 2011, www.arm.com 8. www.ida.liu.se/~TDTS51/lectures/lectures5-6.pdf 9. ARM7-TDMI-manual-pt2 10. Computer organization and architecture designing for performance ; ninth edition 11. Addison Wesley - ARM System-on-Chip Architecture ; 2Ed 12. http://en.wikipedia.org/wiki/Qualcomm_Snapdragon 13. http://www.arm.com/products/processors/cortex-a/index.php 14. http://www.tomshardware.com/reviews/snapdragon-810-benchmarks,4053-2.html