SMSC KBC1100 Keyboard / System Management Controller January 04,2005.
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Transcript of SMSC KBC1100 Keyboard / System Management Controller January 04,2005.
SMSC KBC1100 Keyboard / System Management Controller
January 04,2005
SMSC KBC1100 Power On Sequence
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KBC1100 Power Domain
VCC0
VCC1
DAC_VCCADC_VCC
ClockBattery Backed Resources
EC_SCIPS2 PortsSFIGPIOPWMCount/TimerFIR/CIRSMbusFan TachometerSPISERIAL PORT
LPC BUSPCI Signal
DAC channel
ADC channel
VCC2
PWRGD
14.318MHzCLOCKI
XTAL1XTAL2
32.768kHz Crystal
PWRGD
VCC1RST#
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KBC1100 Power On Sequence
VCC0
S0 S1 S3 S4 S5
ON ON ON ON ON
VCC1DAC/VCCADC/VCC
ON ON ON ON ON OFF OFF
PWRGD
VCC2 ON ON OFF OFF OFF
Real-time Clock Supply
VCC1RST#
20mS
32.768KHz Crystal14.318MHz Clocki33MHz PCI_CLK
32MHZ_PRO 8051 Int
ON ON ON ON ON
ON ON OFF OFF OFFON ON OFF OFF OFF
ON ON ON OFF OFF
SMSC KBC1100 Shared Flash Interface (SFI)
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SFI Decoder Control ARBEN. SFI Hardware Arbitration Enable.
0 - SFI Hardware arbitration disabled. 1 - SFI Hardware arbitration enabled.
MMC. Memory Map Control Bit. 0 - 2KB ScratchRAM area at 0000h--07FFh in data space is available to the 8051. 1 - 2KB ScratchROM area at 0000h--07FFh in code space is available to the 8051.
HF. HOST_FLASH. This bit is a status indicator for the LPC Host to know that it can perform cycles on the Shared Flash Interface.
1 - 8051 is in IDLE or SLEEP modes. 8051 is running out of Scratch ROM and HOST ACCESS is asserted. The LPC Host must read this bit asserted before it can perform any transactions on the Shared Flash Interface when HW arbitration is disabled.
MCS. STP_CLK bit is read/write. The LPC Host can use the STP_CLK bit to stop the 8051 clock.
1 - 8051 clock is stopped only when the System Reset is deasserted. 0 - 8051 clock can run.
HA. HOST ACCESS. Used to transfer ownership of the Shared Flash Interface between the LPC Host and the 8051.
1 - SFI to LPC Host. 0 - SFI to 8051.
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Mode 1:8051 Owns SFI, Scratch RAM Enabled ARBEN (0) MMC (0) HF (X) MCS (0) HA (0) 8051 is running code out of Flash with the memory map. All 8051 code fetches between
0000h and FFFFh will be read from Flash through the SFI. The 8051 has access to up to 8KB of Scratch data RAM at addresses 0000h - 1FFFh in external RAM space.
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Mode 2:8051 Owns SFI, Scratch ROM Enabled ARBEN (0) MMC (1) HF (0) MCS (0) HA (0) 8051 executes from Scratch ROM while it still has access to Flash. This is the only SFI
Decoder mode, 8051 can safely write the entire Flash device. When reading or fetching 8051 code in this mode, addresses 0000h to 1FFFh will be fetched from Scratch ROM and addresses 2000h to FFFFh will be fetched from Flash. All 8051 code writes (WRS =’1’) to 0000h to FFFFh ROM in this mode will be written to the Flash on the SFI and not Scratch ROM.
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Mode 3 : LPC Host Own SFI, 8051 Clock Stop ARBEN (0) MMC (X) HF (X) MCS (1) HA (1) The LPC Host initiates this mode as follow
Send command to 8051 to enter IDLE. Wait for IDLE bit in 8051 Stop Clock Register to be set. Set STP_CLK bit (8051 Stop Clock register). 8051 clock will stop with STP_CLK set and System Reset is de-asserted. Wait for HOST FLASH bit to be set. Host may access SFI.
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Mode 4 : LPC Host Owns SFI, 8051 Running ARBEN (0) MMC (1) HF (1) MCS (0) HA (1) The 8051 must use the Scratch ROM option to execute code when it does not have access to the Shared
Flash Interface. The 8051 initiates this mode as follows:
Enable Scratch ROM and begin executing code. Set the HOST ACCESS bit. LPC Host waits for HOST FLASH bit to be set. LPC Host may access the SFI.
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Mode 5:LPC Host/8051 Share SFI, Scratch RAM Enabled
ARBEN (1) MMC (0) HF (X) MCS (0) HA (0) This is the default operating mode where the 8051 is running code
out of Flash with the memory map. All 8051 code fetches between 0000h and FFFFh will be read from Flash through the SFI.
The LPC Host can read from Flash at any time. When the LPC Host reads from Flash the 8051 is idled for a short time to allow the LPC Host access to the Flash.
The 8051 has access to up to 8KB of Scratch data RAM at addresses 0000h - 1FFFh in external RAM space.
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Mode 6: LPC Host Owns SFI, 8051 Running
ARBEN (1) MMC (1) HF (X) MCS (0) HA (1) The 8051 initiates this mode as follows
Enable Scratch ROM and begin executing code. Set the HOST ACCESS bit.
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SFI Write Contention Normally the 8051 is executing code from the Flash device and has
ownership of the SFI. LPC Host may require access to the Flash device during this time and an SFI contention exists. 8051 is notified of the LPC Host access request by Host Access interrupt. Write access by the LPC Host to the Shared Flash Interface must be negotiated with the 8051 before FWH or LPC Memory write cycles can occur.
FWH Writes When the LPC Host attempts a FWH Write to the SFI when it does not have ownership of the
interface the KBC1100 will return a valid SYNC (0000b) on the LPC bus as if the write occurred without error. As long as the 8051 retains SFI ownership during this cycle, no LPC Host-related transaction will be seen on the SFI. A FWH write is the result of a serious error and there is no recovery method for erroneous writes of this type.
LPC Host Memory Writes If the Host Wait bit is set and the LPC Host attempts an LPC Memory Write to the SFI when it
does not have ownership of the interface the KBC1100 will drive Long Wait SYNCs on the LPC Bus until the 8051 grants SFI ownership to the LPC Host. If the Host Wait bit is cleared and the LPC Host attempts an LPC Memory Write to the SFI the KBC1100 will return a valid SYNC (0000b) on the LPC bus as if the write occurred without error. No LPC Host-related transaction will be seen on the SFI.
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SFI Read Contention The KBC1100 provides hardware arbitration on the SFI so that the
8051 and the LPC interface can read from Flash without software intervention. Flash write accesses are not affected by the ARBEN bit. When SFI hardware arbitration is disabled, software arbitration of the SFI interface must be used. Hardware arbitration between the 8051 and LPC Host only during read accesses to the Shared Flash Interface.
SFI Hardware Arbitration SFI hardware arbitration is enabled by setting the ARBEN bit. When SFI hardware
arbitration is disabled, SFI access is controlled by the 8051. The SFI hardware arbitration is achieved by stopping the 8051 clock for two
cycles during each LPC access, long enough for the LPC host to read a byte of data from the Flash.
If the 8051 is operating out of scratch ROM, the 8051 can give the LPC host complete access to the Flash but can optionally reclaim the SFI when an 8051 interrupt occurs.
SMSC KBC1100 Serial Peripheral Interface (SPI)
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SPI Full Duplex Mode In Full Duplex Mode, serial data is transmitted and received
simultaneously by the SPI master over two separate data transmission lines.
Every data exchange is a simultaneous transmit and receive operation. Data shifted out of the master is shifted into the slave and data shifted out of the slave is shifted into the master synchronized by the master-driven SPCLK.
SPI Master SPI Slave
SPDOUT
SPDIN
SPCLK
SPIMODE = 0
SPIDR
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SPI Bidirectional Mode SPI data can be transmitted and received over a single data line
using Bidirectional mode. Input and output serial data share the SDOUT pin. The Software driver must properly drive the BIOEN bit and store
received data depending on the transaction format of the specific slave device.
BIOEN - Bidirectional Mode Output Enable When BIOEN is '0', the SDOUT signal is configured as the serial data input. When
BIOEN is '1', the SDOUT signal is configured as the serial data output.
SPI Master SPI Slave
SPDOUT
SPDIN
SPCLK
SPIMODE = 1
SPIDR
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SPI Interface Description Clock sources
32Mhz_PRO, 48_MhzRO and PLL SPI Pins
SPI block can be switch from the Primary Port to the Secondary Port and the last state of the Primary SPI Port's buffer mode, pin direction and pin logic state of the SPCLK, SPDOUT and SPDIN functions persists on the LGPIO70, LGPIO60 and LGPIO64 pins. The secondary port is on GPIO74, GPIO73 and GPIO39 pins.
SPDOUT - Serial Peripheral Data Out• Serial data output from the KBC1100 SPI interface. When the interface is configured for
Bidirectional mode, SPDOUT is used for SPI serial I/O. SPDIN - Serial Peripheral Data In
• Serial data input to the KBC1100 SPI. When the interface is configured for Bidirectional mode, SPDIN is unused.
SPCLK - Serial Peripheral Clock• Serial clock driven by the KBC1100 SPI (master) and connected to all SPI slaves.
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SPI Data Clock Timing
MSB 6 5 4 3 2 1 LSB
LSB MSB654321
nBUSY bit
SPIDONE bit
SPCLK
SPDOUT/SPDIN
RCLKPH CLKPOL TCLKPH
0 0 0
1 0 1
0 1 0
1 1 1
TransmitReceive
LSBF = 0
LSBF = 1
TCLKPH - Transmit Clock PhaseCLKPOL - SPI Clock PolarityRCLKPH - Receive Clock Phase
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SPI Baud Rate
CLKSRC=0
32Mhz_PRO
48Mhz Clock
CLKSRC=1
CLKEN
Clock Scale SPICS1/0 /4,6,12
Clock Divider SPICD2-0/1,2,4,8,16,32,64,128
SPI Baud Rate 48Mhz Clock
• SPICS0 and SPICS1 bits in the SPI Baud Rate register can be used to scale the input clock (4 MHz, 8 MHz or 12 MHz) to the SPI Baud Rate Generator.
32Mhz_PRO• SPICS0 and SPICS1 bits are ignored and the 32Mhz_PRO clock output is directly
connected to the SPI Baud Rate Generator. The divisor bits SPICD0, SPICD1 and SPICD2 in the SPI Baud Rate register
can be programmed to divide down the clock from 1 to 128.
SMSC KBC1100 Mailbox Registers Interface
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Mailbox Interface Registers Block Diagram
HOSTCPU
805132 8 bits Mailbox Registers
MBX Primary Base Address High/low ByteActivate=1
MBX access port addresses decode
MBX INDEXMBX DATA
System-to-8051 Mailbox register 0
8051-to-system Mailbox register 1
Flash Recovery
ESMI source register
UART1 FIFO Control registerFan Control Register
8051STP_CLK
PWM 0-2 Frequency Multiply
ESMI mask register
IR data register
INT3
SMI
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System/8051 Interface Registers Mailbox Register 0, System-to-8051, and Mailbox Register 1, 8051-
to-System, are specifically designed to pass commands between the host and the 8051. Mailbox Register 0/1 are not dual-ported, so the System BIOS and Keyboard BIOS must be designed to properly share these registers.
Mailbox Register 0: System-to-8051 If enabled, an INT3 will be generated when the System writes to Mailbox Register
0. The interrupt source bit will be cleared when the 8051 reads this register. After reading Mailbox Register 0, the 8051 can clear the register to “00H” by a dummy write to inform the host that the register contents have been read.
Mailbox Register 1: 8051-to-system If enabled, an SMI will be generated when the 8051 writes to Mailbox Register 1.
The SMI interrupt will be cleared when the host reads this register. After reading Mailbox Register 1, the system can clear the register to “00H” by a dummy write to inform the 8051 that the register has been read.
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LPC Host Access SFISystem is fully powered & the 8051is running
keyboard code. System Reset deasserted and STP_CLK = 0
The host issues a defined command to put the 8051 into Idle mode
8051 goes into idle mode
The host sets STP_CLK = 1 and combined with System Rests deasstered causes the 8051 clock to stop
The host can operate as needed.
When done, the host resets STP_CLK = 0
8051 IRQ? 8051 wakes from idle modeand starts from where it left off
N Y
NOTE: in order to leave idle mode the 8051 must receive an interrupt;typically a software timer interrupt
will be used
LPC Host Sequence to Stop the 8051
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8051 Stop Clock Register IDLE
When the IDLE bit is 0, 8051 is not in idle mode When the IDLE bit is 1, the 8051 is in idle mode. The IDLE bit is read-only.
HOST_FLASH This bit is a status indicator for the LPC Host to know that it can perform cycles on
the Shared Flash Interface. Host_Flash is set, 8051 is in IDLE or SLEEP modes. 8051 is running out of
Scratch ROM and HOST ACCESS is asserted. The LPC Host must read this bit asserted before it can perform any transactions on the Shared Flash Interface when HW arbitration is disabled.
STP_CLK When the STP_CLK bit is 1, the 8051 clock is stopped only when the System
Reset is deasserted; when the STP_CLK bit is ‘0’, the 8051 clock can run.
SMSC KBC1100 BudgetBus Controller
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SMSC BudgetBus Controller Data Format Packet Format for temperature
1 bit 3 bits 11 bits
Sensor Type Sensor Number Sensor Reading
Sensor Type = 0Temperature Data Format
0 000b-111b 11 bits
Temperature data is transmitted in two’s compliment form with a decimal offset of 64
Number portion (Two's complement of Bits 10-3) + Fractional portion (Two's complement of Bits 2-0) + 64 = Actual temperature reading
Bits 10-3 : number portion bits 2-0 : fractional portion
Sensor Data Whole Number Register
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SMSC BudgetBUS Sensors EMC1201
Sensor number• 000 - internal temperature
EMC1202 Sensor number
• 000 - internal temperature• 001 - remote 1
EMC1203 Sensor number
• 000 - internal temperature• 001 - remote 1• 010 - remote 2
8
5
1
2
3
DP1
DN2
VDD
GNDDN1
4
6
7
DP2 SMSCBBus
EMC1203
5
4
1
2
3
Vdd
GND
NC
NC
SMSC BBus
EMC1201
5
4
1
2
3
Vdd
GND
SMSC BBus
EMC1202
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SMSC BudgetBus Controller Data Format Packet Format for voltage
Voltage data transmit in 10 bits or 8 bits binary • Bit 10 is reserved bit.• In 8 bits binary format, bits 0 and 1 are always zero
The voltage formula• V measurement = ( V max * Sensor Reading ) / 1024• V max is the maximum voltage that can be read by the Voltage Sensor
1 bit 3 bits 11 bits
Sensor Type Sensor Number Sensor Reading
Sensor Type = 1Voltage Data Format
1 000b-111b 11 bits
10 Bits Voltage Data
8 Bits Voltage Data
0
000
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Two's compliment of number and fractional portion
Number portion MSB bit indicate the sign of the number
• 0 : positive number• 1 : negative number
Invert the digits. 0 becomes 1, 1 becomes 0. Then add 1. Add sign
Fractional portion Any bit after the point represents a number 2 raised to a negative power. This is how
the fractions are represented.
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SMSC BB0/1 Thermal Events Routing Diagram
Sensor0/1 data acquisition
8 Reading BufferFIFO
HWPRO ThermalThreshold Register
HTEVEN bitEnable
Sensor Data Register
INT4(17Ch)-HWPROWakeUp(10)-HWPRO
HW_PROTECT# Pin
Bus=0/1
EN0/1=1
FIFO0TR INT4(174h)-SENSORWakeUp(12)-SENSOR
SentinelAlert ThermalThreshold Register
INT4(178h)-SA_OVRTEMPWakeUp(13)-SA_OVRTEMP
SentinelAlertlogic DAC[2:0]
SA_GPIO[0:1] TEVEN bit Enable
POL ><
TTEN bit EnableWatchdog Timer WDRST bit
WDTEN bit
Reset
Enable
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SMSC Budget Bus 0/1 Thermal Events Interrupt SENSOR, Sensor Reading Received, INT4 Priority 1 174h
FIFO0TR (FIFO Threshold 0), select 1-8 sensor readings. These bits set the interrupt threshold for SMSC BudgetBus 0. An interrupt is signalled when the FIFO threshold is reached.
HWPRO, Hardware Protect Event Detected, INT4 Priority 3 17Ch A thermal event interrupt occurs when a temperature reading is greater than or equal
to the value programmed in one of the Thermal Threshold registers (HWPRO_TT). Temperature readings from both BudgetBuses are compared against the Thermal Threshold registers when they are pushed into the FIFO.
SA_OVRTEMP, SMSC SentinelAlert! Thermal Event Detected, INT4 Priority 2 178h
When a temperature reading is greater than or equal to or lower than ( depend on POL) the value programmed in SentinelAlert! Thermal Threshold (SA_TT) Registers. Temperature readings from both BudgetBuses are compared against the SentinelAlert! Thermal Threshold (SA_TT) Registers when they are pushed into the FIFO.
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SMSC Budget Bus 0/1 Thermal Events Wake-Up Event SENSOR, Sensor Reading Received, Count 12
FIFO0TR (FIFO Threshold 0), select 1-8 sensor readings. These bits set the wake-up event threshold for SMSC BudgetBus 0. An wake-up event is signalled when the FIFO threshold is reached.
HWPRO, HW_Protect Thermal Event, Count 10 A thermal event occurs when a temperature reading is greater than or equal to the
value programmed in one of the Thermal Threshold registers (HWPRO_TT). Temperature readings from both BudgetBuses are compared against the Thermal Threshold registers when they are pushed into the FIFO.
SA_OVRTEMP, SMSC SentinelAlert! Thermal Event Detected, Count 13
When a temperature reading is greater than or equal to or lower than ( depend on POL) the value programmed in SentinelAlert! Thermal Threshold (SA_TT) Registers. Temperature readings from both BudgetBuses are compared against the SentinelAlert! Thermal Threshold (SA_TT) Registers when they are pushed into the FIFO.
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BudgetBus FIFO Status & Sensor Data BudgetBus FIFO Status Register is used to report the status of the
internal FIFO OVFL1/0
• FIFO Overflow, This bit is set if the BudgetBus FIFO Overflow FIFO1/0
• FIFO Space, these bits report the number of sensor reading present in the FIFO for BudgetBus
Sensor Data register report sensor data to the 8051. The 8051 selects which busses data is read from the Sensor Data Register by writing the BUS field in the SMSC BudgetBus Control Register. An interrupt can be generated each time the internal FIFO reaches the threshold set in the FIFO Threshold Register.
Sensor data is popped from the internal FIFO when the Sensor Data Whole number register is read. To ensure that the data is correct, the Fractional Sensor Data register must be read before reading the Sensor Data Whole Register.
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Temperature Sensor Number Calculate Sensor Data Whole Number Register (Read second)
SD• Sensor Data. These bits return the upper 8 bits of the temperature data (11-bit sensor
reading) and represent the whole number portion of the temperature reading. Fractional Sensor Data Register (Read first)
SD• The Fractional Sensor Data register contains the lower 3-bits of the 11-bit sensor reading.
This register determine the fractional portion of the temperature reading. Actual temperature reading = Number portion (Two's complement of Bits 10-3) + Fractional portion (Two's complement of Bits 2-0) + 64 TMPV
Temperature Threshold Violation. This bit is set when a temperature reading violates the Thermal threshold set in the Thermal Threshold Registers.
SNTYP Sensor Type. 0:Temperature reading. 1:Voltage reading.
SN Sensor Number. These bits return the 3 bits sensor number.
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SMSC BudgetBus Control Register BudgetBus Control Register is used to control the behavior of the
SMSC BudgetBus controller TEVEN
• Thermal Event Enable. Enables the comparison of temperatures against the Thermal Threshold Registers for signaling Thermal Events
HTEVEN• Hardware Thermal Event Enable. Enables the comparison of temperatures against the
HWPRO Thermal Threshold Registers for signaling Thermal Shutdown Events BUS
• Select BudgetBus 0 or 1 temperature data is visible in the Sensor Data Register– 0 - Bus 0 Sensor Data– 1 - Bus 1 Sensor Data
EN1/0• SMSC BudgetBus 1/0 Enable. Enable an disables the SMSC BudgetBus Controller from
receiving data on SMSC BudgetBus 1/0. When the bus is disabled, the bus is placed in power down state
– 0 - SMSC BudgetBus 1/0 disabled– 1 - SMSC BudgetBus 1/0 enabled
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Thermal Shutdown Temperature Thermal shutdown temperature calculate
Number portion : Two's complement of [binary (Shutdown temperature -64)]+1 Fractional portion : Two's complement of fraction
HWPRO Thermal Threshold Registers HWPRO Thermal Threshold (HWPRO_TT) registers are used to set the thermal
shutdown temperature. The default value of this register is 90°C. HWPRO_TT Whole Number Register
The HWPRO Thermal Threshold Whole Number register contains the upper 8-bits (number portion) of the 11-bit temperature threshold.
HWPRO_TT Fractional Sensor Data Register TT. The HWPRO_TT Fractional Sensor Data register contains the lower 3-bits
(fractional portion) of the 11-bit temperature threshold.
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SentinelAlert Thermal Threshold SentinelAlert Thermal Threshold (SA_TT) Registers are used to set
the thermal threshold that cause interrupts to the 8051 SA_TT Whole Number Register
SA_TT Whole Number register contains the upper 8-bits of the 11-bit temperature threshold.
SA_TT Sensor Data Register The SA_TT Fractional Sensor Data register contains the lower 3-bits of the 11-bit
temperature threshold. This register can be used to program the fractional portion of the temperature threshold.
POL. Thermal Threshold Polarity. This bit controls the polarity of the Thermal Event.
• 0 : Temperature >= Thermal Threshold• 1 : Temperature < Thermal Threshold
SMSC SentinelAlert! Control Register TTEN, temperature Threshold Enable. This bit controls if a Thermal Event causes
the KBC1100 to enter SMSC SentinelAlert! Mode.• 0 = Thermal events do not cause SMSC SentinelAlert! Mode• 1 = Thermal events cause SMSC SentinelAlert! Mode
SMSC KBC1100 SentinelAlert! Controls
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SMSC KBC1100 SentinelAlert! control Enter SMSC SentinelAlert! Controls
The Watch-Dog timer expires• A programmable watchdog timer is used to monitor the 8051. The watchdog timer can
be set from 25 milliseconds to 6.4 seconds. The watchdog is restarted anytime the 8051 writes the WDRST bit in the SMSC SentinelAlert! Control Register.
External thermal diode sensors exceed critical temperature limits• Temperatures are monitored by the SMSC BudgetBus Controller using the SMSC
SentinelAlert! Thermal Threshold (SA_TT) Registers.
Action in SMSC SentinelAlert! Controls 4 DAC outputs can be forced to minimum or maximum output voltage under
program control SA_GPIO pins can be programmed as an input or as an output and forced High or
Low.
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Watchdog Timer Setting SMSC SentinelAlert! Control Register
WDRST, Watchdog Timer Reset. Writing this bit restarts the Watchdog Timer. WDTEN, Watchdog Timer Enable. This bit enables the Watchdog timer. If the timer is
not restarted before the timer expires the KBC1100 enters SMSC SentinelAlert! Mode. If the Watchdog timer is disabled it can not cause the KBC1100 to enter SMSC SentinelAlert! Mode.
Watchdog Timer Length = (WDTLEN+1)x25mS 25mS to 6.4 seconds WDTLEN, Watchdog Timer Length Register is used to select the length of timer. The
Watchdog Timer Length Register controls the length of the timer in 25ms steps. Time remaining = (WDTCNT +1) x 25ms
WDTCNT, Watchdog Timer Count, these bits return the time remain before the timer expires.
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SMSC SentinelAlert! Output State SentinelAlert! output control
SentinelAlert! DAC State Register• DAC3-0 SASTATE. DAC3-0 SMSC SentinelAlert! State. These bits control the SMSC
SentinelAlert! State of DAC Channel.• 00 - Maintain current state• 01 - Tri-state output• 10 - Force Output Low• 11 - Force Output High
SentinelAlert! GPIO State Register• SA_GPIO1-0 status. SA_GPIO1-0 SMSC SentinelAlert! State. These bits control the
SMSC SentinelAlert! State of the SA_GPIO1-0 pin.• 00 - Maintain current state• 01 - Tri-state output• 10 - Force Output Low• 11 - Force Output High