SMIC R&D/Power Aug 20 2014

SMIC Power Technologies For PMU Applications

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Outline

PMIC Applications

Power Devices Emphasis and Challenge

SMIC Technologies Development Trend

Design Supporting (Model, IPs, HV IO…)

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PMIC Opportunities in Today’s Market

Portable markets – Mobile handsets – Tablets – Ultrabook

LED driver market – Mobile/TV backlighting – Signal – General illumination

AC-DC – Battery chargers – Appliances – Power supplies

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12%

10%

10%

8% 8% 7%

4%

2% 2% 2% 2%

2% 1% 1%

1% 1% 1%

1% 1%

0% 25%

STMicroelectronics

TexasInstruments

Qualcomm

NXP

Infineon

RenesasElectronics

Power Management IC Market

Power IC MKT and trend Mobile PMIC players

Power IC is about 10% of IC TAM, and diversified among players

Consumer market contributed major volume (>60%) with high increasing rate

Power IC major players

~$30B

Others ~25%

Challenge Looking for high quality, high performance , lower cost solutions .

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PMIC Applications Split by Voltage/Current

* Not including data processing , automotive field

WLED Driver for FPD BL in handset DSC, NB,TV

Driver for ultrasonic,

MEMS Adaptors

LED Lighting Ballast, motor driver

5V 12V 20V 40V 100V 200V 500~800V

0.5A

1A

5A

10A

50A

LDO

USB/AP/Audio Speaker in Handset, MP3,DSC

LED Display

Main I/O Power in NB

Main I/O Power in Server, WS, DT

Memory & Graphic in Server, WS, DT

CPU in Server, WS, DT (I>30A)

Memory & Graphic in NB

CPU/GPU in NB (I>20A)

Main/ I/O/ FPD in LCD TV

Lighting LED Driver & Automotive

Telecom Driver/PoE EL lighting

high volume

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SMIC Power Technology Revenue

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PMIC accounts for 20% SMIC 2013 revenue .

0.35µm BCD is in production for 6 years with over 800K wafer shipment.

0.18/0.153µm BCD mass production > 4 years with over 1.5M wafer shipment.

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No clear and generic roadmap, guideline for “MTM” Challenge =Opportunity

More than Moore: diverse , features size is not key factor, application specific performance is more critical

ITRS 2011

PMIC Process: One Tech of MTM Category

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Logic devices scaled smaller to even smaller sized by nm

Power devices with much more structures still sized by um

10VLDMOS 30VLDMOS

Logic devices and HV power devices with different emphasis

Logic Devices vs HV Power Devices

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Power Devices Focus

Power (Muscle)

Analog (Sense)

Digital (Brain)

1. Ron/BV

2. Isolation

3. Reliability

4. FOM ~ Specific application.

1. CMOS gm, Rout,

2. BJT gain, EA, BV

3. Res, Cap linearity, Vcc/Tcc.

4. Noise, matching,

5. Trim :fuse, OTP, MTP..

Considerations for power devices

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HV LDMOS Device Challenge

Parameters to define LDMOS : ― Electrical: Vgs, Vds, Vs_sub, Vd_sub, Ron/BV, Ron/Qg, SOA etc ― Physical: much more layout parameters depended. (no generic structure)

GT

P- Sub

N+

Drift

S

Drain STI

Body

Vgs=LV/MV Vds=HV

Drain + STI

X1 X2 X3 X4

X5

Deep well

D

Iso_STI

Pick up Source+

B GR

GR

X6

Pick up

HVLDMOS

Parameters to define CMOS: ― Electrical : Vop (Vgs=Vds), Vt, BV, Ion/Ioff, …. ― Physical: W/L, Well (almost standardized structure)

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Typical HV LDMOS Id-Vd Curve

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0

100

200

300

400

500

0 5 10 15 20 25 30 35 40 45

ID(u

A/um

)

Vds(V)

NLDMOS SOA

VG=0

VG=1

VG=2

VG=3

VG=4

VG=5

VG=6

VG=7

VG=8

Ron

Rout

Quasi-Saturation

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……

Short Term (Dev.

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0.18um BCD: – High BV up to 60V

– Even low Ron for switching (Si data will be ready in Q4/14)

PMU for cellphone

50mΩ.mm2/70V

Switching Charger etc.

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HV Devices on Baseline: Low Ron

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0.18um 1.8/5V: 5V devices enhancement for power switch

Enhanced

Standard Enhanced

Standard

Developing Power Devices in 0.18um PMU

Parameter Unit Standard Device Enhanced

Device Difference

Pitch um 1.1 0.89 -19%

Vthi V 0.82 0.904

Idlin uA/um 62 93.82 51%

Ron mohm*mm2 1.85 0.95 -49%

Idsat uA/um 580 712 23%

Ioff pA/um 0.1 0.1

BV V 11 11

Parameter Unit Standard Device Enhanced

Device Difference

Pitch um 1 0.84 -16%

Vthi V -0.84 -1.097

Idlin uA/um -15.8 -25.74 63%

Ron mohm*mm2 6.58 3.26 -50%

Idsat uA/um -280 -426 52%

Ioff pA/um -0.1 -0.1

BV V -9 -10

5V NMOS 5V PMOS

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65nm LP: 1.2/2.5V process 5V LDMOS enhancement for power

Developing Power Devices in 65nm LP

Parameter Unit Standard Device Enhanced

Device Difference

Pitch um 0.83 1.16 40%

Vthi V 0.55 0.55

Idlin uA/um 24.4 45.7 87%

Ron mohm*mm2 3.41 2.54 -26%

Idsat uA/um 440 464 5%

Ioff pA/um 0.44 0.29

Rout@Vg=2V ohm 2,381 11,111 367%

BV V 10.8 10.8

Parameter Unit Standard Device Enhanced

Device Differen

ce Pitch um 0.83 1.16 40%

Vthi V -0.55 -0.55

Idlin uA/um -8.5 -18.7 120%

Ron mohm*mm2 9.76 6.2 -36%

Idsat uA/um -245 278 -213%

Ioff pA/um -0.41 -0.35

Rout@Vg=-2V ohm 1,503 7,142 375%

BV V -10.8 -10.8

5V LDNMOS (Vgs=2.5V) 5V LDPMOS (Vgs=2.5V)

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Accuracy HV power devices modelling

Full set of design documents

― DRC/LVS/xRC

― PDK (flexible p-cell)

Rich logical compatible IP re-usable

― Standard cell, SRAM, IO…

Customization IP supporting

― 3rd part OTP…

― In house e-Fuse…

― Applications’ specific HV IO…

LV Clamp with DNW

HV Clamp

25C Si& fitting

125C Si& fitting

Power Technology Design Supporting

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Work Together, Win the Future

Process and design mutual understanding & interaction is

essential for power analog products.

Virtual IDM: welcome CTM as partner join-in at development stage.

Flexible and optimized solutions for target applications

MTE: Significantly reduce chip size for logic intensive design

HVBCD: Less mask layers for high voltage, logic less design

SVX LDMOS: embedded high performance extendable voltage power

devices with excellent isolation.

Thank You