“Smart Me” for Smart Life, Smart Lifestyle
Transcript of “Smart Me” for Smart Life, Smart Lifestyle
“Smart Me” for Smart Life, Smart Lifestyle – Driving Internet of Things Revolution…
March 18, 2015
Weili Dai, President and Co-Founder
Marvell Technology Group
NASDAQ: MRVL
Our Vision …
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Smart Me
Three Fundamental Technical Challenges
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Size
Power Cost
Marvell Groundbreaking Solutions
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MoChi™ (MOdular CHIp)
Build Chips in Lego-like Format
FLC® (Final-Level Cache)
Redefine Main Memory Hierarchy
L3 Cache
L2 Cache
L1 Cache
SSD
HDD
DRAM
CPU
Outdated Computing Architecture
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1980’s 1990’s 2000’s 2010’s
Decades
Perf
orm
an
ce
C
ost
CPU CPU CPU CPU
L4 DRAM
L3 Cache
L2 Cache
DRAM (64~245KB)
Out of Control
L1 Cache
L3 Cache
L2 Cache
L1 Cache
L2 Cache
L1 Cache
L1 Cache
DRAM (2~6MB)
DRAM (1~4GB)
DRAM (8~16GB)
Clue on How to Solve DRAM Explosion
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Most processes are idle, yet in aggregate, take up a lot of DRAM space
Revolutionary FLC® Memory Architecture
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CPU
Conventional SSD
Main Memory
Stage 1
Stage 2
Final-Level Cache (FLC) Smaller, Faster, Lower-Power DRAM
High Speed
HDD
L3 Cache
L2 Cache
L1 Cache
L3 Cache
L2 Cache
L1 Cache
DRAM (8~16GB)
DRAM (128MB~1GB)
L3 Cache
L2 Cache
L1 Cache
SSD
HDD
DRAM or DDRAM
HS-DRAM
CPU CPU
Now Future
FLC vs. Conventional Memory Hierarchy
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Cover only active portion of small # of working
data sets (minimum: 1)
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Much Smaller DRAM (< 1/8)
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Much Lower Power (< 1/4)
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Higher Speed
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Can be co-located next to CPU
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Can be easily flushed out to SSD for complete
power-down
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Fast Wake-up
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Total size has to cover all working data sets
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Final Level Cache (FLC) Conventional Main Memory (DRAM)
FLC Extends Battery Life
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w/ FLC: 0.5GB w/o FLC: 2~4GB
Energy required to retain DRAM states ~ 10× Increase in Standby Time
Battery capacity extremely limited ~ 100× with MRAM FLC in the Future
Modern OS requirements for DRAM
Key Challenge for Wide Adoption: Very Short Battery Life
FLC Saves Memory Cost
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~1/10 capacity of main memory DRAM sufficient for DRAM FLC
System cost savings from FLC architecture = Total DRAM market of ~ $44B × 0.5 x 0.9
(assuming 50% FLC adoption) ~$20B
Total potential annual savings for end users ~$40B
Implications for Memory Industry • With FLC, many new applications of DRAM will emerge
• Mainstream main memory will use Flash NAND (especially 3D)
• FLC will enable new memory technologies like RRAM
FLC Reduces Format Factor
• Half the operating power
• Half the battery size
• 10× standby battery life
• Half the cost
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FLC Enables Future Supercomputing
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“Smart Me” Energy Efficient
Data Center
FLC enables larger main memories
(10’s of TB vs. 100’s of GB)
Large server room reduced to one cube
FLC Lowers IDC Energy Consumption
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• The FLC memory architecture
potentially saves 50% of power
consumption of computers
• That’s a 2.5% decrease in world
energy consumption!
• IT infrastructure estimated to
consume 10% of world
energy
• Assume 50% of this energy
use is from running and
cooling computers/servers
MoChi™ (MOdular CHIp)
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Single-Die SoC
(Conventional)
MoChi Blocks
(Concept like Lego®)
MoChi and Virtual SoC (VSoC™)
• No Need to change existing software for single-chip SoC designers
• Virtual SoC offers convenience of 1 device & hides complexity
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MoChi Interconnect
MoChi’s (Access common resource such as DRAM)
(Concept like Lego®)
MoChi Applications Example – Smartphone
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Application
Processor
MoChi
Step-
Pyramid
DRAM
(FLC)
Mo
Ch
i In
terc
on
ne
ct
LTE MODEM
MoChi
WiFi
MoChi
CPU GPU
AP MoChi Module
1x1/2x2
802.11n/ac
R9/R10/R11/R1216
8GB/16GB/32GB
SSD
(Main Memory)
MCM of AP MoChi and
DRAM FLC next to
reduces package pins,
simplifying PCB design
Product features are customizable by selecting different flavors of MoChi’s
4/8 of 32b/64b Cores
2x2Gb
MoChi Applications Example – Laptop
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Application
Processor
MoChi
Step-
Pyramid
DRAM
(FLC)
Mo
Ch
i In
terc
on
ne
ct
LTE MODEM
MoChi
CPU GPU
High-End
AP MoChi Module 1x1/2x2
802.11n/ac
R9/R10/R11/R1216
4x2Gb
8GB/16GB/32GB
SSD
(Main Memory)
MCM of AP MoChi and
DRAM FLC next to
reduces package pins,
simplifying PCB design
South Bridge MoChi is added to high-end AP, MODEM, and WiFi MoChi’s
WiFi
MoChi
SB
MoChi
USB 3.0
PCIe SATA
GE
(Optional)
8 of 64b Cores
Kinoma Open Source Announcement
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JSXS
JavaScript
Engine
Our Vision, Delivered …
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L3 Cache
L2 Cache
L1 Cache
SSD
HDD
DRAM
CPU
FLC® (Final-Level Cache) MoChi™ (MOdular CHIp)
Driving down Power, Cost and Size
Enabling
Smart Me