Small but Nasty Logic Synthesis Examples

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1 Small but Nasty Logic Synthesis Examples Petr Fišer, Jan Schmidt, CTU in Prague {fiserp,schmidt}@fel.cvut.cz LUT mapping examples by Cong and Minkovich Proposed method to construct nasty synthesis examples from existing circuits Possible sources of nastiness

Transcript of Small but Nasty Logic Synthesis Examples

Page 1: Small but Nasty Logic Synthesis Examples

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Small but Nasty Logic Synthesis Examples

Petr Fišer, Jan Schmidt, CTU in Prague{fiserp,schmidt}@fel.cvut.cz

• LUT mapping examples by Cong and Minkovich

• Proposed method to construct nasty synthesis examples from existing circuits

• Possible sources of nastiness

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LUT mapping examples

Jason Cong and Kirill MinkovichVLSI CAD Lab, UCLA

J Cong and K Minkovich, ““““Optimality study of logic synthesis for LUTOptimality study of logic synthesis for LUTOptimality study of logic synthesis for LUTOptimality study of logic synthesis for LUT----based based based based FPGAsFPGAsFPGAsFPGAs”””” (2007). IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 26 (2), pp. 230-239. Postprint available free at: http://repositories.cdlib.org/postprints/2376

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Example construction

circuit

core circuit

replication

Boolean network

Boolean network

circuit SOP

collapse and decompose/balance

minimum #LUT actual #LUT

actual #LUTcomparisoncomparison

proof

mapping

synthesis

mapping

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Core circuit and replication

• Several rows of core circuits

• Connection makes a path from each primary input to each primary output

G5 G5

G25

primary inputs

primary outputs • G5– 5 inputs, – 5 outputs– Boolean network: 24 nodes of 2 inputs

– proven optimum mapping is 7 4-LUT

• G6 similar

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Tested synthesis processes

• Optimizing for area

• 4-LUT architecture

ABCBerkeley

DAOmapUCLA

ISE 7.1iXilinx

Quartus 5.0Altera

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LEKO

• Logic synthesis Examples with Known Optimals

• Proof: optimum mapping of the composite circuit is the composition of core circuit mappings

• Input: Boolean network of composite circuit

• Tested: the LUT mapping process

• Metrics: LUT#

• Average result: 1.15 times the optimum

• Worst result: 1.25 times the optimum

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LEKO benchmarks

circuit

core circuit

replication

Boolean network

Boolean network

minimum #LUT actual #LUT

comparison

proof

mapping

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LEKU

• Logic Examples with Known Upper bounds

• Describe by SOP (collapse) and:

– decompose to AND–OR gates (CD benchmarks)�

– decompose to AND–OR gates as a separate circuit for each output (CD’ benchmarks)�

– balance the AND–OR trees (CB benchmarks)�

• Input: a circuit implementing the SOP

• Tested: the entire logic synthesis process

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LEKU - Logic Examples with Known Upper bounds

circuit

core circuit

replication

Boolean network

Boolean network

circuit SOP

collapse and decompose/balance

minimum #LUT actual #LUT

comparison

proof synthesis

mapping

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Results

4.62.7G25 decomposed to AND-OR circuit, balanced

50472G25 decomposed to separate AND-OR circuit for each output

436148G25 decomposed to AND-OR circuit

Worst ratio

Best ratio

Benchmark

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Reactions

• The circuits are too large to be realistic

• Global optimization is missing, the tools cannot rediscover the original structure

• Improvements have been found:

– use external don't cares

– map to 5-LUT first, then to 4-LUT; sometimes gives good results

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Proposed circuits

x1

corecircuit

xn

y1

ym

XOR

•Any core circuit, any formalism•Any size-related metrics•Upper bound: the size of the core circuit plus the size of the XOR tree as implemented by the same synthesis process (or any other synthesis) �

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Construction

Σdesired metricdesired metric

SOP

and collapsecombine

circuit

any formalism any formalism

core circuit XOR tree

LEKU comparison

desired metric

SUE or SUE,

synthesisany other any other

synthesis,or manual

SUE

SUE: Synthesis Under Evaluation

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Results: MCNC

0.01

0.1

1

10

100

1 10 100 1000 10000

Ac

tual

siz

e i

n L

UT

s t

o u

pp

er

bo

un

d

Upper bound, LUTs size →

nastiness →

alu1 b4in6

misex3cpdc

nasty

neat

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Between the core circuit and the complete circuit

x1

corecircuit

xn

y1

ym

XOR

•outputs divided into disjoint groups

•randomly or by a 'clever' process

•one group: the complete circuit

•m groups: the core circuit

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Nastiness is robust

0 1 2 3 4 5 6 7 80

50

100

150

200

250

300 alu1

LU

Ts

Parity bits

0 1 2 3 4 5 6 7 80

20

40

60

80

100 alu2

LU

Ts

Parity bits

0 1 2 3 4 5 6 7 8 9 100

5

10

15

20

25

30

5xp1

LU

Ts

Parity bits

0 5 10 15 20 250

50

100

150

200

250

duke2

LU

Ts

Parity bits

nasty neat

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The beauty of alu1

0

1

0

1

one copy has a permanent 1 here

4 copies

to other copies

X

ah, the Human Designer

Creativity ...

Arithmancy Magic ...

no tool can reinvent The Adder

...

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Fiddling with alu1

0.01

0.1

1

10

100

1 10 100 1000 10000

Ac

tual

siz

e i

n L

UT

s t

o u

pp

er

bo

un

d

Upper bound, LUTs

?halve

double

double

much less reconvergent fanout

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Symmetric functions?

• Symmetric functions have logarithmic depth

• Algebraic decomposition is not very good at discovering that

• F Wang and D L Dietmeyer, ““““Exploiting Near Exploiting Near Exploiting Near Exploiting Near Symmetry in Multilevel Logic SynthesisSymmetry in Multilevel Logic SynthesisSymmetry in Multilevel Logic SynthesisSymmetry in Multilevel Logic Synthesis””””. IEEE Trans. on CAD 17(9), pp. 772-781

• The notion of near symmetry

• An example very similar to our circuits: MCNC f51 + S8{4}

• In the benchmarks, nastiness seems to be independent of symmetry

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Biased representations?

• BDDs are IF-THEN-ELSE based

• ESOP synthesis is focused on XOR-AND

• Everything else is AND-NOT oriented

• The structure of representation often guides decomposition

• BDS: decomposition wrt. AND, XOR, MUX

• C Yang, V Singhal, M Ciesielski: ““““BDD Decomposition for BDD Decomposition for BDD Decomposition for BDD Decomposition for Efficient Logic Synthesis.Efficient Logic Synthesis.Efficient Logic Synthesis.Efficient Logic Synthesis.”””” 1999 IEEE International Conferenceon Computer Design (ICCD'99) p. 626

• C Yang, M Ciesielski, V Singhal: ““““BDS: a BDDBDS: a BDDBDS: a BDDBDS: a BDD----basedbasedbasedbased logiclogiclogiclogicoptimizationoptimizationoptimizationoptimization systemsystemsystemsystem....”””” Proceedings of the 37th conference on Design automation, p.92-97, June 05-09, 2000, Los Angeles, California

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Biased representations.

0.01

0.1

1

10

100

1 10 100 1000 10000

Ac

tua

ls

ize

in L

UT

sto

up

pe

rb

ou

nd

Upper bound, LUTs

alu1

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The beauty of BDS

• 4 classes under NPN-equivalence

• 2 of then essentially dependent on both inputs: x1+x2, x1⊕x2

• BDS can provide the negations for the NPN derivation

• BDS can decompose using any of the two NPN classes

• BDS is a “NPN-complete” decomposition

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To Do

• how come the experiments are incomplete…

• how does BDS perform on the LEKU benchmarks by Cong and Minkovich?

•what can we learn from newer benchmarks?

• can we take the BDS algorithms further…?

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Conclusions

•Contemporary logic synthesis, both academic and professional, can fail on circuits that are small and practical

•A part of this failure can be attributed to unequal handling of AND/OR and XOR operators in decomposition

Welcome to the years of Logic Synthesis II