Slide12 Counters
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Transcript of Slide12 Counters
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Sequential LogicCounters
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Flip-Flops: The Building Block
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Asynchronous Counters
async = events that DO NOT occur at thesame time
async counter = FFs within the counter
DO NOT have a common clock pulse
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Asynchronous Counters
async = events that DO NOT occur at thesame time
async counter = FFs within the counter
DO NOT have a common clock pulse
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Asynchronous Counters
async = events that DO NOT occur at thesame time
async counter = FFs within the counterDO NOT have a common clock pulse
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2-bit AsynchronousBinary Counter
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2-bit Asynchronous Binary Counter
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2-bit Asynchronous Binary
Counter
0
0
0
1
1
0
1
1
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3-bit Async Bin Counter
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3-bit Async Bin Counter
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3-bit Async Bin Counter
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Asynchronous Counter
a.k.a.Ripple Counter
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Propagational Delay
majord
isadvan
tage!
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Calculate the delay
Bewa
re
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Asynchronous DecadeCounters
Binary counters
count from 0 to 2n-1 (n=no. of FFs) What if ... you need to count just from 0 to 9?
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The Answer
Do partial decoding
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BCD Decade Counters
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74LS93(4-bit asynchronous binary counter)
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74LS93(4-bit asynchronous binary counter)
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74LS93(4-bit asynchronous binary counter)
CTR DIV 12
CCLK A
CCLK B
RO(1)
RO(2)
Q0 Q1 Q2 Q3
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That was async...
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Now, its time for
Synchronous counters
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Synchronous Counter
FFs in the counter are clocked at the sametime by a common clock pulse.
Lets begin with a 2-bit synchronous binarycounter...
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2-bit SynchronousBinary Counter
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Whats going on?
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What would we get?
delay is neglected for simplicity
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3-bit Synchronous Binary Counter
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4-Bit Sync Bin Counter
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4-bit Synchronous
Decade Counter
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Up/Down Sync Counters
progressing in either direction (up/down) may be called a bidirectional counter
0 1 2 3 4 5 4 3 2 3 4 5 6 7 6 5 etc...
up dn up dn
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Lets make one
(3-bit counter)
Q0: J0 = K0 = 1
Q1: J1 = K1 = (Q0 UP) + (Q0 DN)
Q2: J2 = K2 = (Q0 Q1 UP) + (Q0 Q1 DN)
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Lets make one
(3-bit counter)
Q0: J0 = K0 = 1
Q1: J1 = K1 = (Q0 UP) + (Q0 DN)
Q2: J2 = K2 = (Q0 Q1 UP) + (Q0 Q1 DN)
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Lets make one
(3-bit counter)
Q0: J0 = K0 = 1
Q1: J1 = K1 = (Q0 UP) + (Q0 DN)
Q2: J2 = K2 = (Q0 Q1 UP) + (Q0 Q1 DN)
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Design of SynchronousCounters
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General Model of aSequential Circuit
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Step 1: State Diagram
3-bit Gray code counter
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Step 2: Next-state Table
The next state is the state that the counter goesto from its present state upon the application of aclock pulse.
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Step 3: Flip-flopTransition Table
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Step 4: Karnaugh Maps
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Step 4: Karnaugh Maps
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Step 5: Logic Expressions forFF Inputs
K1 = Q2Q0
J0 = Q2Q1+Q2Q1 = Q2 Q1_ _
K0 = Q2Q1+Q2Q1 = Q2 Q1_ _
J1 = Q2Q0_
J2 = Q1Q0_
K2 = Q1Q0_ _
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Step 6: Counter Implementation
J0 = Q2Q1+Q2Q1 = Q2 Q1_ _
K0 = Q2Q1+Q2Q1 = Q2 Q1_ _
K1 = Q2Q0
J1 = Q2Q0
_J2 = Q1Q0
_
K2 = Q1Q0_ _
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