Slide 1 Digital Fundamentals CHAPTER 4 Boolean Algebra and Logic Simplification.
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Transcript of Slide 1 Digital Fundamentals CHAPTER 4 Boolean Algebra and Logic Simplification.
Slide 1
Digital FundamentalsDigital Fundamentals
CHAPTER 4 CHAPTER 4
Boolean Algebra and Logic SimplificationBoolean Algebra and Logic Simplification
Slide 3
Boolean Operations and ExpressionsBoolean Operations and Expressions
• AdditionAddition0 + 0 = 00 + 0 = 0
0 + 1 = 10 + 1 = 1
1 + 0 = 11 + 0 = 1
1 + 1 = 11 + 1 = 1
• MultiplicationMultiplication0 * 0 = 00 * 0 = 0
0 * 1 = 00 * 1 = 0
1 * 0 = 01 * 0 = 0
1 * 1 = 11 * 1 = 1
Slide 5
Laws Boolean Algebra Laws Boolean Algebra
• Commutative LawsCommutative Laws
• Associative LawsAssociative Laws
• Distributive LawDistributive Law
Slide 6
Laws of Boolean AlgebraLaws of Boolean Algebra
• Commutative Law of Addition:Commutative Law of Addition:A + B = B + AA + B = B + A
Slide 7
Laws of Boolean AlgebraLaws of Boolean Algebra
• Commutative Law of Multiplication:Commutative Law of Multiplication:A * B = B * AA * B = B * A
Slide 8
Laws of Boolean AlgebraLaws of Boolean Algebra
• Associative Law of Addition:Associative Law of Addition:A + (B + C) = (A + B) + CA + (B + C) = (A + B) + C
Slide 9
Laws of Boolean AlgebraLaws of Boolean Algebra
• Associative Law of Multiplication:Associative Law of Multiplication:A * (B * C) = (A * B) * CA * (B * C) = (A * B) * C
Slide 10
Laws of Boolean AlgebraLaws of Boolean Algebra
• Distributive Law:Distributive Law:
A(B + C) = AB + ACA(B + C) = AB + AC
Slide 21
Rules of Boolean AlgebraRules of Boolean Algebra
• Rule 10: A + AB = ARule 10: A + AB = A
AND Truth Table OR Truth Table
Slide 22
Rules of Boolean AlgebraRules of Boolean Algebra
• Rule 11:Rule 11: BABAA
AND Truth Table OR Truth Table
Slide 23
Rules of Boolean AlgebraRules of Boolean Algebra
• Rule 12: (A + B)(A + C) = A + BCRule 12: (A + B)(A + C) = A + BC
AND Truth Table OR Truth Table
Slide 25
DeMorgan’s TheoremsDeMorgan’s Theorems
• Theorem 1Theorem 1
• Theorem 2Theorem 2
YXXY
YXYX Remember: Remember:
““Break the bar, Break the bar, change the sign”change the sign”
Slide 26
Figure 4–16Figure 4–16 A logic circuit showing the development of the Boolean expression for the output.A logic circuit showing the development of the Boolean expression for the output.
Slide 27
Figure 4–16Figure 4–16 A logic circuit showing the development of the Boolean expression for the output.A logic circuit showing the development of the Boolean expression for the output.
Slide 29
Standard Forms of Boolean ExpressionsStandard Forms of Boolean Expressions
• The sum-of-product (SOP) formThe sum-of-product (SOP) formExample: X = AB + CD + EFExample: X = AB + CD + EF
• The product of sum (POS) formThe product of sum (POS) formExample: X = (A + B)(C + D)(E + F)Example: X = (A + B)(C + D)(E + F)
Slide 30
Figure 4–18Figure 4–18 Implementation of the SOP expression Implementation of the SOP expression ABAB + + BCDBCD + + ACAC..
Slide 31
Figure 4–19Figure 4–19 This NAND/NAND implementation is equivalent to the AND/OR in Figure 4–18. This NAND/NAND implementation is equivalent to the AND/OR in Figure 4–18.
Slide 32
Figure 4–19Figure 4–19 This NAND/NAND implementation is equivalent to the AND/OR in Figure 4–18.This NAND/NAND implementation is equivalent to the AND/OR in Figure 4–18.
Slide 36
Figure 4–23Figure 4–23 Adjacent cells on a Karnaugh map are those that differ by only one Adjacent cells on a Karnaugh map are those that differ by only one variable. Arrows point between adjacent cells.variable. Arrows point between adjacent cells.
Slide 37
Figure 4–24Figure 4–24 Example of mapping a standard SOP expression. Example of mapping a standard SOP expression.
Slide 46
Figure 4–35Figure 4–35 Example of mapping directly from a truth table to a Karnaugh map. Example of mapping directly from a truth table to a Karnaugh map.
Slide 47
Figure 4–36Figure 4–36 Example of the use of “don’t care” conditions to simplify an expression. Example of the use of “don’t care” conditions to simplify an expression.
Slide 48
Figure 4–37Figure 4–37 Example of mapping a standard POS expression. Example of mapping a standard POS expression.
Slide 54
Figure 4–43Figure 4–43 Illustration of groupings of 1s in adjacent cells of a 5-variable map. Illustration of groupings of 1s in adjacent cells of a 5-variable map.
Slide 57
Figure 4–45Figure 4–45 A VHDL program for a 2-input AND gate. A VHDL program for a 2-input AND gate.
Slide 58
VHDLVHDL
• VHDL OperatorsVHDL Operators
andand
oror
notnot
nandnand
nornor
xorxor
xnorxnor
• VHDL ElementsVHDL Elements
entityentity
architecturearchitecture
Slide 59
VHDLVHDL
• Entity StructureEntity Structure
Example:Example:
entityentity AND_Gate1 AND_Gate1 isis
port(port(A,BA,B:in bit::in bit:XX:out bit);:out bit);
end entity end entity AND_Gate1AND_Gate1
Slide 60
VHDLVHDL
• ArchitectureArchitecture
Example:Example:
architecturearchitecture LogicFunction of AND_Gate1 LogicFunction of AND_Gate1 isis
beginbegin
XX<=<=A A andand B B;;
end architecture end architecture LogicFunctionLogicFunction
Slide 62
Hardware Description Languages (HDL)Hardware Description Languages (HDL)
• Boolean Expressions in VHDLBoolean Expressions in VHDLANDAND X X <=<= A A andand B B;;
OROR X X <=<= A A oror B B;;
NOTNOT X X <=<= A A notnot B B;;
NANDNAND X X <=<= A A nandnand B B;;
NORNOR X X <=<= A A nornor B B;;
XORXOR X X <=<= A A xorxor B B;;
XNORXNOR X X <=<= A A xnorxnor B B;;
Slide 63
Figure 4–47Figure 4–47 Seven-segment display format showing arrangement of segments. Seven-segment display format showing arrangement of segments.
Slide 64
Figure 4–48Figure 4–48 Display of decimal digits with a 7-segment device. Display of decimal digits with a 7-segment device.
Slide 65
Figure 4–49Figure 4–49 Arrangements of 7-segment LED displays. Arrangements of 7-segment LED displays.
Slide 66
Figure 4–50Figure 4–50 Block diagram of 7-segment logic and display. Block diagram of 7-segment logic and display.
Slide 67
Figure 4–51Figure 4–51 Karnaugh map minimization of the segment-a logic expression. Karnaugh map minimization of the segment-a logic expression.
Slide 68
Figure 4–52Figure 4–52 The minimum logic implementation for segment a of the 7-segment display.The minimum logic implementation for segment a of the 7-segment display.
Slide 71
Figure 4–55. What is the Boolean expression for each of the logic gates?Figure 4–55. What is the Boolean expression for each of the logic gates?
Slide 72
Figure 4–56. What is the Boolean expression for each of the logic gates?Figure 4–56. What is the Boolean expression for each of the logic gates?
Slide 73
Figure 4–58. Derive a standard SOP and standard POS expression for each truth table.Figure 4–58. Derive a standard SOP and standard POS expression for each truth table.
Slide 74
Figure 4–59. Figure 4–59. Reduce the function in the truth table to its minimum SOP form by using a Karnaugh map.Reduce the function in the truth table to its minimum SOP form by using a Karnaugh map.
Slide 75
Figure 4–62. Example 4-21. Related Problem answer.Figure 4–62. Example 4-21. Related Problem answer.
Slide 76
Figure 4–63. Example 4-22. Related Problem answer.Figure 4–63. Example 4-22. Related Problem answer.
Slide 77
Figure 4–64. Example 4-23. Related Problem answer.Figure 4–64. Example 4-23. Related Problem answer.
Slide 78
Figure 4–65. Example 4-24. Related Problem answer.Figure 4–65. Example 4-24. Related Problem answer.