SLDO tests at CERN

RD53 Serial Powering meeting, 26. July 2019

https://indico.cern.ch/event/829670/

UMBERTO MOLINATI, AGATHE NIDRICHE, STELLA ORFANELLI, ALVARO PRADAS LUENGO, DOMINIK KOUKOLA

Outline

2

1. SLDO test chip measurements

Summary from test chip A (inl. Irradiation campaign)

Overvoltage protection

Undershunt protection

Low Power Mode => Alvaro

2. Wafer Probing with RD53A

SLDO measurements from 1500 chips

1. SLDO test chip A - August submission:Finished testing

Improved line regulation

Limits transient propagation to other chips

2. SLDO test chip B - November submission:Currently being tested

Limits maximum input voltage

Operation with low input current

Earlier start up

3. SLDO test chip C - February submission:Expected beginning of July

SLDO test chips overview

3

1. SLDO test chip A – August 2018 submission:Finished testing

• New bandgap scheme

• Overload protection (= Under shunt protection)

2. SLDO test chip B – November 2018 submission:Currently being tested

• Overvoltage protection

• Low power mode

• New start up circuitry

• Improvements in bandgap scheme

3. SLDO test chip C – February 2019 submission:Not tested yet

• Improvements in start up stability

Testchip A measurements

4

Irradiation measurement

• Irradiated one Shunt-LDO testchip A up to 600 Mrad at 0C in March

Chiller & dry air

X-ray machine

8 Keithleys

Dry airtube

Cooling chuck

X-ray source

5

Voltage trends over TID at Iin = 1.6A

98%

99%

100%

101%

102%

Relativ changes over Dose

Vout/Vref

96%

97%

98%

99%

100%

101%

102%

103%

104%

0 100 200 300 400 500 600

TID [Mrad]

Vin

6

Shunt-LDO is fully functional after 600Mrad:

Output behaviour is very stable Bandgap voltages are very stable

Variations of input behavior

(Voltage changes due to Iref Resistor=> Changed in newer versions)

0.49

0.5

0.51

0.52

0.53

0.54

0.55

0 100 200 300 400 500 600

Extr

acte

d S

lop

e [O

hm

]

Vin_slope

0.88

0.9

0.92

0.94

0.96

0.98

1

1.02

1.04

1.06

0 100 200 300 400 500 600

Extr

acte

d O

ffse

t [V

]

TID [Mrad]

Vin_offset

Extracting line parameters Vofs, R3 from Vin measurements

𝑉𝑖𝑛 = 𝑉𝑜𝑓𝑠 +𝑅3

1000∗ 𝐼𝑖𝑛

SlopeOffset

Extracted parameters change with TID: Slope decreases by ~30mOhm Offset increases by ~100mV

Summary of Shunt-LDO testchip A measurements

8

Basic measurements with ShuntLDO testchip A

• Line regulation improved significantly with new bandgap scheme

• Stronger thermal dependency due to internal Iref resistor than in RD53A => External resistor with testchip B

• Load regulation good performance

• Basic tests with undershunt (overload) protection performed

Irradiation campaign with ShuntLDO testchip A

• General performance is good (Factor 2, Load regulation, bandgap voltages)

• Decrease of Iref over TID

• High startup current and increase with TID Low startup current is critical for power efficient start up!

• Change in input voltage not expected to be that big => Further investigation necessary

Expected and improved with testchip B (external resistor & startup circuit)

Undershunt Protection(Overload Protection)

9

Reducing the shunt current by increasing load current

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

00.010.020.030.04

Vo

ltag

e [V

]

Shunt current = Input current – Load current [A]

Under shunt protection OFF

V_IN

Vout

Vref

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

00.010.020.030.04

Vo

ltag

e [V

]

Shunt current [A] = Input current – Load current [A]

Under shunt protection ON

V_IN

Vout

Vref

When under shunt condition detected Vref and Vout are being reduced Threshold current ~25 mA => ~2-3% of total current => To be considered for headroom

Total overload:Current necessary for SLDO circuit

0.8A

Overload pulse:1A for 1ms

Overload scenario with two chips in series

11

Two chips in series with same configuration Supply current = 0.8 A

Creating overload on one chip

=> Measured response with and without undershunt protection

0.8A

Measured 1ms overload pulse

Overload example with 1 ms overload

12

Overload example with 1 ms overload

13Overload protection decreases overload transients to propagate to other chips

Umberto Molinatti

Overvoltage Protection(Testchip B)

14

2. Limit < 2.0V

3. Too high I/T?

1. Early Startup

Line regulation - Overvoltage protection

15

1. Start up is very early (warm, unirradiated)2. OVP limits to ~1.8V

Due to low Vref_pre bandgap - as expected only 550mV3. At high I/T drop in Vin and Vout => seen before, but more pronounced in testchip B

• Vofs = 1.0V• Startup enabled• OVP on• Vref_ovp = Vrefpre

1. Early Startup

Vin

Vout

Overvoltage protection with different maximum voltages

16

Tested with different configured maximum voltages• Limiting Voltage = 3.33 * Vref_ovp

Overvoltage protection limits the maximum voltage very wellVariations in reference Voltage propagate proportional to maximum voltage!

High I/V/T

Waferprobing

17

SLDO measurements from Wafer Probing @ CERN Analyzed at 1500 chips from 17 wafers

Probed at CERN by L.M. Jara Casas

Focus only on SLDO measurements Done with Rext = 806, Riofs = 249k (=> Vofs ~ 1V)

Cuts shown are not a measure for production yield

=> Looking at SLDO performance here!

=> Not proposing cuts for SLDOs or for module production (=> different discussion)

Will show three different characteristics1. VDD & VIN measured with Iin = 0.6A (fast power up)

2. Extracted Slope and Offset

3. Startup current of VDD & VIN

18

from IV measurement

SLDO related wafer probing measurements

Two SLDO measurements:1. VIN + VDD @ 0.6A input current (per SLDO)

“Fast” jump from 0 to 0.6A2. IV curve (0 to 1A per SLDO)

Measured VIN+VDD+Vref “Slow ramp”: 50mA step every ~5s

Latest presented wafer probing results in RD53A testing meetings [M. Daas]:

https://indico.cern.ch/event/790616/contributions/3312331/attachments/1794073/2923758/2019-02-11_RD53Meeting_Waferprobing_cuts.pdf

https://indico.cern.ch/event/804870/contributions/3393333/attachments/1830094/2996823/2019-04-09_RD53Meeting_Special_waferprobing_statistics.pdf

Test procedure [M. Daas]

19

VDD measurement at Iin = 0.6A (fast power up)

20

Big difference between Analog and Digital => 33% less green chip for analog!

Mean VDD is 60 – 80 mV lower than 1.2V (as already seen)

VDD measurement at Iin = 0.6A (fast power up)

21

Big difference between Analog and Digital => 33% less green chip for analog!

Mean VDD is 60 – 80 mV lower than 1.2V (as already seen)

Bad Vref (and Vofs) Bad Vofs

VIN measurement at Iin = 0.6A (fast power up)

22

Again big difference between Analog and Digital => 21% less green chip for analog!

Mean VIN close to expected value of VIN = 1.48V

VIN measurement at Iin = 0.6A (fast power up)

23

Bad Vofs

Again big difference between Analog and Digital => 21% less green chip for analog!

Mean VIN close to expected value of VIN = 1.48V

Measurement at Iin = 0.6A (fast power up)

24

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

0 0.5 1 1.5 2

VD

DA

[V

]

VINA [V]

Analog

Bad Vofs

Bad Vref

Bad Vofs& Vref

Two bandgaps per SLDO => Four populations in VDD / VIN scatter plot

Both GoodFew with high ohmic behavior

IV curve measurements (slow ramp)

25

Measurement:

ShuntLDOs powered by independent channels

Slow steps: 50mA every ~5s

Not returning to zero

ShuntLDO Configuration:

Rext = 806

Riofs = 249k => Vofs≈1.0V

Slope and Offset Extraction:

Linear fit of measurement points 0.8A to 0.95A

Extracted Offsets

26

Again big difference between Analog and Digital => 23% less green chips for analog!

Extracted offset is 60-80 mV lower than expected (as already seen)

Sigma is around 45 mV (4 to 5%)

Extracted Offsets - Zoom in

27

Again big difference between Analog and Digital => 23% less green chips for analog!

Extracted offset is 60-80 mV lower than expected (as already seen)

Sigma is around 45 mV (4 to 5%)

Extracted Slope

28

Again big difference between Analog and Digital => 26% less green chips for analog!

Extracted slope is around 80 mΩ higher than expected (as already seen)

Sigma is around 35 mΩ (3 to 4%)

Extracted Slope – Zoom in

29

Again big difference between Analog and Digital => 26% less green chips for analog!

Extracted slope is around 80 mΩ higher than expected (as already seen)

Sigma is around 35 mΩ (3 to 4%)

Extracting the “startup current”

30

Definition:

Startup current is the first current where measured voltage passes threshold

Defined thresholds:

VDD => 1.0V

VIN => 1.4V

Vin threshold

VIND Istart = 0.45A

VINA Istart = 0.55A

Example

VIN start up current (“When does VIN pass 1.4V?”)

31

21% more late starting analog VINs than digital

33% more late starting analog VDDs than digital

Two peaks visible, one at 0.4A and one at 0.8A => Unclear why?

VDD start up current (“When does VDD pass 1.0V?”)

32

Comparing fast ramp up – slow ramp up

33

• Calculated difference between first 0.6A measurement and the respective point from IV curve measurement

Only small difference of 0.6A measurements with:

• Fast ramp up O(10 ms)

• Slow ramp up O(10 s)

Observation at I = 0A

34

Power supply settings:

VLimit = 2V

I = 0A

=> Small leakage current of power supply gives ~0.5V drop on RD53A

=> Seen consistently on chips

~0.5V

0A

Summary of analyzed wafer probing results Systematic differences in analog and digital SLDOs

Significantly more analog SLDOs start up later than digital SLDOs

=> Because of load difference? Ianalog = 0.4A vs Idigital = 0.1A

General “late” startup of bandgaps is already improved for RD53B

Slope and Offset differences to the expected values are as seen beforeSlope around 80 mΩ higher than expected

Offset around 60 to 80 mV lower than expected

Standard deviation of Slope and Offset is around 4 to 5%

SLDO performance, especially late startup, should be considered for RD53A module production!

35

Not fully understood yet

Summary Systematic differences in analog and digital SLDOs

Significantly more analog SLDOs start up later than digital SLDOs

=> Because of load difference? Ianalog = 0.4A vs Idigital = 0.1A

General “late” startup of bandgaps is already improved for RD53B

Slope and Offset differences to the expected values are as seen beforeSlope around 80 mΩ higher than expected

Offset around 60 to 80 mV lower than expected

Standard deviation of Slope and Offset is around 4 to 5%

SLDO performance, especially late startup, should be considered for RD53A module production!

36

Not fully understood yet

Thank you

37

Shunt-LDO regulator • Resistive behavior

• Provides constant voltage to the chip

• Input impedance, Vofs and Vref are configurable

38

𝑉𝑖𝑛 = 𝑉𝑜𝑓𝑠 +𝑅3

1000∗ 𝐼𝑖𝑛

𝑉𝑜𝑢𝑡 = 2 ∗ 𝑉𝑟𝑒𝑓

Relationships

IIN

𝑉𝑜𝑓𝑠

R3/1000

VIN

VOUT = 2 ∗ 𝑉𝑟𝑒𝑓

VOFS

VOUT

LDO ShuntVIN

Setting a working point• Choose Vofs and Slope (with external resistors)

=> For input behaviour

• Choose Vref=> For output behaviour

• Provide constant input current=> Shunt-LDO regulates input voltage accordingly

=> Should be higher than maximum expected load

39

𝑉𝑖𝑛 = 𝑉𝑜𝑓𝑠 +𝑅3

1000∗ 𝐼𝑖𝑛

𝑉𝑜𝑢𝑡 = 2 ∗ 𝑉𝑟𝑒𝑓

Relationships

1A

1.5V

1.0V Vout = 1.2 V = 2 ∗ 0.6 𝑉

Failures & hotspot

Normal operation

Chip2Chip1 VIN

I2

Chip2Chip1 VIN++

I1 + I2

Chip2Chip1 VIN≈0

I2 = 0

Open on one chip

1.5W

4 W

Short on one chip

Umberto Molinatti

Umberto Molinatti

Testchip A – Irradiation campaign

43

Trends of voltages and currents @Iin=1.6A

99%

100%

101%

102%

0 100 200 300 400 500 600

Relativ changes over Dose

Vpre

Parameters independent on Iref:=> Good performance=> No changes in future versions expected

• Change in Vout/Vref is +/- 1%:=> Equivalent to +/- 12mV Vout change

99%

100%

101%

102%

0 100 200 300 400 500 600

Vbg

99%

100%

101%

102%

0 100 200 300 400 500 600TID [Mrad]

Vout/Vref

0 Mrad 600 Mrad Delta

Vout/Vref 2.053 2.069 +0.80 %

Vbg 0.498 0.501 + 3 mV

Vpre 1.141 1.148 + 7mV

Reference values

Trends of voltages and currents @Iin=1.6A

90%

92%

94%

96%

98%

100%

102%

0 100 200 300 400 500 600

TID [Mrad]

Vofs

Vout

Iref_uA

Vref

45

Parameters dependent on Iref:• Iref decreases with irradiation (green)=> Expected due to change of internal resistor

• Voltages dependent on Iref follow same trend

• Except Vin, starts to increase with TID=> Not fully understood yet, under investigation

0 Mrad 600 Mrad Delta

Vin 1.804 1.860 +56 mV

Vout 1.204 1.126 -78 mV

Vref 0.587 0.544 - 43 mV

Vofs 1.005 0.959 - 46 mV

Iref_uA 4.037 3.742 - 0.3 uA

Reference values

96%

98%

100%

102%

104%

0 100 200 300 400 500 600

Vin

Looking closer at Vin

46

1.72

1.74

1.76

1.78

1.8

1.82

1.84

1.86

1.88

1.9

1.92

0 100 200 300 400 500 600

Inp

ut

volt

age

[Vin

]

TID [Mrad]

Vin adjusted for change in Vofs

Measured Vin

• Subtracted the change of Vofs from Vin=> To compare how it is expected with new versions (more stable Vofs)

• Absolute change of 100mV observed!

Trends of startup voltage and current - Measurement• Startup current is minimum current necessary to start proper regulation

=> Extracted from all line regulations last input voltage/current point where Vpre < 1.0V• Vpre is the crucial voltage that drives the start up behavior

Example:

0

0.5

1

1.5

2

0 0.5 1 1.5 2

Vo

ltag

es [

V]

Iin [A]

Line regulation for 0 Mrad

Vin

Vpre

Startupcurrent

Startup voltage

Note: The startup voltage is the input voltage, NOT the preregulator voltage47

Trends of startup voltage and current - Result

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

0 100 200 300 400 500 600

Thre

sho

ld c

urr

ent

[A]

TID [Mrad]

Startup current to Vpre reach > 1.0V

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

0 100 200 300 400 500 600

Thre

sho

ld v

olt

age

[V]

TID [Mrad]

Startup voltage for Vpre to reach >1.0V

48

=> High startup current and increase with TID expected in testchip A

• Startup voltage (right) compatible with simulations: Up to 1.4V expected after irradiation

Some discrepancies in LDO-mode => See next slide

• Startup current (left) without startup circuitry (Not in testchip A)

Want to start up with <0.5A!