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SKEE2263

Digital System Topic 2b

Power and Timing

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Power dissipation

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Each integrated circuit (IC) consumes power

PT = P

S + P

D

› PT = total power consumed by IC

› PS = static or quiescent power consumption

› PD = dynamic power consumption

Power Consumption

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TTL vs CMOS Power

Logic Type TTL CMOS

Static Power Large, depends on low or

high output

Very small

Dynamic Power ~0 Varies with Frequency

Typical quiescent power

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Total Power Consumption (74xx00)

0 Hz 1 MHz 100 MHz

TTL 15.8 mW 15.8 mW 15.8 mW

CMOS 100 µW 1.8 mW 180 mW

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TIMING ANALYSIS

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An important phase of digital systems design is Timing

Analysis

› Involves delay calculation for the various components and

subsystems.

Propagation delay is used to determine

› When outputs are valid

› The maximum speed of a combinational circuit

› The maximum frequency of a sequential circuit

Gate propagation delay is the time for a change on an

input of a gate to propagate to the output.

Introduction

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Propagation Delay

tpLH

V DD

V DD

Gnd

Gnd

50% 50%

90%

tpHL

10%

t r

50%

90%

50%

10%

t f

input

output

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tPHL

› Time for output to transition from high to low after a change in

input

tPLH

› Time for output to transition from low to high after a change in

input

tr (rise time)

› Time for output to change from low to high

tf (fall time)

› Time for output to change from high to low

Definitions

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Delay categories:

› Maximum Delay (max): Worst-case delay

› Typical Delay (typ): Mean delay

› Minimum Delay (min): Fastest possible

tpd

› Propagation delay = max(tPHL , tPHL)

Delay Categories

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DIY Find tPHL, tPLH and tpd for the signals given

IN (

volts)

OU

T (

volts)

t (ns)

1.0 ns per division

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Given: A logic circuit with multiple inputs and a single

output.

Given: A single transition on one of the inputs.

Determine: The time delay to propagate the transition on

the input to the output.

› Use the propagation delay specified for each gate in the path

between the input on which the transition occurred and the

output.

Simple Analysis

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Problem: Some circuits have more than one path from

an input to an output.

Critical Path: the path with the maximum delay, from any

input to any output.

› Why do we care about the critical path?

Solution:

› Analyze every possible delay path

or

› Use the Worst Case Analysis

Provides a conservative specification

Often sufficient

Critical Path

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Write worst case delay next to each logic gate

› Select maximum of tPLH and tPHL

Identify all input-output paths (i.e. all delay paths)

Calculate worst case delay for each path

› Summarize in table

Select worst case (i.e. maximum propagation delay)

Sum of Worst Cases (SWC) Analysis

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Example SWC

f

x 1

x 2

74LS04

74F04

74F08

74LS08

74F32

tPLH tPHL

min typ max min typ max

74LS04 0 9 15 0 10 14

74F04 2.4 3.7 6.0 1.5 3.2 5.4

74LS08 0 8 18 0 10 20

74F08 2.4 3.7 6.2 2.0 3.2 5.3

74F32 2.4 3.7 6.1 1.8 3.2 5.5

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Example SWC

f

x 1

x 2

74LS04

74F04

74F08

74LS08

74F32

tPLH tPHL

min typ max min typ max

74LS04 0 9 15 0 10 14

74F04 2.4 3.7 6.0 1.5 3.2 5.4

74LS08 0 8 18 0 10 20

74F08 2.4 3.7 6.2 2.0 3.2 5.3

74F32 2.4 3.7 6.1 1.8 3.2 5.5

TP = 32.1

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Example SWC

f

x 1

x 2

74LS04

74F04

74F08

74LS08

74F32

tPLH tPHL

min typ max min typ max

74LS04 0 9 15 0 10 14

74F04 2.4 3.7 6.0 1.5 3.2 5.4

74LS08 0 8 18 0 10 20

74F08 2.4 3.7 6.2 2.0 3.2 5.3

74F32 2.4 3.7 6.1 1.8 3.2 5.5

TP = 12.3

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Example SWC

f

x 1

x 2

74LS04

74F04

74F08

74LS08

74F32

tPLH tPHL

min typ max min typ max

74LS04 0 9 15 0 10 14

74F04 2.4 3.7 6.0 1.5 3.2 5.4

74LS08 0 8 18 0 10 20

74F08 2.4 3.7 6.2 2.0 3.2 5.3

74F32 2.4 3.7 6.1 1.8 3.2 5.5

TP = 26.1

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Example SWC

f

x 1

x 2

74LS04

74F04

74F08

74LS08

74F32

tPLH tPHL

min typ max min typ max

74LS04 0 9 15 0 10 14

74F04 2.4 3.7 6.0 1.5 3.2 5.4

74LS08 0 8 18 0 10 20

74F08 2.4 3.7 6.2 2.0 3.2 5.3

74F32 2.4 3.7 6.1 1.8 3.2 5.5

TP = 27.3

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Example SWC

Input Output Delay

X1 F 32.1

X1 F 12.3

X2 F 26.1

X2 F 27.3

Worst Case Propagation Delay = 32.1

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Quartus II Timing Simulation

Notice the delay in the output

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Glitches

Y

A

S

B

2:1 MUX Y = B for S = 1 Y = A for S = 0

0.2

0.4

0.4

0.5

A

S B

Y

S

“Glitch” is due to delay of inverter

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JUST A TOUCH OF VLSI

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Have an appreciation why we needed to convert from

AND-OR to NAND-NAND, OR-AND to NOR-NOR

Understand the effect fan-in and fan-out

Why Go Very Low Level?

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CMOS Inverter

NMOS: Turns on when input = 0

PMOS: Turns on when input = 0

CMOS inverter is built using 2 transistors.

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CMOS NOR

CMOS NOR is built using only 4 transistors.

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CMOS NAND

CMOS NAND is also built using only 4 transistors.

Even though it looks similar to CMOS NOR, CMOS NAND is faster due to different characteristics of NMOS and PMOS

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CMOS AND, OR

AND must be built using NAND + NOT

6 transistors

OR must be built using NOR + NOT

› 6 transistors

XOR, XNOR

› More, much more…

Hopefully, now you appreciate why we go to all the

trouble of converting to all NANDs gates …

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Gate Switching Behavior

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Fan-out: number of inputs connected to an output

In units of minimum-sized inverters

The delay of a gate is proportional to its output capacitance. The more

inputs gate 1 has to drive, the more time it need to arrive at the correct

voltage.

Gate Delay due to Fan-Out

1

3

2

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Fan-in = number of inputs to a gate

tpHL rises very quickly as gate capacitance and resistance increase

Gate Delay due to Fan-In

1 3 5 7 9 fan-in

0.0

1.0

2.0

3.0

4.0 t p

( n

s e c )

t pHL

t p

t pLH linear

quadratic

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You will look at the MSI design. How to use standard

devices to realise digital circuitry.

What’s Next